Search Results (836)

The integration of a pixelated Fabry–Pérot filter array onto the image sensor enables on-chip snapshot multispectral imaging, significantly reducing the size and weight of conventional spectral imaging equipment. However, a traditional Fabry–Pérot cavity, based on metallic or dielectric layers, exhibits a narrow bandwidth, which restricts their utility in broader applications. In this work, we propose novel Fabry–Pérot filter structures that employ dielectric thin films for phase modulation, enabling single-peak filtering across a broad operational wavelength range from 400 nm to 1100 nm. The proposed structures are easy to fabricate and compatible with complementary metal-oxide-semiconductor (CMOS) image sensors. Moreover, the structures show low sensitivity to oblique incident angles of up to 30° with minimal wavelength shifts. This advanced Fabry–Pérot filter design provides a promising pathway for expanding the operational wavelength of snapshot spectral imaging systems, thereby potentially extending their application across numerous related fields. Full article

High parasitic capacitance from poly-insulator-poly capacitors in complementary metal oxide semiconductor (CMOS) processes presents a major bottleneck to achieving high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) in imaging systems. This study proposes a Phase-Adjustable SAR ADC that addresses this limitation through a reconfigurable architecture. The design utilizes a phase-adjustable logic unit to switch between a conventional SAR mode for high-speed operation and a noise-shaping (NS) SAR mode for high-resolution conversion, actively suppressing in-band quantization noise. An improved SAR logic unit facilitates the insertion of an adjustable phase while concurrently achieving an 86% area reduction in the core logic block. A prototype was fabricated and measured in a 0.35-µm CMOS process. In conventional mode, the ADC achieved a 7.69-bit effective number of bits at 2 MS/s. By activating the noise-shaping circuitry, performance was significantly enhanced to an 11.06-bit resolution, corresponding to a signal-to-noise-and-distortion ratio (SNDR) of 68.3 dB, at a 125 kS/s sampling rate. The results demonstrate that the proposed architecture effectively leverages the trade-off between speed and accuracy, providing a practical method for realizing high-performance ADCs despite the inherent limitations of non-ideal passive components. Full article

In order to solve the problem of the efficiency reduction and complex manufacturing of traditional grating couplers under environmental temperature fluctuations, a Si₃N₄ high-efficiency grating coupler integrating a distributed Bragg reflector (DBR) and thermo-optical tuning layer is proposed. In this paper, the double-layer DBR is used to make the down-scattered light interfere with other light and reflect it back into the waveguide. The finite difference time domain (FDTD) method is used to simulate and optimize the key parameters such as grating period, duty cycle, incident angle and cladding thickness, achieving a coupling efficiency of −1.59 dB and a 3 dB bandwidth of 106 nm. In order to further enhance the temperature stability, the amorphous silicon (a-Si) thermo-optical material layer and titanium metal serpentine heater are embedded in the DBR. The reduction in coupling efficiency caused by fluctuations in environmental temperature is compensated via local temperature control. The simulation results show that within the wide temperature range from −55 °C to 150 °C, the compensated coupling efficiency fluctuation is less than 0.02 dB, and the center wavelength undergoes a blue shift. This design is compatible with complementary metal-oxide-semiconductor (CMOS) processes, which not only simplifies the fabrication process but also significantly improves device stability over a wide temperature range. This provides a feasible and efficient coupling solution for photonic integrated chips in non-temperature-controlled environments, such as optical communications, data centers, and automotive systems. Full article

Improving the transient response performance is a critical challenge in low-dropout regulator (LDO) design. This paper proposes a novel on-chip capacitor-less LDO based on substrate technology implemented in an SMIC (Semiconductor Manufacturing International Corporation) 0.18 μm CMOS (complementary metal oxide semiconductor technology) process. Central to this innovation is a fast response loop between the PMOS driver’s body and gate, which leverages the body effect to enhance driver control without complex bulk-driven techniques. The proposed LDO achieves a quiescent current of 4.5 μA, an efficiency of $88\%$, an overshoot/undershoot of $12\mathrm{mV}/22\mathrm{mV}$, and a settling time of 1.2 μs. The comparative analysis confirms that this structure increases the maximum load current and reduces the loop response time relative to those for conventional LDOs. These results validate a significant improvement in the transient performance, marking an important advance in integrated voltage regulator technology. Full article

Sea surface roughness (SSR) retrieval is a frontier topic in the field of ocean remote sensing, and SSR retrieval based on multi angle, passive, visible spectrum remote sensing images has been proven to have potential applications. Traditional multi angle retrieval models ignored the nonlinear relationship between radiation and digital signals, resulting in low accuracy in SSR retrieval using visible spectrum remote sensing images. Therefore, we analyze the transmission characteristics of signals and random noise in sea surface imaging, establish signals and noise transmission models for typical sea surface imaging visible spectrum remote sensing systems using Complementary Metal Oxide Semiconductor (CMOS) and Time Delay Integration-Charge Coupled Device (TDI-CCD) sensors, and propose a model for SSR retrieval using multi angle passive visible spectrum remote sensing images. The proposed model can effectively suppress the noise behavior in the imaging link and improve the accuracy of SSR retrieval. Simulation experiments show that when simulating the retrieval of multi angle visible spectrum images obtained using CMOS or TDI-CCD imaging systems with four SSR levels of 0.02, 0.03, 0.04, and 0.05, the proposed model relative errors using two angles are decreased by 4.0%, 2.7%, 2.3%, and 2.0% and 6.5%, 4.3%, 3.7%, and 3.2%, compared with the relative errors of the model without considering noise behavior, which are 7.0%, 6.7%, 7.8%, and 9.0% and 9.5%, 8.3%, 9.0%, and 10.2%. When using more fitting data, the relative errors of the model were decreased by 5.0%, 2.7%, 2.5%, and 2.0% and 7.0%, 5.0%, 4.3%, and 3.2%, compared with the relative errors of the model without considering noise behavior, which are 8.5%, 7.0%, 8.0%, and 9.4%, and 10.0%, 8.7%, 9.3%, and 10.0%. Full article

Resistive switching (RS) phenomena are nowadays one of the most studied topics in the area of microelectronics. It can be observed in Metal–Insulator–Metal (MIM) structures that are the basis of resistive switching random-access memories (RRAMs). In the case of commercial use of RRAMs, it is beneficial that the applied materials would have to be compatible with Complementary Metal-Oxide-Semiconductor (CMOS) technology. Fabricating methods of these materials can determine their stoichiometry and structural composition, which can have a detrimental impact on the electrical performance of manufactured devices. In this study, we present the influence of the Ar/N₂ ratio during reactive magnetron sputtering of titanium nitride (TiN) electrodes on the resistive switching behavior of MIM devices. We used silicon oxide (SiOx) as a dielectric layer, which was characterized by the same properties in all fabricated MIM structures. The composition of TiN thin layers was controlled by tuning the Ar/N₂ ratio during the deposition process. The fabricated conductive materials were characterized in terms of chemical and structural properties employing X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) analysis. Structural characterization revealed that increasing the Ar content during the reactive sputtering process affects the crystallite size of the deposited TiN layer. The resulting crystallite sizes ranged from 8 Å to 757.4 Å. The I-V measurements of fabricated devices revealed that tuning the Ar/N₂ ratio during the deposition of TiN electrodes affects the RS behavior. Our work shows the importance of controlling the stoichiometry and structural parameters of electrodes on resistive switching phenomena. Full article

Integrating two-dimensional transition-metal dichalcogenides with graphene is attractive for low-power memory and neuromorphic hardware, yet sequential wet transfer leaves polymer residues and high contact resistance. We demonstrate a complementary metal–oxide–semiconductor (CMOS)-compatible, transfer-free route in which an atomically thin amorphous MoS₂ precursor is RF-sputtered directly onto chemical vapor-deposited few-layer graphene and crystallized by confined-space sulfurization at 800 °C. Grazing-incidence X-ray reflectivity, Raman spectroscopy, and X-ray photoelectron spectroscopy confirm the formation of residue-free, three-to-four-layer 2H-MoS₂ (roughness: 0.8–0.9 nm) over 1.5 cm × 2 cm coupons. Lateral MoS₂/graphene devices exhibit reproducible non-volatile resistive switching with a set transition (SET) near +6 V and an analogue ON/OFF ≈2.1, attributable to vacancy-induced Schottky-barrier modulation. The single-furnace magnetron sputtering + sulfurization sequence avoids toxic H₂S, polymer transfer steps, and high-resistance contacts, offering a cost-effective pathway toward wafer-scale 2D memristors compatible with back-end CMOS temperatures. Full article

Electrochemical sensing arrays enable the spatial study of dopamine levels throughout brain slices, the diffusion of electroactive molecules, as well as neurotransmitter secretion from single cells. The integration of complementary metal-oxide semiconductor (CMOS) devices in the development of electrochemical sensing devices enables large-scale parallel recordings, providing beneficial high-throughput for drug screening studies, brain–machine interfaces, and single-cell electrophysiology. In this paper, an electrochemical sensor capable of recording at 40,000 frames per second using a CMOS sensor array with 1024 electrochemical detectors and a custom field-programmable gate array data acquisition system is detailed. A total of 1024 on-chip electrodes are monolithically integrated onto the designed CMOS chip through post-CMOS fabrication. Each electrode is paired with a dedicated transimpedance amplifier, providing 1024 parallel electrochemical sensors for high-throughput studies. To support the level of data generated by the electrochemical device, a powerful data acquisition system is designed to operate the sensor array as well as digitize and transmit the output of the CMOS chip. Using the presented electrochemical sensing system, both dopamine and hydrogen peroxide diffusions across the sensor array are successfully recorded at 40,000 frames per second across the 32 × 32 electrochemical detector array. Full article

Precise time interval generation is a cornerstone of modern measurement, automation, and distributed control systems, particularly within Internet of Things (IoT) architectures. This paper presents the design, implementation, and evaluation of a low-cost and high-precision time interval generator based on Complementary Metal-Oxide Semiconductor (CMOS) logic counters (Integrated Circuit (IC) IC 7493 and IC 4017) and inverter-based crystal oscillators (IC 74LS04). The proposed system enables frequency division from 1 MHz down to 1 Hz through a cascade of binary and Johnson counters, enhanced with digitally controlled multiplexers for output signal selection. Unlike conventional timing systems relying on expensive Field-Programmable Gate Array (FPGA) or Global Navigation Satellite System (GNSS)-based synchronization, this approach offers a robust, locally controlled reference clock suitable for IoT nodes without network access. The hardware is integrated with Arduino and ESP32 microcontrollers via General-Purpose Input/Output (GPIO) level interfacing, supporting real-time timestamping, deterministic task execution, and microsecond-level synchronization. The system was validated through Python-based simulations incorporating Gaussian jitter models, as well as real-time experimental measurements using Arduino’s micros() function. Results demonstrated stable pulse generation with timing deviations consistently below ±3 µs across various frequency modes. A comparative analysis confirms the advantages of this CMOS-based timing solution over Real-Time Clock (RTC), Network Time Protocol (NTP), and Global Positioning System (GPS)-based methods in terms of local autonomy, cost, and integration simplicity. This work provides a practical and scalable time reference architecture for educational, industrial, and distributed applications, establishing a new bridge between classical digital circuit design and modern Internet of Things (IoT) timing requirements. Full article

In advanced Complementary Metal-Oxide-Semiconductor (CMOS) technologies, where diminished feature sizes amplify radiation-induced soft errors, the optimization of fault-tolerant circuit designs requires detailed transistor-level analysis of reliability–performance trade-offs. As a fundamental building block in digital systems and critical data paths, the 2:1 multiplexer, widely used in data-path routing, clock networks, and reconfigurable systems, provides a critical benchmark for assessing radiation-hardened design methodologies. In this context, this work aims to analyze the power consumption, area overhead, and delay of 2:1 multiplexer designs under transient fault conditions, employing the CMOS and Differential Cascode Voltage Switch Logic (DCVSL) logic styles and mitigation strategies. Electrical simulations were conducted using 32 nm high-performance predictive technology, evaluating both the original circuit versions and modified variants incorporating three mitigation strategies: transistor sizing, D-Cells, and C-Elements. Key metrics, including power consumption, delay, area, and radiation robustness, were analyzed. The C-Element and transistor sizing techniques ensure satisfactory robustness for all the circuits analyzed, with a significant impact on delay, power consumption, and area. Although the D-Cell technique alone provides significant improvements, it is not enough to achieve adequate levels of robustness. Full article

When a CMOS (Complementary Metal–Oxide–Semiconductor) imaging system operates at a high frame rate or a high line rate, the exposure time of the imaging system is limited, and the acquired image data will be dark, with a low signal-to-noise ratio and unsatisfactory sharpness. Therefore, in order to improve the visibility and signal-to-noise ratio of remote sensing images based on CMOS imaging systems, this paper proposes a low-light remote sensing image enhancement method and a corresponding ZYNQ (Zynq-7000 All Programmable SoC) design scheme called the BGIR (Bilateral-Guided Image Restoration) algorithm, which uses an improved multi-scale Retinex algorithm in the HSV (hue–saturation–value) color space. First, the RGB image is used to separate the original image’s H, S, and V components. Then, the V component is processed using the improved algorithm based on bilateral filtering. The image is then adjusted using the gamma correction algorithm to make preliminary adjustments to the brightness and contrast of the whole image, and the S component is processed using segmented linear enhancement to obtain the base layer. The algorithm is also deployed to ZYNQ using ARM + FPGA software synergy, reasonably allocating each algorithm module and accelerating the algorithm by using a lookup table and constructing a pipeline. The experimental results show that the proposed method improves processing speed by nearly 30 times while maintaining the recovery effect, which has the advantages of fast processing speed, miniaturization, embeddability, and portability. Following the end-to-end deployment, the processing speeds for resolutions of 640 × 480 and 1280 × 720 are shown to reach 80 fps and 30 fps, respectively, thereby satisfying the performance requirements of the imaging system. Full article

The monolithic integration of III-V semiconductors with silicon (Si) is a critical step toward advancing optoelectronic and photonic devices. In this work, we present GaAs nanoheteroepitaxy (NHE) on Si nanotips using gas-source molecular beam epitaxy (GS-MBE). We discuss the selective growth of fully relaxed GaAs nanoislands on complementary metal oxide semiconductor (CMOS)-compatible Si(001) nanotip wafers. Nanotip wafers were fabricated using a state-of-the-art 0.13 μm SiGe Bipolar CMOS pilot line on 200 mm wafers. Our investigation focuses on understanding the influence of the growth conditions on the morphology, crystalline structure, and defect formation of the GaAs islands. The morphological, structural, and optical properties of the GaAs islands were characterized using scanning electron microscopy, high-resolution X-ray diffraction, and photoluminescence spectroscopy. For samples with less deposition, the GaAs islands exhibit a monomodal size distribution, with an average effective diameter ranging between 100 and 280 nm. These islands display four distinct facet orientations corresponding to the {001} planes. As the deposition increases, larger islands with multiple crystallographic facets emerge, accompanied by a transition from a monomodal to a bimodal growth mode. Single twinning is observed in all samples. However, with increasing deposition, not only a bimodal size distribution occurs, but also the volume fraction of the twinned material increases significantly. These findings shed light on the growth dynamics of nanoheteroepitaxial GaAs and contribute to ongoing efforts toward CMOS-compatible Si-based nanophotonic technologies. Full article

The neurobiology of chronic pain is complex and multifaceted, intertwining with the mesocorticolimbic system to regulate the behavioral and perceptional response to adverse stimuli. Specifically, the ventral tegmental area (VTA), the dopaminergic hub of the reward pathways located deep within the midbrain, is crucial for regulating the release of dopamine (DA) throughout the central nervous system (CNS). To better understand the nuances among chronic pain, VTA response, and therapeutics, implementing progressive approaches for mapping and visualizing the deep brain in real time during nociceptive stimulation is crucial. In this study, we utilize a fluorescence imaging platform with a genetically encoded calcium indicator (GCaMP6s) to directly visualize activity in the VTA during acute nociceptive stimulation in both healthy adult mice and adult mice with partial nerve ligation (PNL)-induced neuropathic pain. We also investigate the visualization of the analgesic properties of morphine. Deep brain imaging using our self-fabricated µ-complementary metal–oxide–semiconductor (CMOS) imaging device allows the tracking of the VTA’s response to adverse stimuli. Our findings show that nociceptive stimulation is associated with a reduction in VTA fluorescence activity, supporting the potential of this platform for visualizing pain-related responses in the central nervous system. Additionally, treatment with morphine significantly reduces the neuronal response caused by mechanical stimuli and is observable using the CMOS imaging platform, demonstrating a novel way to potentially assess and treat neuropathic pain. Full article

This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm²/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm²/mg at 300 K, dropping to 6 MeV cm²/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 10⁻⁴ A/μm at 300 K to 4.65 × 10⁻⁵ A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K. Full article

The scope of this study was to evaluate the response of Ce-doped gadolinium aluminum gallium garnet (GAGG:Ce) crystalline scintillator under medical X-ray irradiation for medical imaging applications. A 10 × 10 × 10 mm³ crystal was irradiated at X-ray tube voltages ranging from 50 kVp to 150 kVp. The crystal’s compatibility with several commercially available optical photon detectors was evaluated using the spectral matching factor (SMF) along with the absolute efficiency (AE) and the effective efficiency (EE). In addition, the energy-absorption efficiency (EAE), the quantum-detection efficiency (QDE) as well as the zero-frequency detective quantum detection efficiency DQE(0) were determined. The crystal demonstrated satisfactory AE values as high as 26.3 E.U. (where 1 E.U. = 1 μW∙m⁻²/(mR∙s⁻¹)) at 150 kVp, similar, or in some cases, even superior to other cerium-doped scintillator materials. It also exhibits adequate DQE(0) performance ranging from 0.99 to 0.95 across all the examined X-ray tube voltages. Moreover, it showed high spectral compatibility with commonly used photoreceptors in modern day such as complementary metal–oxide–semiconductors (CMOS) and charge-coupled-devices (CCD) with SMF values of 0.95 for CCD with broadband anti-reflection coating and 0.99 for hybrid CMOS blue. The aforementioned properties of this scintillator material were indicative of its superior efficiency in the examined medical energy range, compared to other commonly used scintillators. Full article