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Keywords = latch-adder

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16 pages, 4236 KB  
Article
Ternary Logic Design Based on Novel Tunneling-Drift-Diffusion Field-Effect Transistors
by Bin Lu, Hua Qiang, Dawei Wang, Xiaojing Cui, Jiayu Di, Yuanhao Miao, Zhuofan Wang and Jiangang Yu
Nanomaterials 2025, 15(16), 1240; https://doi.org/10.3390/nano15161240 - 13 Aug 2025
Viewed by 634
Abstract
In this paper, a novel Tunneling-Drift-Diffusion Field-Effect Transistor (TDDFET) based on the combination of the quantum tunneling and conventional drift-diffusion mechanisms is proposed for the design of ternary logic circuits. The working principle of the TDDFET is analyzed in detail. Then, the device [...] Read more.
In this paper, a novel Tunneling-Drift-Diffusion Field-Effect Transistor (TDDFET) based on the combination of the quantum tunneling and conventional drift-diffusion mechanisms is proposed for the design of ternary logic circuits. The working principle of the TDDFET is analyzed in detail. Then, the device is packaged as a “black box” based on the table lookup method and further embedded into the HSPICE platform using the Verilog-A language. The basic unit circuits, such as the Standard Ternary Inverter (STI), Negative Ternary Inverter (NTI), Positive Ternary Inverter (PTI), Ternary NAND gate (T-NAND), and Ternary NOR gate (T-NOR), are designed. In addition, based on the designed unit circuits, the combinational logic circuits, such as the Ternary Encoder (T-Encoder), Ternary Decoder (T-Decoder), and Ternary Half Adder (T-HA), and the sequential logic circuits, such as the Ternary D-Latch and edge-triggered Ternary D Flip-Flop (T-DFF), are built, which has important significance for the subsequent investigation of ternary logic circuits. Full article
(This article belongs to the Section Nanoelectronics, Nanosensors and Devices)
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14 pages, 3929 KB  
Article
Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology
by Recep Emir, Dilek Surekci Yamacli, Serhan Yamacli and Sezai Alper Tekin
Electronics 2024, 13(15), 2993; https://doi.org/10.3390/electronics13152993 - 29 Jul 2024
Cited by 2 | Viewed by 1535
Abstract
The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are [...] Read more.
The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the average power consumption of the considered logic circuits employing GNRFETs was 78.6% lower than those built using classical Si-based MOSFETs. Similarly, the delay advantage of the logic circuits employing GNRFETs was calculated to be 53.2% lower than those using Si-based MOSFET counterparts. In addition, a deep learning model was developed to model both the power consumption and the propagation delay of GNRFET-based logic inverters. As the second result, it was demonstrated that the developed deep learning model could accurately represent the power consumption and delay of GNRFET-based logic circuits with the coefficient of determination (R2) values in the range of 0.86 and 0.99. Full article
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17 pages, 2957 KB  
Article
All-Optical 4-Bit Parity Generator and Checker Utilizing Carrier Reservoir Semiconductor Optical Amplifiers
by Amer Kotb, Kyriakos E. Zoiros, Chunlei Guo and Wei Chen
Electronics 2024, 13(12), 2314; https://doi.org/10.3390/electronics13122314 - 13 Jun 2024
Cited by 1 | Viewed by 1449
Abstract
This research explores the forefront of all-optical data processing systems through the utilization of carrier reservoir semiconductor optical amplifiers (CR-SOAs). Recent advancements have showcased the successful design and implementation of CR-SOA-based combinational systems, incorporating pivotal elements like half adders, half subtractors, digital-to-analog converters, [...] Read more.
This research explores the forefront of all-optical data processing systems through the utilization of carrier reservoir semiconductor optical amplifiers (CR-SOAs). Recent advancements have showcased the successful design and implementation of CR-SOA-based combinational systems, incorporating pivotal elements like half adders, half subtractors, digital-to-analog converters, latches, header recognition, and header processors. These breakthroughs signify a significant stride towards the realization of faster and more efficient optical logic systems. This study delves into the distinctive characteristics of CR-SOA-based Mach–Zehnder interferometer (MZI) functioning as an XOR gate, emphasizing their transformative potential in information processing. By integrating them into the architecture of an all-optical 4-bit parity generator and checker, the research underscores the practicality of CR-SOA technology in all-optical processing, offering unprecedented speeds and facilitating enhanced data processing capabilities at a remarkable speed of 120 Gb/s return-to-zero pulses. In evaluating the performance of the proposed scheme, the research employs the quality factor metric. This assessment not only yields quantitative insights into the efficacy of CR-SOA-based logic systems but also establishes a critical benchmark for their practical implementation. The study further explores the impact of key data signals and CR-SOA parameters on this metric. The outcomes demonstrate the ability of the CR-SOA-based MZI to cascade and form more intricate logic circuits, thereby highlighting the versatility and potential of this innovative approach in advancing the landscape of all-optical data processing. Full article
(This article belongs to the Section Circuit and Signal Processing)
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12 pages, 3187 KB  
Article
Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications
by Jin-Fa Lin, Cheng-Yu Chan and Shao-Wei Yu
Electronics 2019, 8(12), 1429; https://doi.org/10.3390/electronics8121429 - 30 Nov 2019
Cited by 8 | Viewed by 5200
Abstract
In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder [...] Read more.
In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz. Full article
(This article belongs to the Section Circuit and Signal Processing)
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