Search Results (11)

With the development of embedded electronic devices, energy consumption has become a significant design issue in modern systems-on-a-chip. Conventional SRAMs cannot maintain data after powering turned off, limiting their use in applications such as battery-powered smartphone devices that require non-volatility and no leakage current. RRAM devices are recently used extensively in applications such as self-charging wireless sensor networks and storage elements, owing to their intrinsic non-volatility and multi-bit capabilities, making them a potential candidate for mitigating the von Neumann bottleneck. We propose a new RRAM-based hybrid memristor model incorporated with a permanent magnet. The proposed design (1T2R) was simulated in Cadence Virtuoso with a 1.5 V power supply, and the finite-element approach was adopted to simulate magnetization. This model can retain the data after the power is off and provides fast power on/off transitions. It is possible to charge a smartphone battery without an external power source by utilizing a portable charger that uses magnetic induction to convert mechanical energy into electrical energy. In an embedded smartphone self-charging device this addresses eco-friendly concerns and lowers environmental effects. It would lead to the development of magnetic field-assisted embedded portable electronic devices and open the door to new types of energy harvesting for RRAM devices. Our proposed design and simulation results reveal that, under usual conditions, the magnet-based device provide a high voltage to charge a smartphone battery. Full article

As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing. Full article

In this manuscript, strontium barium titanate (BST) ferroelectric memory film materials for applications in the feasibility of applying to non-volatile RAM devices were obtained and compared. Solutions were synthesized with a proportional ratio and through the deposition of BST films on titanium nitride/silicon substrates using the sol–gel method, using rapid thermal annealing for defect repair and re-crystallization processing. The crystallization structure and surface morphology of annealed and as-deposited BST films were obtained by XPS, XRD, and SEM measurements. Additionally, the ferroelectric and resistive switching properties for the memory window, the maximum capacitance, and the leakage current were examined for Al/BST/TiN and Cu/BST/TiN structure memory devices. In addition, the first-order reaction equation of the decay reaction behavior for the BST film RRAM devices in the reset state revealed that $r=0.19{[O^{2-}]}^1$. Finally, the Cu/BST/TiN and Al/BST/TiN structures of the ferroelectric BST films RRAM devices exhibited good memory window properties, bipolar switching properties, and non-volatile properties for applications in non-volatile memory devices. Full article

Vector–matrix multiplication (VMM), which dominates the computational workload in neural networks, accounts for over 99% of all operations, particularly in Convolutional Neural Networks (CNNs). These operations, consisting of multiply-and-accumulate (MAC) functions, are straightforward but demand massive parallelism, often involving billions of operations per layer. This computational demand negatively affects processing time, energy consumption, and memory bandwidth due to frequent external memory access. To efficiently address these challenges, this paper investigates the implementation of a full neural network for image classification, using TensorFlow as a software baseline, and compares it with a hardware counterpart mapped onto resistive RAM-based crossbar arrays, a practical implementation of the memristor concept. By leveraging the inherent ability of RRAM crossbars to perform VMMs in a single step, we demonstrate how RRAM-based neural networks can achieve efficient in-memory analog computing. To ensure realistic and practical results, the hardware implemented utilizes RRAM memory cells characterized through silicon measurements. Furthermore, the design exclusively considers positive weights and biases to minimize the area overhead, resulting in a lightweight hardware solution. This approach achieves an energy consumption of 190 fJ/MAC operation for the crossbar array, highlighting its efficiency in power-constrained applications despite a drop in the prediction confidence of 27.5% compared to the software approach. Full article

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages. Full article

One of the important features of Resistive RAM (RRAM) is its conductance modulation, which makes it suitable for neuromorphic computing systems. In this paper, the conductance modulation of Oxide-based RAM (OxRAM) devices is evaluated based on experimental data to reveal its inherent analog synaptic behavior. A test chip made of a classical 1T-1R elementary memory array is used to demonstrate the conductance modulation. Using an array of cells, as opposed to an isolated cell, allows to catch temporal as well as spatial variabilities. Thus, the multiple resistance levels capability of OxRAMs is assessed in a more realistic context. Two different programming techniques are used to program the OxRAM cells. The first approach leverages on RESET (RST) voltage control. The second approach relies on compliance current control during the SET operation. In both approaches, although multiple resistance levels can be easily obtained, it is demonstrated that a successful implementation of a reliable conductance modulation scheme mainly depends on the ability to precisely control the impact of variability on the different conductance levels obtained after the programming operation. Full article

This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cell consumes less power in standby mode and has excellent switching performance during power on/off speed. It also has better read and write stability and significantly improves noise tolerance than the conventional asymmetrical 6T SRAM and other NVSRAM cells. The power dissipation is evaluated at different technology nodes. Hence, our proposed symmetric 8T3R NVSRAM cell is suitable to use at low power and embedded applications. Full article

Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache. Full article

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues. Full article

State-of-the-art IoT technologies request novel design solutions in edge computing, resulting in even more portable and energy-efficient hardware for in-the-field processing tasks. Vision sensors, processors, and hardware accelerators are among the most demanding IoT applications. Resistance switching (RS) two-terminal devices are suitable for resistive RAMs (RRAM), a promising technology to realize storage class memories. Furthermore, due to their memristive nature, RRAMs are appropriate candidates for in-memory computing architectures. Recently, we demonstrated a CMOS compatible silicon nitride (SiN_x) MIS RS device with memristive properties. In this paper, a report on a new photodiode-based vision sensor architecture with in-memory computing capability, relying on memristive device, is disclosed. In this context, the resistance switching dynamics of our memristive device were measured and a data-fitted behavioral model was extracted. SPICE simulations were made highlighting the in-memory computing capabilities of the proposed photodiode-one memristor pixel vision sensor. Finally, an integration and manufacturing perspective was discussed. Full article

RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation without the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell programming current of 1T-1R HfO₂-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 μs, respectively. Full article