Search Results (455)

Electrochemical biosensors have reached a high degree of analytical maturity; however, only a small portion of laboratory demonstrations actually progress to commercial products. In this review, we looked non-analytically at the factors which are in place with respect to this translational gap, specifically looking into supply chain design, scale-up manufacturing strategy, regulatory–quality, and more. Based on a wide range of academic and industrial literature, the paper considers how decisions about what kind of material to use, especially for material that recognizes living things, conductive material made from ink, and the material that is the actual product being made, can make a big difference in whether the product can be reproduced easily, if it will stay stable for a long time, and if it is allowed according to the rules. This review compares the dominant manufacturing paradigms—roll-to-roll printing, and semiconductor-derived microfabrication—and shows how the respective strengths and limitations match the different targets, costs, and risk class. This is more about making manufacturing an upstream optimization problem than treating processes as defects and quality as assurance, rather than making it an upstream optimization problem. And it does this by looking at some other big pathways for regulations in the U.S., EU, and China as well, where we get to see how those differences in classification requirements, what kind of proofs you should have, and different ways about running those quality management systems affect how quickly things can come out after developing them, and what your flexibility with customers is like when those products are already out there in the world. The study looks at some case studies: disposable glucose strips, cartridge-based blood analyzers, and new continuous monitoring systems are used to show how the exact same electrochemical ideas can result in very different commercialization issues based on the clinical context and system integration. Synthesizing those angles creates a review that can give a system level map of matching research design to industrial and regulatory realities, with the goal of making it easier for electrochemical biosensors to go from lab prototypes to ready-for-market diagnostic tools. Full article

Semiconductor manufacturing is a resource and energy-intensive industry with a substantial environmental footprint. To address the footprint, we present a methodology for quantifying the environmental impact of semiconductor unit processes using the Environmental Footprint 3.1 Life Cycle Impact Assessment (LCIA) framework, focusing on identifying improvement opportunities in process steps with less sensitivity to defects. We apply this methodology to backside wet cleaning by proposing an alternative single-wafer process that adopts ozonated chemistries. The assessment used primary data from imec’s 300 mm pilot line. Results show that the proposed process reduces the total environmental footprint by 55% compared to the baseline Spin Cleaning with Repetitive use of Ozonated water and Diluted HF process. Key reductions include 67% less electricity for cleaning, 59% less HF use, and a 31% reduction in ultrapure water consumption. When scaled to a facility producing N28 Logic wafers at 50,000 wafer starts per month, with 46 backside clean steps per processed wafer, the process achieves annual savings of approximately 4 million kWh of electricity and 28 million liters (28,000 m³) of tap water per year. A sensitivity analysis revealed that replacing fossil-based electricity with hydroelectric power further reduces total environmental impacts by up to 63%, emphasizing the benefit of combining process innovation with renewable energy sourcing. Full article

Dicing is an important process in the packaging segment of the semiconductor manufacturing process, and due to the high hardness and brittleness of 4H-SiC wafers, they are prone to crack propagation and severe chipping during the dicing process. To reduce chipping defects, this study investigates the effects of key process parameters on the chipping behavior of 4H-SiC wafers, as well as the associated chipping formation and material removal mechanisms during dicing. Firstly, a spindle current measurement scheme was designed to indirectly reflect changes in grinding force during the cutting process, and the change in the cutting process in a single pass was analyzed. Secondly, experiments controlling single-factor variables were designed to explore the influence of laws of process parameters, including depth of cut, spindle speed, feed speed, and the dicing blade parameter, abrasive grain size, on the quality of chipping, and the optimal process parameters were obtained. Thirdly, the morphology of the 4H-SiC cutting contact arc area, front–back chipping, and sidewalls was analyzed in order to investigate the chipping formation and material removal mechanism. This study contributes to a fundamental understanding of material removal mechanisms during the cutting of 4H-SiC wafers and other advanced semiconductor materials and provides guidance for optimizing cutting process parameters. Full article

Alumina ceramics used in semiconductor plasma environments require high densification, microstructural homogeneity, and stable performance under increasingly aggressive processing conditions. However, systematic studies linking slurry processing parameters to the plasma resistance of alumina ceramics remain limited. In this study, the effects of slurry preparation parameters—specifically milling and aging—and sintering atmosphere on the densification, mechanical strength, and plasma etching resistance of slip-cast alumina ceramics were systematically investigated. Optimal dispersion stability was achieved under 12 h milling and 12–24 h aging conditions, resulting in homogenized green body packing and a high relative sintered density exceeding 99%. Mechanical strength and plasma resistance were strongly influenced by slurry aging and sintering atmosphere. Specimens aged for 48 h and sintered under a low oxygen partial pressure (N₂ at 1.0 L/min) exhibited the highest flexural strength and significantly improved resistance to SF₆/Ar plasma etching, with reduced etch depth and suppressed surface roughening. These results demonstrate that coordinated slurry processing and sintering atmosphere control is an effective strategy for designing high-reliability, plasma-resistant alumina ceramics for high-demand semiconductor manufacturing environments. Full article

The sustained interest in efficient, low-cost, and straightforward-to-manufacture lasers has prompted intense research into organic semiconductor laser emitter materials in recent decades. The main focus of this research is determining the optical gains and losses of amplified spontaneous emission (ASE) in order to describe materials by their amplification signature. A method that has been used for decades as the standard technique for determining gain characteristics is the variable-stripe-length (VSL) method. The success of the VSL method has led to the development of further measurement techniques. These techniques provide a detailed insight into the nature of optical amplification. One such method is the scattered emission profile (SEP) method. In this study, we present an extension of the SEP method, the Diffracted Emission Profile (DEP) method. The DEP method is based on the detection of ASE by partial decoupling of waveguide modes diffracted by a one-dimensional grating integrated into a planar waveguide. Diffraction causes a proportion of the intensity to exit the waveguide, transferring the growth and decay process of the waveguide mode to the transverse mode profile of the diffracted mode. In the present article, an approach to determine the amplification signature of an organic copolymer is presented, utilizing partial decoupled radiation. Full article

Nanostructured semiconductors have emerged as transformative materials for enhancing the efficiency of waste heat-to-electricity conversion through thermoelectric (TE) processes. By altering structural features at the nanoscale, these materials can simultaneously reduce lattice thermal conductivity and optimize electronic transport properties, thereby significantly improving the thermoelectric figure of merit (ZT). Recent studies have demonstrated that introducing periodic twin planes in III–V semiconductor nanowires can achieve a tenfold reduction in thermal conductivity while maintaining excellent electrical performance. Similarly, Pb_1−xGe_xTe alloys, through controlled spinodal decomposition, form stable nanostructures that maintain low thermal conductivity even after thermal cycling, crucial for high-temperature applications. Enhancing electrical properties is another key advantage of nanostructuring. PbTe-based materials, when heavily doped and engineered with nanoscale inclusions, have achieved a ZT of approximately 1.9 and a thermoelectric efficiency of around 12% over a 590 K temperature difference. Single-walled carbon nanotubes (SWCNTs) also show strong correlations between their electronic structure and thermoelectric conductivity, highlighting their potential for next-generation devices. Two-dimensional silicon–germanium (Si_xGe_γ) compounds offer ultra-low lattice thermal conductivity and high Seebeck coefficients, providing a promising pathway for future TE applications. Despite these advancements, challenges remain, particularly regarding scalability and integration into existing energy recovery systems. Techniques such as focused ion beam milling and solution-based synthesis of porous nanostructures are being developed to fabricate high-performance materials on a commercial scale. Moreover, integrating nanostructured semiconductors into real-world systems, such as automotive exhaust heat recovery units, requires improvements in material durability, fabrication efficiency, and device compatibility. In conclusion, nanostructured semiconductors offer a powerful route for enhancing waste heat-to-electricity conversion. Their ability to decouple electrical and thermal transport at the nanoscale opens new opportunities for high-efficiency, sustainable energy harvesting technologies. Continued research into scalable manufacturing techniques, material stability, and system integration is essential to fully unlock their potential for commercial thermoelectric applications. Full article

Industrial aluminum-block heating processes exhibit nonlinear dynamics, substantial time delays, and stringent requirements for fault detection and diagnosis, especially in semiconductor manufacturing and other high-precision electronic processes, where slight temperature deviations can accelerate device degradation or even cause catastrophic failures. To address these challenges, this study presents a digital twin-based intelligent heating platform for aluminum blocks with a dual-artificial-intelligence framework (dual-AI) for control and diagnosis, which is applicable to multi-port aluminum-block heating systems. The system enables real-time observation and simulation of high-temperature operational conditions via virtual-real interaction. The platform precisely regulates a nonlinear temperature control system with a prolonged time delay by integrating a conventional proportional–integral–derivative (PID) controller with a Levenberg–Marquardt-optimized backpropagation (LM-optimized BP) neural network. Simultaneously, a relay is employed to sever the connection to the heater, thereby simulating an open-circuit fault. Throughout this procedure, sensor data are gathered simultaneously, facilitating the creation of a spatiotemporal time-series dataset under both normal and fault conditions. A one-dimensional convolutional neural network (1D-CNN) is trained to attain high-accuracy fault detection and localization. PID+LM-BP achieves a response time of about 200 s in simulation. In the 100 °C to 105 °C step experiment, it reaches a settling time of 6 min with a 3 °C overshoot. Fault detection uses a 0.38 °C threshold defined based on the absolute minute-to-minute change of the 1-min mean temperature. Full article

As semiconductor process nodes shrink to 3 nm and beyond, traditional optical proximity correction (OPC) and resolution enhancement technologies (RETs) can no longer meet the high patterning precision needs of advanced chip manufacturing due to the sub-wavelength lithography limits. Inverse lithography technology (ILT), a key part of computational lithography, has become a critical solution for these issues. From an EDA industry perspective, this review provides an original and systematic summary of ILT’s development and applications, which helps integrate the scattered research into a clear framework for both academic and industrial use. Compared with traditional OPC, the latest ILT has three main advantages: (1) better patterning accuracy, as a result of the precise optical models that fix complex optical issues (like diffraction and interference) in advanced lithography systems; (2) a wider process window, as it optimizes mask designs by working backwards from the target wafer patterns, making lithography more stable against process changes; and (3) stronger adaptability to new lithography scenarios, such as High-NA EUV and extended DUV nodes. This review first explains ILT’s working principles (the basic concepts, mathematical formulae, and main methods like level-set and pixelated approaches) and its development history, highlighting key events that boosted its progress. It then analyzes ILT’s current application status in the industry (such as hotspot fixing, full-chip trials, and EUV-era use) and its main bottlenecks: a high computational complexity leading to long runtime, difficulties in mask manufacturing, challenges in model calibration, and a conservative market that slows large-scale adoption. Finally, it discusses promising future directions, including hybrid ILT-OPC-SMO strategies, improving model accuracy, AI/ML-driven design, GPU acceleration, multi-beam mask writer improvements, and open-source data to solve data shortage problems. By combining the latest research and industry practices, this review fills the gap of comprehensive ILT summaries that cover the principles, progress, applications, and prospects. It helps readers fully understand ILT’s technical landscape and offers practical insights for solving the key challenges, thus promoting ILT’s industrial use in advanced chip manufacturing. Full article

In semiconductor packaging and microelectronic manufacturing, inkjet printing technology is widely employed in critical processes such as conductive line fabrication and encapsulant dot deposition. However, dynamic printing defects, such as missing droplets and splashing can severely compromise circuit continuity and device reliability. Traditional inspection methods struggle to detect such subtle and low-contrast defects. To address this challenge, we propose MCHB-DETR, a novel lightweight defect detection framework based on RT-DETR, aimed at improving product yield in inkjet printing for semiconductor packaging. MCHB-DETR features a lightweight backbone with enhanced multi-level feature extraction capabilities and a hybrid encoder designed to improve cross-scale and multi-frequency feature fusion. Experimental results on our inkjet dataset show a 29.1% reduction in parameters and a 36.7% reduction in FLOPs, along with improvements of 3.1% in mAP@50 and 3.5% in mAP@50:95. These results demonstrate its superior detection performance while maintaining efficient inference, highlighting its strong potential for enhancing yield in semiconductor packaging. Full article

This paper proposes a grating Moiré fringe signal compensation method based on Variational Mode Decomposition (VMD) to address signal errors in grating encoders. VMD decomposes Moiré fringe signals into multiple amplitude-modulated and frequency-modulated components, and realizes noise compensation through parameter optimization and signal reconstruction. The Multi-Strategy Particle Swarm Optimization (MSPSO) enhances optimization performance via adaptive inertia weight adjustment and chaotic perturbation, solving the problems of mode mixing or over-decomposition caused by blind parameter selection in traditional VMD. A hardware-software co-design test system based on ZYNQ FPGA is developed, which optimally allocates tasks between the Processing System and Programmable Logic, resolving issues of large data volume and long computation time in traditional systems. The compensation scheme provides excellent signal processing performance. The experimental tests on random periodic signals, triangular waves and square waves with different duty cycles have demonstrated the robustness of this scheme. After compensation, the output signal exhibits excellent sinuosity and orthogonality, with harmonic components and noise in the frequency domain almost negligible. It provides a practical solution for high-precision measurement in ultra-precision machining, semiconductor manufacturing, and automated control. Full article

Tin selenide (SnSe) is a sustainable, lead-free IV–VI semiconductor whose layered orthorhombic crystal structure induces pronounced electronic and phononic anisotropy, enabling diverse energy-related functionalities. This review systematically summarizes recent progress in understanding the structure–property–processing relationships that govern SnSe performance in thermoelectric and optoelectronic applications. Key crystallographic characteristics are first discussed, including the temperature-driven Pnma–Cmcm phase transition, anisotropic band and valley structures, and phonon transport mechanisms that lead to intrinsically low lattice thermal conductivity below 0.5 W m⁻¹ K⁻¹ and tunable carrier transport. Subsequently, major synthesis strategies are critically compared, spanning Bridgman and vertical-gradient single-crystal growth, spark plasma sintering and hot pressing of polycrystals, as well as vapor- and solution-based thin-film fabrication, with emphasis on process windows, stoichiometry control, defect chemistry, and microstructure engineering. For thermoelectric applications, directional and temperature-dependent transport behaviors are analyzed, highlighting record thermoelectric performance in single-crystal SnSe at hi. We analyze directional and temperature-dependent transport, highlighting record thermoelectric figure of merit values exceeding 2.6 along the b-axis in single-crystal SnSe at ~900 K, as well as recent progress in polycrystalline and thin-film systems through alkali/coinage-metal doping (Ag, Na, Cu), isovalent and heterovalent substitution (Zn, S), and hierarchical microstructural design. For optoelectronic applications, optical properties, carrier dynamics, and photoresponse characteristics are summarized, underscoring high absorption coefficients exceeding 10⁴ cm⁻¹ and bandgap tunability across the visible to near-infrared range, together with interface engineering strategies for thin-film photovoltaics and broadband photodetectors. Emerging applications beyond energy conversion, including phase-change memory and electrochemical energy storage, are also reviewed. Finally, key challenges related to selenium volatility, performance reproducibility, long-term stability, and scalable manufacturing are identified. Overall, this review provides a process-oriented and application-driven framework to guide the rational design, synthesis optimization, and device integration of SnSe-based materials. Full article

With the rapid development of semiconductor manufacturing technology, methods to effectively control the production process, reduce variation in the manufacturing process, and improve the yield rate represent important competitive factors for wafer factories. Wafer bin maps, a method for characterizing wafer defect patterns, provide valuable information for engineers to quickly identify potential root causes through accurate pattern recognition. Vision-based deep learning approaches rely on visual patterns to achieve robust performance. However, they rarely exploit the rich semantic information embedded in defect descriptions, limiting interpretability and generalization. To address this gap, we propose YOLO-LA, a lightweight prototype-based vision–language alignment framework that integrates a pretrained frozen YOLO backbone with a frozen text encoder to enhance wafer defect recognition. A learnable projection head is introduced to map visual features into a shared embedding space, enabling classification through cosine similarity Experimental results on the WM-811K dataset demonstrate that YOLO-LA consistently improves classification accuracy across different backbones while introducing minimal additional parameters. In particular, YOLOv12 achieves the fastest speed while maintaining competitive accuracy, whereas YOLOv10 benefits most from semantic prototype alignment. The proposed framework is lightweight and suitable for real-time industrial wafer inspection systems. Full article

In an era of rapid technological advancements and growing necessity for effective power management systems, the significance of silicon Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs) in contemporary power electronics is more critical than ever. This review explores the advancements in silicon MOSFET technology through the lens of Design Technology Co-Optimization (DTCO). By integrating design and process technology strategies, DTCO optimizes power, performance, area, and cost (PPAC) metrics, addressing the limitations of traditional scaling methods. The manuscript presents an exhaustive analysis of the foundational principles of MOSFET technology, the progression of DTCO, and its implications on critical design metrics. The inclusion of machine learning techniques enhances the DTCO process, enabling vast simulations and efficient design iterations, which are crucial for navigating the complexities of advanced semiconductor device physics. Empirical evidence from TCAD simulations augmented by machine learning insights demonstrates the effectiveness of DTCO in enhancing device performance, reliability, and manufacturing yield. This review emphasizes the significance of DTCO and machine learning in addressing contemporary challenges and influencing the future trajectory of silicon MOSFET technology. Full article

Ultra-precision single-point diamond turning (SPDT) remains the core process for fabricating optical-grade surfaces with nanometric roughness and sub-micrometer form accuracy. However, machining hard-to-cut or brittle materials such as high-entropy alloys, metals, ceramics, and semiconductors is limited by severe tool wear, high cutting forces, and brittle fracture. To overcome these challenges, a new generation of non-conventional assisted and hybrid SPDT platforms has emerged, integrating multiple physical fields, including mechanical, thermal, magnetic, chemical, or cryogenic methods, into the cutting zone. This review comprehensively summarizes recent advances in hybrid non-conventional assisted SPDT platforms that combine two or more assistive techniques such as ultrasonic vibration, laser heating, magnetic fields, plasma or gas shielding, ion implantation, and cryogenic cooling. The synergistic effects of these dual-field platforms markedly enhance machinability, suppress tool wear, and extend ductile-mode cutting windows, enabling direct ultra-precision machining of previously intractable materials. Recent key case studies are analyzed in terms of material response, surface integrity, tool life, and implementation complexity. Comparative analysis shows that hybrid SPDT can significantly reduce surface roughness, extend diamond tool life, and yield optical-quality finishes on hard-to-cut materials, including ferrous alloys, composites, and crystals. This review concludes by identifying major technical challenges and outlining future directions toward optimal hybrid SPDT platforms for next-generation ultra-precision manufacturing. Full article

Semiconductor wafer manufacturing is one of the most complex and data-intensive processes in the industry, encompassing the front-end (FEOL), middle-end (MOL), and back-end (BEOL) stages, involving thousands of interdependent processes. Each stage can introduce potential variability, thereby reducing yield, making metrology and inspection crucial for process control. However, due to capacity, cost, and destructive testing constraints, exhaustive metrology for every wafer or die is impractical. Therefore, this study aims to introduce sampling strategies that have evolved to balance the accuracy, risk, and efficiency of measurement allocation. This review presents a literature review of static, adaptive, and dynamic sampling and discusses recent intelligent sampling techniques. The results show that traditional static sampling provides fixed, rule-based inspection schemes that ensure comparability and compliance but lack responsiveness to process variations. Adaptive sampling introduces flexibility, allowing measurement density to be adjusted based on detected drift, anomalies, or statistical control limits. Building on this, dynamic sampling represents a paradigm shift towards predictive, real-time decision-making driven by machine learning, risk analysis, and digital twin integration. The dynamic framework continuously assesses process uncertainties and prioritizes metrology to maximize information gain, thereby significantly reducing metrology workload without impacting yield or quality. Static, adaptive, and dynamic sampling together constitute a continuous evolution from deterministic control to self-optimizing intelligence. As semiconductor nodes move towards sub-3 nm, this intelligent sampling technology is crucial for maintaining yield, cost competitiveness, and process flexibility in autonomous, data-centric wafer fabs. Full article