Search Results (60)

This paper presents the Goddard RISC-V (GRV) a compact, portable, and highly customizable fault-tolerant 32-bit RISC-V processor, specifically designed for embedded space applications. The design integrates advanced fault-tolerance mechanisms to mitigate arbitrary Single Event Transient (SET) and Single Event Upset (SEU) errors while ensuring data integrity. Importantly, fault tolerance is achieved entirely at the design level, eliminating the need for SEU-hardened semiconductor processes, custom cell libraries, or specialized back-end tools. The implementation prioritizes portability and resource efficiency, enabling compatibility with various FPGA and ASIC technologies. This initiative aims to provide NASA with a suite of portable, modular, and scalable alternatives to proprietary solutions. These solutions are designed for broad adaptability across multiple platforms, such as compact scientific instruments, miniaturized deep-space technologies, CubeSats, control and automation systems, and other applications constrained by low-resource processing environments. Full article

This paper presents a systematic methodology for time-domain modeling of three-phase power transformers aimed at electromagnetic transient analysis in shipboard and embedded electrical systems. Accurate modeling of transformers in such environments is critical, as naval power systems are subject to strict electromagnetic compatibility (EMC) requirements and are particularly susceptible to fast transients caused by switching operations, fault events, and nonlinear loads operating in confined and isolated grids. The proposed approach combines the Vector Fitting (VF) algorithm with Clarke modal decomposition to obtain stable, passive, and causal rational approximations of the frequency-dependent admittance matrix over a wide frequency range. The admittance matrix is first identified from frequency-domain measurements or simulations, capturing the transformer’s terminal behavior across multiple frequency sub-bands. Clarke’s transformation is then applied to decouple the three-phase system into independent modal components—namely the zero-sequence and positive-sequence modes, reducing the original multi-phase problem to a set of independent single-phase systems. This modal decoupling significantly improves computational efficiency without sacrificing accuracy, as each mode can be fitted and simulated independently. Full article

This study presents a TCAD model of a SiGe HBT designed for high-speed data transfer, with a cutoff frequency of 246.5 GHz and a β-value up to 416.7. Comprehensive single-event transient (SET) irradiation simulations were performed by injecting charges at different junctions with various angles. The influence of SET on data transfer was further evaluated at circuit level by loading the SET model from TCAD simulation into a high-speed laser diode driver circuit. Hence, this work employed a collector dummy structure in the designed HBT to build radiation-hardened devices. Simulation results indicate significant mitigation of the single-event transient current, which could be reduced to 10%, compared with non-hardened devices. Full article

The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single-Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel “Electrical Masking Window” (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. The experimental results over some featured benchmarks demonstrate a speedup of more than 25,000× compared with SPICE while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaining scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF, DEF, LIB, or SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows. Full article

Soft errors and Hardware Trojans (HTs) constitute major reliability concerns, and in combination they can pose an even greater threat to circuit security. The main aim of this research is to develop and implement a reliability-based HT and to identify the optimal regions for its injection, enabling the creation of challenging benchmarks for evaluating detection techniques. In this context, a reliability-based HT is designed and evaluated using different components to achieve the required time overhead. Next, a method that combines the generation and propagation of Single-Event Transients (SETs), while accounting for both masking effects and the design’s timing constraints, is employed to efficiently identify the most vulnerable and critical gates. The sensitive gates selected for HT insertion exhibit 50–70% vulnerability to soft errors. At the same time, their insertion and the resulting path delay overhead must not violate the design’s timing constraints, and the additional area must remain below 10% of the total area. These three conditions ensure that the inserted HTs remain stealthy and, therefore, challenging to detect. The experimental results demonstrate that selecting this category of gates is highly effective, as it leads to a significant increase in the number of soft errors and, consequently, aggravates circuit vulnerability with minimal impact on the design. On average, the targeted gates exhibit a 130% increase in sensitivity, and the overall Soft Error Rate (SER) increases by 78%, confirming the importance of providing robust benchmarks to combat potential attacks of this kind. Full article

Semiconductor technologies are susceptible to radiation effects. The particle incidence in susceptible areas of an integrated circuit (IC) can generate physical interactions capable of producing errors. This paper predicts the IC cross sections for Single Event Effects. The cross section is a metric that provides an IC’s susceptibility to radiation. It deals with particle source interaction and physical design volumes. This work evaluates the IC cross section, exploring the physical design characteristics of susceptible regions in logic gates. It explores particles with low LET, identifying the charge collection areas. Also, the heavy ions are used to evaluate the critical cross section range. Distinct benchmark circuits were simulated to characterize sensitivity trends. The influence of circuit input conditions along with cells’ susceptibility reveals significant findings. The results indicate a difference up to ten times between low- and high-energy particles. Consequently, predicting the IC cross section at an early stage of the design flow is essential, especially for electronics devices used in radiation environments. Full article

To balance the quantity of heat generated and consumed, thermal energy storage systems are crucial for power plants and district heating systems. Particularly when phase transitions and pressure variations are not adequately covered in the existing literature, their work frequently takes place under complicated, changing temperature and fluid dynamic settings. The goal of this research is to create a thermodynamic model that incorporates the effects of steam condensation, steam injection, and heating failures to describe the transient behaviour of temperature and pressure in pressure vessels containing single-phase and two-phase fluids. To account for nonlinear, temperature-dependent steam properties, as well as initial and boundary constraints, the study proposes energy balance models for hot water and saturated steam cases. Numerical simulations evaluating sensitivity to parameter changes are presented alongside analytical solutions for isochoric and isobaric systems. The model also includes direct steam injection heating and the use of a heat exchanger. It explains the changes in temperature and pressure that occur in thermal energy storage systems over time, including significant events such as steam cushion collapse and condensate drainage. According to the sensitivity analysis, the main factors influencing the system’s safety limitations and transient dynamic phenomena are thermal power, heat exchanger capacity, and thermal insulation efficiency. The proposed thermodynamic model closes a major gap in the literature by providing reliable predictions of the transient behavior needed for the safe design and reliable operation of pressure vessels utilized for heat storage in district heating networks. This model can be used by engineers and researchers to optimize system design and steer clear of risky operational situations. Full article

This study investigates the impact of the self-heating effect (SHE) on single-event transient (SET) sensitivity in triple-layer stacked nanosheet transistors, using technology computer-aided design (TCAD) simulations. The results demonstrate that SHE significantly elevates the channel lattice temperature under DC bias, leading to notable degradation in DC performance metrics, including the drive current (I_ON) and the on/off current ratio. By employing a finer time resolution in the AC simulation, we observed that the device reaches thermal equilibrium on a picosecond timescale. Crucially, SHE is found to exacerbate SET sensitivity markedly. Compared to simulations without SHE, the presence of self-heating increases both the peak transient current and the collected charge at the drain terminal following heavy-ion strikes. Furthermore, the transient response is shown to depend on the thermal history; longer pre-strike heating times amplify the SET peak magnitude, whereas longer cooling times attenuate it. These findings underscore the critical importance of co-optimizing thermal management and radiation hardening in the design of advanced nanosheet technologies. Full article

Low-dropout regulators (LDOs) are critical modules in aerospace electronic systems. However, they are susceptible to single-event transient effects, which can impact the stability of the power system. Currently, almost all aerospace LDOs employ analog design to achieve robust output current characteristics. In this paper, three LDO architectures including analog LDO, digital LDO, and hybrid LDO are investigated, and a novel multi-loop hybrid LDO featuring analog proportional and digital integral control is proposed. A load detection module is introduced to allow the analog loop to operate independently under light-load conditions, thereby eliminating limit cycle oscillation (LCO) issues. In addition, a falling edge detection module is implemented to accelerate the transient response of the circuit. Three LDO circuits are designed using a 28 nm CMOS process, and their single-event transient responses are compared using double-exponential current pulse simulations. The results show that the proposed hybrid LDO exhibits the strongest transient response and best immunity to single-event effects under heavy-load conditions, achieving an efficiency of 99.975%. Full article

Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability Function (VF) derived from Verilog fault injection. This framework guides targeted Engineering Change Orders (ECOs), such as clock-net remapping, re-routing, and the selective insertion of SET filters, within a reproducible open-source flow (Yosys, OpenROAD, OpenSTA). A new analytical Soft Error Rate (SER) model for clock trees is also proposed, which decomposes contributions from the root, intermediate levels, and leaves, and is calibrated by SPICE-measured propagation probabilities, area, and particle flux. When coupled with throughput, this model yields a frequency-aware system-level Bit Error Rate (${BER}_{sys}$). The methodology was validated on a First-In First-Out (FIFO) memory, demonstrating a significant vulnerability reduction of approximately 3.35× in READ mode and 2.67× in WRITE mode. Frequency sweeps show monotonic decreases in both clock-tree vulnerability and ${BER}_{sys}$ at higher clock frequencies, a trend attributed to temporal masking and throughput effects. Cross-node SPICE characterization between 65 nm and 28 nm reveals a technology-dependent effect: for the same injected charge, the 28 nm process produces a shorter root-level pulse, which lowers the propagation probability relative to 65 nm and shifts the optimal clock-tree partition. These findings underscore the framework’s key innovations: a technology-independent, early-stage VF for ranking critical clock nets; a clock-tree SER model calibrated by measured propagation probabilities; an ECO loop that converts VF insights into concrete hardening actions; and a fully reproducible open-source implementation. The paper’s scope is architectural and pre-layout, with extensions to broader circuit classes and a full electrical analysis outlined for future work. Full article

This paper presents a comprehensive register transfer-level (RTL) fault injection study targeting the program counter (PC) of the LEON3 processor, a SPARC V8-compliant core widely used in safety-critical and radiation-prone embedded applications. Using the enhanced NETFI+ framework, over four million faults, including single-event upsets (SEUs), multiple-bit upsets (MBUs), and single-event transients (SETs), were systematically injected into the PC across all pipeline stages. The analysis reveals that early stages, particularly Fetch (FE), Decode (DE), Register Access (RA), and Execute (EX), are highly sensitive to SEU and MBU faults. The propagation of errors detected in the two early stages of the pipeline (FE and DE) is classified with an important percentage of halt execution and timeout traps. Intermediate stages, such as RA and EX, exhibited a higher incidence of silent data corruption and halt execution, while the Memory (ME) and Exception (XC) stages demonstrated greater resilience through fault masking. SET faults were mostly transient and masked, though they occasionally resulted in control flow anomalies. In addition to error classification, detailed trap and exception analysis was performed to characterize fault-induced failure mechanisms. The findings underscore the need for pipeline-stage-specific hardening strategies and highlight the value of simulation-based fault injection for early design validation in safety-critical embedded processors. Full article

This work investigates the effects of radiation on FinFET-based full adders, which are crucial components of arithmetic units, particularly in aerospace and space applications. While FinFETs offer significant advantages, they remain susceptible to single-event transients (SETs) induced by radiation, which can cause computational errors. We assess three circuit-level mitigation techniques against SETs in FinFET adders: decoupling cells (DCELLs), transistor sizing (TS), and a combined approach incorporating both methods. Our results demonstrate that the most sensitive nodes and critical vectors in the adders vary depending on the mitigation strategy, underscoring their impact on overall radiation resilience. By analyzing these techniques alongside critical node evaluation, we identify their advantages and limitations, providing insights to enhance the robustness of FinFET-based processors in radiation-prone environments. Full article

In this work, the effects of heavy ion strike position, incident angle, linear energy transfer (LET) value, ambient temperature, bias conditions, and the synergistic effects of total dose irradiation on the single-event transient (SET) in silicon-germanium heterojunction bipolar transistors on silicon-on-insulator (SiGe-on-SOI HBTs) were investigated using TCAD simulations. It was demonstrated that, compared to the bulk SiGe HBT, the SiGe-on-SOI HBT exhibits lower transient current and less charge collection, indicating better resistance to SET. The SET response is more pronounced when heavy ions strike vertically from the emitter and base regions. Transient current and collected charge escalate with increasing incident angle, demonstrating a strong linear correlation with LET values. As the temperature decreases, the peak transient current increases, while the pulse duration decreases and the total collected charge diminishes. After total dose irradiation, the peak transient current in the SiGe-on-SOI HBT decreases, whereas the damage was more severe in the absence of irradiation. Under collector positive bias and positive bias, significant SET responses were observed, while cutoff bias and substrate bias exhibited better resistance to SET damage. These findings provide critical insights into radiation-hardened design strategies for the SiGe-on-SOI HBT. Full article

Based on the simulation software, single-event transient (SET) simulations were conducted on semi-enclosed gate NMOS devices. The simulation involved bombarding the semi-enclosed gate NMOS devices with heavy ions under specific conditions. A comparative analysis was conducted to evaluate the single-event transient tolerance of traditional NMOS and semi-enclosed gate NMOS. Simulation curves from transient to steady-state states under different Linear Energy Transfer (LET) values, as well as potential distribution and current density distribution maps following heavy ion bombardment, were analyzed. Furthermore, single-event transient simulations were carried out on inverters composed of both NMOS types, with subsequent analysis. The results ultimately demonstrate that the semi-enclosed gate NMOS exhibits superior single-event transient tolerance compared to conventional NMOS. Full article

Background/Objectives: Thread-embedding acupuncture (TEA) is widely used for cosmetic and therapeutic purposes; however, its safety profile, particularly in real-world clinical settings, remains under-researched. This study aimed to evaluate the safety profile of TEA through a prospective, observational analysis and confirm the feasibility of the study design for future studies involving larger patient populations. Methods: A multicenter, prospective observational study was conducted involving 100 patients who received TEA. Adverse events (AEs) were tracked, including incidence, severity, and duration during the 6-month post-treatment period. Bivariate analysis was used to assess factors influencing AE occurrence, including treatment site, depth, and patient-specific variables. Results: A total of 100 patients received 136 treatments during the study period. A total of 12 AEs were reported, most of which were mild and transient local reactions, including pain and bruising. More than half of the AEs occurred on the day of the procedure, with an average duration of 7 days. No serious AEs were observed, and all events resolved without any lasting effects. Patients undergoing multiple treatments showed no significantly higher AE rates than those receiving a single session. Conclusions: This study suggested that TEA generally has a favorable safety profile, with most AEs being mild and resolving without long-term effects. Further studies that evaluate the safety of TEA treatment across larger populations are recommended. Full article