Switched-Capacitor-Based High Boost DC-DC Converter

Abstract

A non-isolated high boost DC-DC converter topology based on a switched-capacitor (SC) structure is introduced in this paper. By controlling the duty cycle in each period, the voltage gain of the converter is adjusted. The main features of the proposed SC converter are the continuous input current, achieving high voltage gain with low voltage and current stress on the power components, no use of a high-frequency transformer, and easy to increase the voltage by adding the SC cell. To correct the operating analysis, a 200-W output power prototype was built with the input voltage in the range of [25 V, 50 V] and the output voltage of 200 V. The proposed inverter reaches a maximum efficiency of 93% at the input voltage of 25 V and the output power of 150 W. The simulation and experimental verifications match the analysis.

1. Introduction

Recently, with the development of industrialization, the use of the renewable resources—photovoltaic arrays, fuel cells, etc.—have been a most effective solution. However, they are DC sources with low voltage, low current, and instability. To link them to loads or grid applications, the power conversion generation in Figure 1 was developed. To convert the low voltage of the renewable sources into 200 V or 400 V DC voltage, a high step-up DC-DC stage [1,2,3] is set up as the first stage in the power-conversion system. The second-stage DC-AC converter can provide 110 Vrms or 220 Vrms AC volts for the grid-connected application.

Since the components have an equivalent series resistance (ESR), the traditional boost converter is difficult to step up a large gain voltage. When the high boost voltage is required, the boost converter needs to have a large duty cycle, which leads to high conduction loss and reducing efficiency [4,5,6]. Moreover, in order to achieve the high boost voltage gain, the various DC-DC converters have been presented, including isolated and non-isolated topologies. The isolated topology [7,8,9,10] can provide the isolation between input and output terminals, which is based on a high-frequency transformer. Since the isolated topologies include a DC-AC stage and an AC-DC stage, they required a number of components, which increase the circuit’s size. If the leakage inductances are designed carelessly, the switches appear as a voltage spike. The non-isolated topologies [11,12,13,14,15,16,17,18,19] can achieve a high efficiency with a simple circuit because of the lack of a transformer. In the non-isolated topologies, the high step-up voltage gain can be achieved by using the following techniques: cascade boost, switched-capacitor, switched-inductor, coupled inductor, and a mixture of them. The coupled-inductor-based converters [12,13,14] have a large voltage conversion ratio with increasing efficiency and reduces the voltage/current stress on switches and diodes. However, the circuits are complex to design and the leakage problem of the coupled inductor causes a high voltage spike on semiconductor components. The dual-switch-based converters [15,16,17] present a high voltage gain with high input current ripple. In these topologies, an additional active switch is required with the increasing gate drive. The SC structure was proposed in [18]. By charging the capacitors in parallel and discharging them in series the SC-based converter produces a high voltage at the output side. In [19], an interleaved DC-DC multilevel converter was proposed by combining a multilevel boost structure and a single inductor multiplier Cuk converter to achieve a minimum input current ripple. A non-isolated high step-up DC-DC converter with single-inductor-energy-storage cell-based SCs (SIESC-SCs) was introduced in [20]. By changing the SC cell connection, various converter topologies are obtained.

To decrease the converter’s size and obtain a high voltage gain, the cascade boost converter, the voltage multiplier cells (VMC) boost converter, and the dual boost converter were proposed, as shown in Figure 2. The cascade boost converter, as shown in Figure 2a, can provide a high ratio, but the circuit is complex, and the size and cost of the converter are increased. The cascade converter can reduce switch S₁ and diode D₁ voltage stress, high flexibility, and suitability for high power applications. However, the switch S₂ and diode D₂ voltage stress are high. The VMC boost converter were presented in [5] and is shown in Figure 2b. The voltage ratio of the VMC boost converter can achieve a larger gain voltage by increasing the N cell of the VMC. The switches’ and diodes’ voltage stresses are decreased, and the diodes are turned off with ZCS. However, the duty cycle is limited and the switches’ current stress is large, and the voltage stress is dependent on the number of VMC. The dual converter was quoted from [6], as shown in Figure 2c. Similarly, the dual boost converter decreases the voltage stress on the switches, the inductor current is rated roughly at half of the total input current, and the isolated gate driver is needed for the dual boost converter.

This paper proposes a new boost converter based on a switched-capacitor structure. The proposed SC converter has a large step-up gain with continuous input current. The operating principles and circuit analysis in continuous conduction mode (CCM) and discontinuous mode (DCM) are presented. The parameters selection of the proposed SC converter and a comparison with conventional converters are shown. Simulation and experiment verifications prove the correctness of the operating analysis.

2. Proposed SC Converter Topology

2.1. Proposed Topology

The proposed SC non-isolated boost DC-DC converter is presented in Figure 3, which includes a SC structure and multilevel-boost converter. It uses a single switch, five diodes, single inductor, five capacitors and load. Figure 4 shows a detailed PWM algorithm for the proposed SC converter. The switch S₀ is controlled by comparing the reference voltage, V_ref to the triangle waveform with the amplitude of “1”.

2.2. Circuit in CCM Operation

To facilitate the circuit analysis of the proposed converter, the following conditions are guaranteed as all components seem ideal and reflect no losses, the voltage of capacitors is constant, and the inductor current is increased and decreased linearly.

Mode 1 [t₀–t₁, Figure 5a]: The time interval in this mode is DT, where D is the duty cycle of switch S₀ in one switching period T. The MOSFET S₀ is turned on. The diodes D₁ and D₃ are forward-biased. The inductor is charged. We have the equivalent equations:

$$\{\begin{array}{l}{V}_L=V_i\\ V_{C1}=V_{Ca}+V_{Cb}\\ V_{C2}=V_{C3}\end{array}$$

(1)

Mode 2 [t₁–t₂, Figure 5b]: This interval time in mode 2 is (1 − D)T. Switch S₀ is turned off. The diodes D_a, D_b, and D₂ are forward-biased. The inductor delivers the stored energy to the load. We have:

$$\{\begin{array}{l}{V}_L=V_i-V_{Ca}\\ V_{Ca}=V_{Cb}\\ V_O=V_{C1}+V_{C3}\end{array}$$

(2)

The average voltage across the inductor in period switching is zero:

$${\overline{V}}_L=D\cdot V_i+(1-D)\cdot (V_i-V_{Ca})=0$$

(3)

In the steady state, the capacitor voltage and output voltage are calculated as:

$$\{\begin{array}{l}{V}_C=V_{Ca}=V_{Cb}=V_{C2}=V_{C3}=\frac{1}{1-D}{V}_i\\ V_{C1}=2V_C=\frac{2}{1-D}{V}_i\\ V_O=3V_C=\frac{3}{1-D}{V}_i\end{array}$$

(4)

2.3. Circuit in DCM Operation

When the power load is reduced to a light load, the converter works in CCM. Then, the inductor current goes to zero and stays there until the new switching period starts. The inductor current waveform is the last one sketched in Figure 4. The inverter has one more mode, as shown in Figure 5c.

Mode 1 [t₀–t₁, Figure 5a] and mode 2 [t₁–t_x, Figure 5b]: These modes are the same as modes 1 and 2 in the CCM. The interval time in modes 1 and 2 is DT and (1 − D − D_x)T, respectively.

Mode 3 [t_x–t₂, Figure 5c]: The interval time in this mode is D_xT. The switch S₀ is still off. The inductor current is zero. The equivalent circuit is shown in Figure 5c. The switching ripple of peak amplitude is:

$$\Delta I_L=\frac{V_i}{L}\cdot DT$$

(5)

If the power losses of circuit are equal to zero, the average input current is calculated as:

$${\overline{I}}_i=\frac{P_o}{V_i}=\frac{V_o^2}{R{V}_i}=\frac{9V_i}{{\left(1-D\right)}^{2}R}$$

(6)

where P_o and R are the power and the resistance of the load, respectively.

The condition of the proposed converter in the discontinuous conduction mode is:

$${\overline{I}}_L<\left(\Delta I_L/2\right)$$

(7)

Substituting Equations (5) and (6) into (7), we have:

$$K<K_{crit}\left(D\right)$$

(8)

where $K=18L/\left(RT\right)$, and $K_{crit}\left(D\right)=D\cdot {\left(1-D\right)}^2$.

Applying the inductor volt-second balance, the D_x was obtained as:

$$D_x=\frac{D{V}_i}{V_C-V_i}$$

(9)

From Figure 5, the average inductor current is easily evaluated:

$${\overline{I}}_L=\frac{V_i}{2L}\cdot D\cdot \left(D+D_x\right)\cdot T=\frac{V_o^2}{V_{i}R}$$

(10)

From Equations (8)–(10), we have:

$$G_{DCM}=\frac{V_o}{V_i}=\frac{3+\sqrt{9+\frac{36D^2}{K}}}{2}$$

(11)

Figure 6a gives the voltage gain of the proposed SC converter in DCM/CCM. The output voltage gain in the DCM is higher in the CCM. The converter works in the CCM when Kcrit > 0.148. Figure 6b shows the relationship between K_crit and D at CCM/DCM boundary.

3. Capacitance and Inductance Selections

3.1. Inductance Selection

The inductor is chosen based on the current ripple through it. From Figure 5a, we have:

$$V_L=L\frac{di}{dt}=V_i$$

(12)

where di/dt is the variation of the inductor current. Equation (12) can be rewritten as:

$$V_L=L\frac{\Delta i}{\Delta t}=V_i$$

(13)

The inductor current ripple is calculated as:

$$\Delta i=a\%\cdot I_L=\frac{H\cdot P}{V_i}$$

(14)

where H (%) and a% are the converter efficiency and the inductor current ripple, respectively.

Based on the inductor current ripple in DT interval and Equations (13) and (14), the inductance is calculated as:

$$L=\frac{V_i^2}{a\cdot H\cdot P_o}\cdot DT$$

(15)

3.2. Capacitance Selection

In mode 2, the peak current flows to capacitor C₃ calculated as:

$$I_{C3}=C_3\frac{dv}{dt}=I_o$$

(16)

The capacitance is chosen as C = C_a = C_b = C₂ = C₃ = 0.5C₁. From Equation (16), we obtain:

$$C=\frac{3DT}{\%bR}$$

(17)

where %b is the capacitor C₃ voltage ripple.

3.3. Calculation of Power Loss

Power Loss of Switch:

The power loss of switch are the conduction loss and the switching loss. The MOSFET conduction loss of switch S₀ is:

$$P_{cS}=R_{DSon}\cdot D\cdot I_{in}^2/4$$

(18)

where R_DSon is the drain-source resistance of the MOSFET.

The MOSFET switching loss is determined as [21]:

$$P_{swS}=V_C\cdot \frac{I_{in}}{2}\cdot f_s\cdot \left(\frac{tru+tfi}{2}+\frac{tri+tfu}{2}\right)$$

(19)

where tru, tfu, tri, and tfi are the rising time, falling time of voltage, rising time, and falling time of current, respectively, and the parameters are obtained from the datasheet.

Power Loss of the Diodes:

The conduction loss of diodes D₀, D₁, and D₂ is:

$$\begin{array}{l}{P}_{CD}=2\cdot \left[u_{Dx}\cdot I_{in}/2+R_{Dx}\cdot I_{in}^2/4\right]\cdot \left(1-D\right)\\ +2\left(u_{Dx}\cdot I_o/2+R_{Dx}\cdot I_o^2/4\right)\cdot D\\ +\left(u_{Dx}\cdot I_o/2+R_{Dx}\cdot I_o^2/4\right)\cdot \left(1-D\right)\end{array}$$

(20)

where u_Dx and R_Dx are the drop voltage and the resistance of the D_a, D_b, D₁–D₃, respectively.

The reverse recovery loss of the diodes is:

$$P_{rrD}=5Q_{rrf}\cdot V_C\cdot f_s$$

(21)

where Q_rrf is the reverse recovery charge of diodes.

Power Loss in the Capacitor:

The capacitor power loss is calculated by:

$$P_C=r_{Ca}\cdot I_{Ca}^2+r_{Cb}\cdot I_{Cb}^2+r_{C1}\cdot I_{C1}^2+r_{C2}\cdot I_{C2}^2+r_{C3}\cdot I_{C3}^2$$

(22)

where r_Ca, r_Cb, r_C1, r_C2, and r_C3 are the internal resistances of C₁, C₂, and C₃ capacitors.

The current of capacitors C_a, C_b, C₁, C₂, and C₃ are defined by:

$$\{\begin{array}{l}{I}_{Ca}=I_{Cb}=\frac{I_{in}}{2}\\ I_{C1}=\sqrt{{\left(I_o-I_{in}/2\right)}^2\cdot D+{\left(\frac{I_o}{2}\right)}^2\cdot \left(1-D\right)}\\ I_{C2}=\frac{I_o}{2}\\ I_{C3}=\sqrt{{\left(\frac{I_o}{2}\right)}^2\cdot D+I_o^2\cdot \left(1-D\right)}\end{array}$$

(23)

Power Loss of the Inductor:

The power loss of the inductor is such as the loss of core and copper wire. The inductor core loss is expressed as:

$$P_{fe}=K_{fe}\cdot \Delta B^{\beta }\cdot A_c\cdot l_m$$

(24)

where K_fe is a constant, β is selected from the core datasheet; A_c is the core cross-sectional area; and l_m is the core mean magnetic path length.

The inductor copper losses are given by:

$$P_{cu}=R_L\cdot I_{L\_RMS}^2$$

(25)

where R_L is the resistance wire.

The power loss is calculated and shown in Figure 7a at V_i = 25 V, V_o = 200 V and P_o = 200 W. The parameters of device are used to calculate the power loss, are shown in

Table 1. Conducting current of the devices in the proposed SC converter.

Devices	Conducting Current	Conducting Time
So	IL/2	D·T
Da, Db	IL/2	(1 − D)·T
D1, D3	Io/2	D·T
D2	Io/2	(1 − D)·T
L	IL	T
Ca, Cb	IL/2	T
C1	Io − IL/2	D·T
	−Io/2	(1 − D)·T
C2	−Io/2	T
C3	−Io/2	D·T
	−Io	(1 − D)·T

and

Table 2. Parameters of the devices.

Devices	SIESC-SCs [20]	Proposed SC Converter
MOSFET S0	STW88N65M5 (650 V, 84 A, 24 m Ω)
Diodes	DSEI30-06A (600 V, 37 A)	DSEI30-06A (600 V, 37 A)
ESR of capacitors	280 mΩ	280 mΩ
ESR of C1 (470 µF/400 VDC)	130 mΩ	130 mΩ
Inductor core	CM777125 (142 nH/N2)	CM777125 (142 nH/N2)
Copper wire resistivity (ρ)	1.724 µΩ-cm	1.724 µΩ-cm

. The total power loss is 13.55 W and the calculated efficiency of the proposed SC converter is 93.23%. Figure 7b shown the calculated efficiency comparison between the proposed converter and SIESC-SCs [20] when V_i = 25 V and V_o = 200 V. The power loss of both proposed converter and SIESC-SCs are determined based on the parameters in Table 2. As shown in Figure 7b, the calculated efficiency of the proposed SC converter is slightly lower than that of the SIESC-SCs [20]. This is because the proposed inverter uses two more diodes and capacitors to obtain the high voltage gain. As shown in Figure 7a, the major loss contributions are from diodes and capacitors. Note that the parameters for power loss calculation in Table 2 are chosen from devices those are available in the laboratory for the experimental test. Therefore, these parameters are not optimally selected for efficiency consideration. The devices including MOSFET and diodes with lower voltage rating should be selected to reduce the power loss of the proposed converter.

4. Comparison with Other High Voltage Gain Converters

The comparison between the proposed SC converter and other converters, including the dual boost converter (DBC) [3], the cascade boost converter (CBC) [5], the boost voltage multiplier cell (B-VMC) (n = 2) [6], the single inductor multiplier Cuk converter (SLMC) [19], and the converter with the SIESC-SCs [20], are shown in

Table 3. Comparison of topologies.

Converter	L	C	Switches	Diodes
DBC [3]	2	2	2	2
B-VMC (n = 2) [6]	2	3	1	3
CBC [5]	2	2	1	2
SLMC [19]	1	6	1	6
SIESC-SCs [20]	1	3	1	3
Proposed	1	5	1	5

and

Table 4. Comparison voltage stress and gain of topologies.

Converter	Switched Stress	Diode Stress	Voltage Gain
DBC [3]	Vo/2	Vo/2	G = (1 + D)/(1 − D)
B-VMC (n = 2) [6]	Vo/2	Vo/2	G = 2/(1 − D)
CBC [5]	Vo/2	Vo/2	G = 1/(1 − D)2
SLMC [19]	Vo/3	Vo/3	3/(1 − D)
SIESC-SCs [20]	Vo/2	Vo/2	2/(1 − D)
Proposed	Vo/3	Vo/3	G = 3/(1 − D)

. In the comparison to DBC [3], B-VMC [6], and CBC [5], the proposed SC converter saves one inductor. Moreover, the voltage stress on diodes and switches of the proposed SC converter is small. Similar to the CBC [5] and B-VMC [6], the proposed SC converter uses one active switch. Compared to the DBC [3], B-VMC [6], CBC [5], and SIESC-SCs [20], the proposed SC converter uses two more diodes and capacitors, but the voltage gain of the proposed SC converter is higher. When the gain and voltage stress of active components are considered, the SLMC [19] is an interesting topology. However, the proposed SC converter has the same advantages with SLMC [19] and uses one less capacitor and one less diode.

Figure 8 shows the voltage gain comparison between the proposed SC converter and the other non-isolated converters in the CCM. The voltage gain of the proposed SC converter is the same as that of SLMC [19] and is highest when D < 2/3. Therefore, the proposed configuration is more profitable than other non-isolated configurations of the boost coefficient.

5. Simulation and Experimental Verifications

5.1. Simulation Verification

To confirm the operating principle of the proposed DC-DC converter, PSIM simulation software was used to prove the correctly of the operating principle with the parameters as L = 0.4 mH, C₁ = 470 µF, C_a = C_b = C₂ = C₃ = 220 µF. The on-resistance of the MOSFET is 24 mΩ. The forward-voltage of diodes is set to 1.4 V. The switching frequency of semiconductor components is 20 kHz. The input DC source is used to adjust from 25 V to 50 V. The output voltage is stepped up to 200 V.

Figure 9a shows the simulation results for the proposed SC converter when V_i = 25 V and D = 0.644. As shown in Figure 9a, the input current is continuous and the peak-to-peak inductor current is 1.96 A. The capacitor voltages are boosted to V_Ca = V_Cb = 68 V, V_C1 = 134 V, and V_C2 = V_C3 = 66 V. Then, the input voltage is increased to 50 V and the duty cycle is decreased to 0.282, while the output voltage is still 200 V, as shown in Figure 9b. The input current in this case is also continuous with the peak-to-peak inductor current of 1.7 A.

5.2. Experimental Verifications

The experiment results are implemented by using a TMS320F28335 DSP kit with experimental parameters as shown in

Table 5. Parameters for verification.

Parameter	Values
Output power, Po	200 W
Input voltage, Vi	25 V
Output voltage, Vo	200 V
Switching frequency	20 Khz
The ripple of inductor current (a%)	≤20%
The ripple of capacitor voltage (b%)	≤5%

and

Table 6. Accessories used for experiments.

Number	Component	Values
1	Inductor L	0.4 mH; 20 A
2	Capacitor Ca, Cb, C2, C3	220 µF; 400 V
3	Capacitor C1	470 µF; 400 V
4	Diode Da, Db, D1, D2, D3	DSEI30-06A
5	Mosfet S0	STW88N65M5
6	Load (R)	200 Ω

. One MOSFET is STW88N65M5 and five diodes are DSEI30-06A. The output voltage and output powers are 214 V and 200 W, respectively. Figure 10 shows a photograph of the converter prototype.

Figure 11 shows the experimental results of the proposed SC converter in CCM when V_i = 25 V. The output voltage is boosted to 200 V when the input voltage is 25 V. The peak-to-peak ripple input current is 2 A, which is close to the simulation value.

Figure 12 shows the measured efficiency of the proposed SC converter when the output power is changed from 80 W to 200 W. The WT230 digital power meter is set up to connect the input and output. The maximum measured efficiency is 93% at 150 W. The efficiency for the experiment can be improved with the optimal selection of components. The experimental results are slightly similar from the theoretical and simulation results.

Figure 13 shows the voltage gain between the calculated values and simulated values. The simulated values are slightly lower than the calculated values because the parasitics on the devices were set in the simulation.

6. Conclusions

A non-isolated boost DC-DC converter was proposed in this paper. The major advantages of the proposed SC converter are as follows: high voltage gain; decrease voltage and current stress on the power device, which helps reduce the loss; and being easy to increase the voltage gain and control using one switch. The operating principles in the CCM and DCM, parameters design, power loss analyses, and the comparison with the other non-isolated high boost converters are discussed. The experimental results of the proposed converter at 25 V input voltage are presented to produce the output voltage of 200 V. The maximum measured efficiency of the converter is 93% at 150 W. The experimental and simulation verifications were shown to verify the theoretical analysis.