A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Round 1

Reviewer 1 Report

The authors showed a new solution for a low-voltage power efficient op-amp. The proposed architecture does not contain high-impedance internal nodes, i.e. it is based on low-gain stages with relatively high cutoff frequency. Stable operation is achieved thanks to the output pole, associated with a load capacitance. Thanks to this architecture, an improved power efficiency, expressed by standard FOMs is achieved. The approach is interesting, nevertheless I have some comments.

-On page 8 the authors state that the lack of tail current sources is responsible for low CMRR. In my opinion it is a bit problematic statement. Some architectures based on similar non-tailed stages, showed much better CMRR, e.g. [19], [30], [31], even in the presence of mismatch and PVT variations. The input stage used in these designs (in fact also used here in stage 1), has inherent CMRR, so the CMRR is not only dependent on current cancellation, as in pseudo-differential stages. Probably the problem here is rather with variations of the operating point.

-Low gain of the first stage improves the bandwidth, but noise and mismatch of the second stage contribute to the total input referred noise and offset.

-I am a bit concerned about the B2G interface, e.g. between the first and the
 second stage. For instance, what about variations of the bulk potentials of
 M4A, M4B in stage 2 under PVT and mismatch?. It seems to me that there is
 a risk here, that M4A enters the triode region, thus degrading the voltage gain and maybe  CMRR.

- 3 sigma variations of CMRR, Mphi and GBW in table 2 are rather large. I think, that it would be good to add Min and Max values, to the already exixting Mean and Std dev, since most probably the histogram is not Gaussian. 

-Please provide also the value of the input-referred offset voltage and voltage gain in table 2.

-In tables 3-5 please add also the voltage gain and frequency for which the
 input noise was determined.

-The CMRR in tables 3-5 is also dependent on PVT. Is it associated with variations of the bulk potentials in stage 2?

-Variations of noise in tables 3-5 are also surprisingly large. For instance, 
 in table 3 the input noise increase from 0.85uV to 1.6uV when T increases by only 10deg (from 17 to 27deg).

-In my opinion large variations of CMRR and noise can suggest variations of the operating point with PVT, even though the total current is approximately constant.

-Can the circuit operate with lower C_L. Which is the minimum C_L in this design?

-Table 1 is a bit unclear for me. What the bias current means here? Is it a total current for a given stage? This not sums up to the total current consumed by  the circuit. Maybe it would be better to provide a bias current for each branch of the circuit?

-In conclusions the authors point out "very good CMRR and PSRR". In my opinion they are rather sufficient.

-The authors could consider to add a transistor level schematic of the whole structure.
  

Author Response

The authors showed a new solution for a low-voltage power efficient op-amp. The proposed architecture does not contain high-impedance internal nodes, i.e. it is based on low-gain stages with relatively high cutoff frequency. Stable operation is achieved thanks to the output pole, associated with a load capacitance. Thanks to this architecture, an improved power efficiency, expressed by standard FOMs is achieved. The approach is interesting, nevertheless I have some comments.

-On page 8 the authors state that the lack of tail current sources is responsible for low CMRR. In my opinion it is a bit problematic statement. Some architectures based on similar non-tailed stages, showed much better CMRR, e.g. [19], [30], [31], even in the presence of mismatch and PVT variations. The input stage used in these designs (in fact also used here in stage 1), has inherent CMRR, so the CMRR is not only dependent on current cancellation, as in pseudo-differential stages. Probably the problem here is rather with variations of the operating point.

We thank the reviewer for this comment. We agree with the reviewer that our statement on page 8 is not clear and could be misleading. We also agree that some non-tailed stages, such as the one in [19] ([37] of the revised manuscript) used also in this work as stage 1, have inherent CMRR. Furthermore, we acknowledge that the body-mirrors adopted in stage 2 degrade the CMRR due to the limited body transconductance gain and to the inherent higher mismatch in body transconductances with respect to the gate transconductances. We have updated this aspect in the revised manuscript.

For what concerns the OTA reported in [19] ([37] of the revised manuscript), we agree that the CMRR is higher than the one attained with the proposed tree architecture. However it has to be noted that the OTA in [19] ([37] of the revised manuscript) presents a much higher differential gain than the OTA in this work and this helps in achieving good CMRR performance.

-Low gain of the first stage improves the bandwidth, but noise and mismatch of the second stage contribute to the total input referred noise and offset.

We acknowledge that the proposed architecture has that limitation, and this weakness has been better pointed out in the revised manuscript. However we believe that, even if noise and offset performance are suboptimal, they are still acceptable, and accepting this weakness allows to obtain very good small- and large-signal FoMs.

-I am a bit concerned about the B2G interface, e.g. between the first and the second stage. For instance, what about variations of the bulk potentials of M4A, M4B in stage 2 under PVT and mismatch? It seems to me that there is a risk here, that M4A enters the triode region, thus degrading the voltage gain and maybe CMRR.

We agree with the reviewer that M4A, M4B transistors may enter in triode under PVT variations if not properly designed and/or for large temperature variations. To meet the concern of the reviewer we simulated these interface under PVT and Mismatch variations and confirmed that M4A, M4B enter the triode region for temperatures higher than 70°C. We have added some comments on this point in the revised manuscript.

- 3 sigma variations of CMRR, Mphi and GBW in table 2 are rather large. I think, that it would be good to add Min and Max values, to the already existing Mean and Std dev, since most probably the histogram is not Gaussian.

We thank the reviewer for this comment. As pointed out by the reviewer, the histogram is not Gaussian (it seems log-normal distribution, typical of sub threshold circuits). We have added the minimum and maximum values in table II, thus confirming reasonable variations also in extreme PVT mismatch conditions. We have also added the histograms for CMRR and PSRR.

-Please provide also the value of the input-referred offset voltage and voltage gain in table 2.

We have added the input-referred offset voltage in Tab.2 as requested. The value for the dc voltage gain was already reported in the table as Gain (1Hz).

-In tables 3-5 please add also the voltage gain and frequency for which the input noise was determined.

We have added the voltage gain in Tab 3-5 as suggested by the reviewer and the frequency at which the input referred noise was computed.

-The CMRR in tables 3-5 is also dependent on PVT. Is it associated with variations of the bulk potentials in stage 2?

-Variations of noise in tables 3-5 are also surprisingly large. For instance, in table 3 the input noise increase from 0.85uV to 1.6uV when T increases by only 10deg (from 17 to 27deg).                                                                                                                   

-In my opinion large variations of CMRR and noise can suggest variations of the operating point with PVT, even though the total current is approximately constant.

We thank the reviewer for these comments. We fully agree with the reviewer that the main cause of performance variations is the variation of the operating point with PVT: this happens mainly in stage 2. We have better pointed out these aspects in the revised manuscript.

-Can the circuit operate with lower C_L. Which is the minimum C_L in this design?

Stability in typical conditions requires a minimum CL of 8pF. Obviously larger values are needed to also ensure a suitable phase margin. Compensation is needed for lower CL values. These points have been better clarified in section 3.1 of the revised manuscript.

-Table 1 is a bit unclear for me. What the bias current means here? Is it a total current for a given stage? This not sums up to the total current consumed by the circuit. Maybe it would be better to provide a bias current for each branch of the circuit?

We thank the reviewer for this comment which allowed us to better clarify the table, which has been updated in the revised manuscript. The reported value of the current is the bias current of the single devices in the different stages of the OTA.

-In conclusions the authors point out "very good CMRR and PSRR". In my opinion they are rather sufficient.

We agree with the reviewer on this point, and we changed very good with reasonable.

-The authors could consider to add a transistor level schematic of the whole structure.

We thank the reviewer for this comment, but we believe that Fig. 1,3,4,5, are enough clear and a figure with the whole OTA would be difficult to read.

Author Response File: Author Response.pdf

Reviewer 2 Report

Line 63: Blalok introduced body-driven opamps before with "Designing 1-V Op Amps Using Standard Digital CMOS Technology". There may be prior works with bulk-driven rail-to-rail inputs.

Line 86: "The current gains obtained by means of conventional current mirrors". Series-parallel current mirrors can achieve very large current gains with little PVT variability, even for ULV. See Fiorelli's "Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors".

Circuit Analysis

First stage gain is close to 0 dB, as gmb1 approx. gmb2.

Second stage gain must be close to 1/(n-1), which is about 12 dB for n=1.25.

Third stage makes the bulk of the OTA gain, as it is gate-driven and its load isn't diode connected, as in the previous stages.

This has the following repercussions:

Line 186: "Taking into account that the noise sources due to stage3 can be neglected due to the high gain of the preceding stages, the equivalent input noise mainly results from the first two stages and can be expressed as follows"

The first two stages do not have high gain, so stage3 noise can't be neglected. The same can be said about input offset voltage, all stages' mismatch will add to it.

Amplifier Design and Simulation Results

Small-signal voltage gain is high but CMRR isn't that large. Phase margin is ok, and the OTA seems to be stable for the used capacitive load. Would it be stable for no load at all for a non-inverting unity gain configuration?

Process corners and monte carlo simulations were run, but there were no input offset mismatch results. This is a big problem for bulk driven input OTAs.

Process variability is acceptable. The problem is to make a biasing circuit without a ideal current source. Can a self-biasing current source work at 0.3 V VDD and considering other design constraints? A reference should be provided as example, or it must be explained that it is a problem yet to be solved.

There should be a noise profile graphic to show the noise results as function of frequency. Maybe also integrated input referred noise results should be added.

FoM is extremely large, considering it is a bulk-driven input OTA with a tree like architecture, so it seems too good to be true.

How was the area calculated? Multiple stage OTAs, with each OTA with isolated transistors use a lot of area. It's unfair to compare area usage without at least a finished layout.

Author Response

Line 63: Blalok introduced body-driven opamps before with "Designing 1-V Op Amps Using Standard Digital CMOS Technology". There may be prior works with bulk-driven rail-to-rail inputs.

We thank the reviewer for this comment. The reviewer is right, and the text has been modified accordingly.

Line 86: "The current gains obtained by means of conventional current mirrors". Series-parallel current mirrors can achieve very large current gains with little PVT variability, even for ULV. See Fiorelli's "Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors".

We thank the reviewer for this comment. We have added a reference to this work and provided some comments in the revised manuscript.

Circuit Analysis

First stage gain is close to 0 dB, as gmb1 approx. gmb2. :

Second stage gain must be close to 1/(n-1), which is about 12 dB for n=1.25. :

Third stage makes the bulk of the OTA gain, as it is gate-driven and its load isn't diode connected, as in the previous stages.

This has the following repercussions:

Line 186: "Taking into account that the noise sources due to stage3 can be neglected due to the high gain of the preceding stages, the equivalent input noise mainly results from the first two stages and can be expressed as follows"

The first two stages do not have high gain, so stage3 noise can't be neglected. The same can be said about input offset voltage, all stages' mismatch will add to it.

On this point we don’t fully agree with the reviewer. The above analysis does not take into account the tree architecture which results in 12dB additional gain as accounted by the factor 4 in equation (7), and this in our opinion allows to reasonably neglect the third stage contribution of noise and offset. Noise summary results in Cadence confirm this point and justify neglecting the noise due to the third stage.

Amplifier Design and Simulation Results

Small-signal voltage gain is high but CMRR isn't that large. Phase margin is ok, and the OTA seems to be stable for the used capacitive load. Would it be stable for no load at all for a non-inverting unity gain configuration?

Stability in typical conditions requires a minimum CL of 8pF. Obviously larger values are needed to also ensure a suitable phase margin. Compensation is needed for lower CL values.

Process corners and monte carlo simulations were run, but there were no input offset mismatch results. This is a big problem for bulk driven input OTAs.

We have added the input-referred offset voltage in Tab.2 as requested. We acknowledge that the proposed architecture has relatively high offset, and this weakness has been better pointed out in the revised manuscript. However we believe that, even if noise and offset performance are suboptimal, they are still acceptable, and accepting this weakness allows to obtain very good small- and large-signal FoMs.

Process variability is acceptable. The problem is to make a biasing circuit without a ideal current source. Can a self-biasing current source work at 0.3 V VDD and considering other design constraints? A reference should be provided as example, or it must be explained that it is a problem yet to be solved.

We agree with the reviewer that a self-biasing current source working at 0.3 V V_DD is yet an open research problem even if some references are available and have been added in the revised manuscript. We have better clarified this point in the revised manuscript and explicitly stated that simulations have been carried out assuming an ideal current source.

There should be a noise profile graphic to show the noise results as function of frequency. Maybe also integrated input referred noise results should be added.

It has been added in the revised manuscript.

FoM is extremely large, considering it is a bulk-driven input OTA with a tree like architecture, so it seems too good to be true.

We thank the reviewer for this comment, and as we have better clarified in the revised manuscript, these good results can be attained thanks to the approach in [11] ([20] in the revised manuscript) which allows to optimize the bandwidth efficiency and has been exploited in this work in ULV condition.

How was the area calculated? Multiple stage OTAs, with each OTA with isolated transistors use a lot of area. It's unfair to compare area usage without at least a finished layout.

We thank the reviewer for this comment. We have estimated the layout area taking into account the area constraints due to deep N-Wells for body connections, and a note on this aspect has been added in Table 6 of the revised manuscript.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The authors properly adressed my comments.