A Standard-Cell-Based CMFB for Fully Synthesizable OTAs

Abstract

In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) based on a cascade of such stages. A detailed analysis of the CMFB is reported to both provide insight into circuit behavior and to derive useful design guidelines. The proposed CMFB is then exploited to build a fully standard-cell OTA suitable for automatic place and route. Simulation results referring to the standard-cell library of a commercial 130 nm CMOS process illustrated a differential gain of 28.3 dB with a gain-bandwidth product of 15.4 MHz when driving a 1.5 pF load capacitance. The OTA exhibits good robustness under PVT and mismatch variations and achieves state-of-the-art FOMs also thanks to the limited area footprint.

1. Introduction

Recent years have seen a growing interest in ultra-low-voltage operational transconductance amplifiers (OTAs) [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18] that are a key building block in many analog and mixed-signal applications such as Internet-of-Things (IoT) and biomedical ones [19,20,21,22]. This is a strong incentive to innovate the design flow of analog blocks: even if they often constitute just a small fraction of a mixed-signal system, their design requires a large fraction of the overall effort. Indeed, both the schematic and layout design are typically carried out manually, iterating each step several times until specifications are met, also taking into account the required robustness under process, supply voltage and temperature (PVT) variations. To minimize the analog design effort and hence the cost and time-to-market of such mixed-signal applications, circuit solutions for analog blocks based on digital standard cells were explored in [23,24]. The end goal is to achieve a fully automatic design flow for the analog blocks that is similar to the one adopted for the digital section; as an intermediate step, the use of digital standard cells to design analog functions allows for the automating of the place and route steps of the design flow and, in perspective, the achievement of a fully automatic synthesis flow for both analog and digital blocks.

Recently, different approaches to exploit digital-based architectures to mimic the behavior of analog functions were explored in [25]. In particular, the behavior of OTAs has been mimicked through VCO-based architectures [26,27,28] and the DIGOTA approach [29,30,31]. Even if all these innovative techniques are very interesting from a research point of view, the most common approach to implementing analog building blocks suitable for automatic place and route exploits the digital standard cells as basic analog amplifiers [32,33,34,35,36,37]. In fact, the simplest digital gate (the inverter) behaves as a common source amplifier [38], and several inverter-based OTAs [39,40,41,42,43,44,45,46,47,48,49,50] have been proposed in the literature. However, differently from custom-designed inverters, the standard-cell inverter is typically optimized for area footprint or symmetrical slew rate, and as a consequence, it exhibits a systematic offset in its input–output dc transfer characteristic which impacts the output static voltage and strongly degrades the performance of standard-cell-based cascaded amplifiers. According to the above considerations, the design of standard-cell-based OTAs must cope with additional issues that make achieving good and robust performance a very critical task. Several authors [37,42,50,51,52] have pointed out that the performances and even the operation of standard-cell-based analog circuits are severely impaired by PVT and mismatch variations, resulting in incorrect bias, large offsets and significant performance variations.

In such a context, the use of a common-mode feedback (CMFB) loop for each differential gain stage becomes mandatory to ensure a stable bias point [53,54,55], especially for ultra-low-voltage applications. The need to design a standard-cell-based CMFB greatly restricts the design options; some CMFB solutions have been proposed in the literature, but they usually do not involve an explicit reference voltage, resulting in some sensitivity to process, supply voltage and temperature (PVT) variations.

In this paper, we propose a fully standard-cell-based CMFB loop that exploits an explicit reference voltage to guarantee robust biasing, and we exploit it to design a two-stage OTA. Thanks to the proposed approach, a stable dc output voltage is guaranteed for the first stage, allowing a correct biasing of the second stage. The paper is structured as follows: in Section 2, the proposed CMFB is described and analyzed; in Section 3, the design of the standard-cell-based OTA is presented. Section 4 reports the simulation results, and, finally, conclusions are drawn in Section 5.

2. The Proposed CMFB

Figure 1a shows a CMOS inverter that can be thought of as a common-source amplifier. Its dc output voltage depends on the size of NMOS and PMOS devices and is also affected by PVT and mismatch variations. Figure 1b shows the dc input–output transfer characteristic (blue dashed line) and its derivative (continuous green line) for a typical standard-cell inverter, as a function of the input bias voltage V_i for a supply voltage V_DD = 0.3 V. Figure 1b clearly shows that an incorrect input dc bias results in a drop of voltage gain, thus making multistage amplifiers very difficult to implement if the dc output voltage of basic inverter stages is not controlled. The plot in Figure 1b also highlights the systematic offset of the inverter from a standard-cell library. In fact, the maximum gain is achieved for an input bias voltage different from V_DD/2 = 150 mV (value marked as a red dashed line). This systematic offset of the inverter (resulting in a logic threshold different from V_DD/2) is due to the fact that standard cells are not optimized for analog applications, and a trade-off between area, propagation time and balancing constraints is considered.

A fully differential amplifier can be easily obtained using two inverters; however, it requires a CMFB loop to reduce the common-mode gain and to control the dc output voltage. Furthermore, to ensure correct biasing, multi-stage fully differential amplifiers require a CMFB at each stage. In the absence of accessible terminals to set the bias point of the inverter (e.g., the gate or body terminals of individual devices), the CMFB typically exploits two inverters with shorted outputs to sense the common-mode output voltage and other inverters as current sources to close the loop at the input of the main amplifier [53,54,55]. However, when applied to the first stage, this technique adds a resistive component to the input impedance of the OTA, and, therefore, the use of common-mode feedforward [33] has been proposed as an alternative. It is worth noting that, typically, this approach is used to reduce the common-mode gain, whereas other techniques such as body biasing [34,53] are exploited to set the output dc common-mode voltage. However, ultra-low voltage applications show low tolerance to biasing errors, and when standard-cell inverters are used, the body terminal is often not available for biasing purposes.

To maintain the advantages of the feedback avoiding this drawback, one option is to use a local common-mode feedback (LCMFB): when applied at transistor level [17], the LCMFB is typically implemented with a pair of common-mode sensing resistors whose central node is connected to the gates of the active load devices. The corresponding standard cell implementation [37] exploits a pair of sensing inverters and a pair of controlling inverters connected to the same output nodes. For the differential mode signal, the load impedance of the LCMFB is the output resistance of the loading inverters, whereas for the common-mode signal the LCMFB provides a low impedance load that reduces the gain, improving the common-mode rejection ratio (CMRR).

In this work, in order to improve the robustness of the dc operating point to PVT variations and to overcome the systematic offset of the standard cell inverters, we propose to add an explicit voltage reference V_ref to the standard-cell LCMFB through the inverter I₇, as shown in Figure 2.

The resulting fully differential amplifier topology is depicted in Figure 2 (indicated as First-Stage): different colors are used to highlight the inverters constituting the gain stage (I₁ and I₁’), the common-mode estimator (I₂, I₂’ and I₃), the reference inverting buffer (I₇, loaded by I₅) and the CMFB auxiliary amplifier (I₄, I₅, I₆ and I₆’). Inverters with their input and output terminals connected together are used as load devices to avoid high impedance nodes in the loop, providing better stability and a degree of freedom to design the circuit, as will be shown following this section. They are equivalent to parallel NMOS and PMOS diode-connected devices; thus, the cascade of an inverter and such a diode-connected inverter is equivalent to the parallel connection of an NMOS and a PMOS diode-loaded common-source stage.

To analyze the proposed topology and obtain design guidelines, we model each inverter I_X (X = 1, …, 7) with a transconductance gain G_X and an output conductance G_oX, given by

$$G_X=g_{mnX}+g_{mpX}$$

(1)

$$G_{oX}=g_{dsnX}+g_{dspX}$$

(2)

where g_m and g_ds are the small-signal transconductance and output conductance of MOS devices, and n and p subscripts refer to NMOS and PMOS transistors, respectively. We assume that they scale linearly with the size of the devices (hence with the strength of the standard cells, IV_xN meaning an inverter whose devices have N times the minimum width), and their ratio is the voltage gain A_X = G_X/G_oX that we assume is identical for all the inverters (hence A_X = A for x = 1, …, 7).

Let α be the ratio of the strengths of inverters I₆ and I₁ (hence α = G₆/G₁), λ = G₂/G₃, ρ = G₄/G₅ and β = G₇/G₄. The differential voltage gain of the first stage in Figure 2 results in

$$A_d=\frac{A}{1+\alpha }$$

(3)

where the loading effect of the LCMFB is considered. For the common mode, the analysis provides

$$V_{oc}=A_c{V}_{ic}+A_R{V}_{ref}$$

(4)

where V_ic and V_oc are the input and output common-mode components. The gains are

$$A_c=\frac{A}{\left(1+\alpha \right)D}=\frac{A_d}{CMRR}$$

(5)

$$A_R=\frac{\alpha A\beta \rho {\epsilon }_4}{\left(1+\alpha \right)D}$$

(6)

$$D=1+\frac{2\alpha A\lambda {\epsilon }_2\rho {\epsilon }_4}{1+\alpha }$$

(7)

where the error factors

$${\epsilon }_2=\frac{1}{1+\frac{2\lambda +1}{A}}$$

(8)

$${\epsilon }_4=\frac{1}{1+\frac{\beta \rho +\rho +1}{A}}$$

(9)

take into account the effect of the output conductances (ideally, if G_X >> G_oX,, since A approaches to infinite, the values of ${\epsilon }_2$ and ${\epsilon }_4$ tend to 1).

Equations (3)–(9) show that the CMRR of the stage is set by $D$ in (7) and allow the ability to derive design guidelines for the choice of the inverter sizes. A trade-off between high CMRR and low gain penalty due to the loading effect involves the factor α: a large value of α maximizes the CMRR, whereas the smaller its value, the lower the reduction of the differential gain (3). A suitable solution is to choose α = 1 and maximize the CMRR acting on the other factors.

Correct biasing would require A_R = 1, which in the limit of large CMRR implies

$$\beta =2\lambda {\epsilon }_2.$$

(10)

CMRR optimization then requires maximizing

$$\beta \rho {\epsilon }_4=\frac{\beta \rho }{1+\frac{\beta \rho +\rho +1}{A}}.$$

(11)

that asymptotically tends to A for increasing β and ρ. Moreover, by (7) and the condition (10), we obtain

$$\lambda =\frac{\beta }{2}\frac{1+\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$A$}\right.}{1-\raisebox{1ex}{$\beta $}\!\left/ \!\raisebox{-1ex}{$A$}\right.}$$

(12)

that poses the further design constraints. Equation (11) implies that the size of inverter I₇ must be maximized, and (12) requires β < A.

In practical situations, the smallest inverter size to be used is limited by matching constraints (the smaller the transistors, the higher the standard deviation of mismatches, hence offset and common mode to differential mode conversion), and the largest inverter size is limited by area and power constraints and by available standard-cells. Hence, there is a limit to the size of I₇ (that is βρ times larger than I₅) and I₂ (that is λ times larger than I₃):

$$\beta \rho \le R_{max}\hspace{1em}\hspace{1em}\lambda \le R_{max}.$$

(13)

It must also be noted that there is a trade-off between CMRR and the common-mode range: a large value of λ provides a larger CMRR at the cost of the common-mode voltage swing at the output of the stage, since the output of I₂ saturates.

From (12), setting a maximum value of λ poses a more stringent limit on the value of β:

$${\beta }_{max}=\frac{2R_{max}}{1+\frac{2R_{max}+1}{A}}.$$

(14)

If β_max > R_max, βρ is set to R_max and maximizing (11) requires keeping the factor ρ as small as possible (ρ = 1). If β_max < R_max, which is the case for low values of the gain A, β = β_max must be chosen; (11) then becomes

$$\frac{{\beta }_{max}\rho }{1+\frac{\rho \left({\beta }_{max}+1\right)+1}{A}}.$$

(15)

and its optimization involves maximizing ρ, whose maximum value is set by (13) to R_max/β_max. A flow graph illustrating this design procedure is reported in Figure 3.

Further insight into the behavior of the differential stage with the proposed CMFB can be gained by adding to the model of each inverter a current source I_offX that accounts for the offset of the inverter, i.e., the error in the output voltage with respect to V_DD/2 when the input voltage is V_DD/2:

$$I_{offX}=G_{oX}{\left.V_o\right|}_{V_i=V_{DD}/2}.$$

(16)

This current source accounts for both the systematic offset due to the design of the inverter (PMOS to NMOS size ratio) and the random variation due to mismatches, and we can assume it is proportional to the strength of the inverter. The resulting block scheme for the common-mode behavior of the stage is shown in Figure 4; if we consider the contribution to the output common-mode voltage V_oc due to these offset current sources, which can be obtained by letting V_ic = V_ref = 0 in Figure 4, we obtain

$$V_{oc}^{\left(ioff\right)}=\frac{\alpha A}{D\left(1+\alpha \right)}\left. [\frac{I_{off1}+I_{off6}}{\alpha G_1}+\frac{\rho {\epsilon }_2}{G_3}\left(2I_{off2}+I_{off3}\right)-\frac{{\epsilon }_4}{G_5}\left(I_{off4}+I_{off5}+I_{off7}\right)\right].$$

(17)

Equation (17) shows that the residual error on setting V_oc = V_ref is due also to the offset currents of the inverters and that the CMFB suppresses this error in the limit of its finite loop gain. This is true both for the systematic offset currents and for their random components, thus demonstrating that the circuit provides a stable dc output voltage under process and mismatch variations. It must be noted that a suitable choice of the inverter strengths can lead to minimizing (17) and could be used as a further design constraint for design optimization.

3. Standard-Cell-Based OTA

An operational transconductance amplifier must provide high voltage gain, thus requiring, especially in an ultra-low-voltage environment with deep submicron technologies, the cascade of at least two gain stages with a differential-to-single-ended (D2S) conversion.

In the context of a standard-cell-based approach, mimicking the typical analog architecture with an input D2S converter followed by single-ended gain stages would result in a very poor CMRR and in a very high sensitivity to PVT variations. Better performance can be achieved by exploiting differential stages with CMFB loops to improve the CMRR and stabilize the bias point, followed by a final D2S stage.

To illustrate this approach, we propose a two-stage OTA, shown in Figure 2, composed by the fully differential stage described in the previous section (First-Stage) followed by a standard-cell-based D2S converter (Second-Stage), composed by inverters I₈–I₁₁. Inverters I₈ and I₉ constitute an inverting voltage buffer whose gain is ideally −1, and inverters I₁₀ and I₁₁ act as transconductance amplifiers driving the same output node.

The voltage gain of the D2S stage is thus ideally

$$\frac{V_{out}}{V_{o1p}-V_{o1m}}=A_{d2}=\frac{A}{2}.$$

(18)

with an infinite CMRR. However, in deep submicron technologies the voltage gain A is limited; hence, the output conductances of I₈ and I₉ cannot be neglected in the analysis. This reduces the gain of the voltage buffer and drastically worsens the CMRR even in typical conditions. Assuming I₈ = I₉ and I₁₀ = I₁₁, differential and common-mode gains of the second stage are

$$A_{d2}=\frac{A}{2}\frac{1+\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$A$}\right.}{1+\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$A$}\right.}$$

(19)

$$A_{c2}=\frac{A}{2}\frac{\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$A$}\right.}{1+\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$A$}\right.}=\frac{1}{1+\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$A$}\right.}$$

(20)

and the overall CMRR results are

$$CMR{R}_{TOT}=\frac{A_{VD}}{A_{VC}}=\frac{A_d{A}_{d2}}{A_c{A}_{c2}}=D\frac{A+1}{2}$$

(21)

where D, defined in (7), is the CMRR of the first stage.

The D2S stage presents an output pole set by the load capacitance C_L; moreover, its dual path nature results in a pole–zero doublet similar to that provided by the current mirror load of a differential pair. With reference to Figure 2, assuming I₈ = I₉ and I₁₀ = I₁₁ and considering a differential input to the D2S (i.e., V_o1p = −V_o1m), the frequency response of the D2S can be written as

$$A_{d2}=\frac{A}{2}\frac{2\left(1+\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$A$}\right.\right)G_8+s{C}_X}{\left(1+\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$A$}\right.\right)G_8+s{C}_X}\frac{1}{1+\raisebox{1ex}{$s{C}_L$}\!\left/ \!\raisebox{-1ex}{$2G_{o10}$}\right.}$$

(22)

where C_X is the total capacitance seen at the output of I₈. Equation (22) shows that the pole and zero due to the inverting buffer I₈–I₉ are spaced by an octave; thus, their effect can be neglected. It must further be noted that Equation (22) poses no constraint on the sizing of inverters I₈ and I₉ with respect to I₁₀ and I₁₁; regardless, it could be convenient to use inverters of the same size to provide a symmetric loading to the first stage.

The OTA is stable when driving a sufficiently large load capacitance that makes the output pole dominant; for small load capacitors, a compensation is needed. More in detail, neglecting the pole–zero doublet due to I₈ and I₉, the internal pole of the OTA is given by

$$p_{int}=\frac{G_{o1}\left(1+\alpha \right)}{C_{in2}+C_{in8}}$$

(23)

where C_in2 and C_in8 are the input capacitances of I₂ and I₈, and the output pole is

$$p_{out}=\frac{2G_{o10}}{C_L}$$

(24)

(assuming I₁₀ = I₁₁). By imposing that the second pole is γ times the unity-gain frequency (where γ is set by the required phase margin), the minimum load capacitance required to have stability with the dominant pole at the output is

$$C_{Lmin}=\gamma \frac{2G_{o10}{A}_{VD}}{p_{int}}=\gamma \frac{A^2}{4}\frac{G_{o10}}{G_{o1}}\left(C_{in2}+C_{in8}\right)$$

(25)

where α = 1 has been considered. Equation (25) shows that the standard-cell-based OTA has the capacity to drive small capacitors, as required in most on-chip applications, without the need of compensation capacitors thanks to the fact that the intrinsic gain of inverters is low and small-size inverters are used in the output stage. The latter condition, however, limits the slew rate of the OTA.

4. Simulation Results

The OTA in Figure 2 was designed using the standard-cell library of the STMicroelectronics 130 nm CMOS technology. Supply voltage was set to 0.3 V. Taking into account the design guidelines in Section 2 and the mismatch requirements that impose the use of non-minimum size cells, the inverters were designed as specified in Figure 2 (inverter IV_xN has devices with N times the minimum width). It must be noted that the low voltage gain of the inverters (A = 19 dB) result in the error factors (8) and (9) that are significantly below 1: in particular, we obtain ${\epsilon }_2=0.5$ and ${\epsilon }_4=0.6.$ With reference to the analysis in Section 2, the smallest inverters were chosen as 20 times the minimum size inverter (IV_x20 for all the inverters except I₂ and I₈) and the design factors were set to α = 1, λ = 4, ρ = 1 and β = 4. The resulting static offset is therefore

$$V_{oc}^{\left(ioff\right)}=0.57\frac{I_{off1}}{G_{o1}}.$$

(26)

To assess the effectiveness of the proposed approach in stabilizing the dc output voltage, the pseudo-differential stage with the CMFB was tested under PVT variations. The reference voltage was set to V_DD/2, and the error of the output dc common-mode voltage with respect to this reference was evaluated. The LCMFB without I₇ and the reference input were also tested for comparison.

Figure 5 shows the relative error on the dc output common-mode voltage for the proposed CMFB and for the LCMFB without the reference input, under variations of temperature and supply voltage. An error is present in typical conditions (300 mV V_DD, 27 °C) due to the finite loop gain of the CMFB. When the reference input is present, the output common-mode voltage presents a limited variation when the temperature ranges from 0° to 80 °C, whereas the voltage drifts with the temperature if the reference input is not used. For what concerns the variation of the supply voltage, the dc common-mode output voltage tracks V_DD/2 with an error, due to the finite loop gain, that presents little variation and is lower than the error achieved by the design without the reference input.

The advantage provided by the reference input is even more evident when the effect of process variations is considered. Figure 6 shows the relative error on the dc output common-mode voltage with respect to the reference input for the extreme process corners. A residual error of about 1.34% is reported in typical (TT) conditions due to the finite loop gain of the CMFB. This error increases in the corners where NMOS and PMOS devices present opposite variations (corners FS and SF); however, the values are below 10% and are one third of the errors obtained if the reference input is not used.

The proposed pseudo-differential stage with CMFB thus results in suitable-to-design multi-stage amplifiers, and the OTA in Figure 2 was designed and simulated. The amplifier dissipates 4.4 μW from a 0.3 V supply; this relatively high power consumption is due to the use of large inverters to minimize the mismatches. Figure 7 shows the differential (A_VD) and common-mode (A_VC) gains of the OTA loaded by a 1.5 pF capacitor. The differential dc gain is 28.27 dB with a 15.42 MHz unity-gain frequency and 54.18° phase margin; the common-mode rejection ratio (CMRR) is about 41.07 dB and is constant across all the bandwidth.

The amplifier was tested in a unity-gain buffer configuration to assess its large-signal performance. The response to an input pulse from 45 to 255 mV (Figure 8) shows identical values for positive and negative slew rates equal to 9.75 V/μs. We also simulated the unity-gain buffer configuration with a 1 MHz sinusoidal input applied, and Figure 9 reports the total harmonic distortion (THD) as a function of the input amplitude. Distortions below 1% (−40 dB THD) are obtained for an input amplitude up to 115 mV, which is about 75% of the rail-to-rail swing.

Figure 10 shows the input-referred noise spectrum of the OTA: a noise corner frequency lower than 1 kHz with a white noise spectral density of 0.497μV/√Hz measured at 10 kHz was obtained, resulting in 1.445 mV rms noise when integrated over the whole closed-loop bandwidth.

The performance under PVT variations and mismatches was evaluated to assess the robustness of the design.

Table 1. Variations under process corners.

Corner	FF	SS	FS	SF
AVD [dB]	25.22	31.43	28.04	27.37
GBW [MHz]	26.4	10.24	15.28	14.57
mφ [°]	63.38	49.18	60.59	60.28
Pd [μW]	7.832	1.89	3.97	3.74
VOS [mV]	0.45	0.18	0.93	0.45
SR [V/μs]	15.15	5.85	12.47	6.33

reports the main performance parameters of the OTA in five different process corners highlighting how the proposed circuit exhibits a relatively low sensitivity to process variations. The effect of supply voltage and temperature variations is reported in

Table 2. Variations under supply voltage and temperature.

	Voltage Variations		Temperature Variations
T [°C]	27	27	0	80
VDD [mV]	270	330	300	300
AVD [dB]	27.28	29.03	29.25	26.32
GBW [MHz]	10.03	23.03	9.80	29.41
mφ [°]	59.94	52.04	52.10	58.50
Pd [μW]	2.65	7.15	2.38	11.21
VOS [mV]	−0.29	−0.29	−0.29	0.17
SR [V/μs]	3.61	12.52	6.91	12.88

: power consumption and gain-bandwidth product exhibit a non-negligible variation as expected since there is no bias loop setting the currents. However, the voltage gain A_VD and the output dc voltage (measured through the parameter V_OS) are extremely stable, confirming the effectiveness of the proposed approach.

Table 3. Results of Monte Carlo mismatch analysis.

	Mean	Std
AVD [dB]	28.2	0.88
GBW [MHz]	15.78	1.91
mϕ [°]	54.47	3.12
CMRR [dB]	24.68	8.56
Pd [μW]	4.49	0.11
VOS [mV]	0.002	9.2
SR [V/μs]	9.12	1.02

reports the results of 200 Monte Carlo mismatch simulations that show a good robustness of the proposed OTA, with limited variation of all the parameters. As can be observed in Table 3, under mismatch variations, the standard deviation of the output offset voltage is 9.2 mV, in line with other ULV OTAs taken from the literature. In order to further reduce the standard deviation of V_OS under mismatch variations, we can place multiple gates in parallel or exploit standard cells with larger driving capability, at the cost, however, of increased area and power consumption. We consider the proposed design as a good tradeoff between area, power consumption and output offset voltage standard deviation. Figure 11 shows the histogram of the CMRR, which is always higher than 10 dB and presents a log-normal distribution. The histogram shows that, even under mismatch conditions, acceptable values of CMRR are obtained, taking also into account the low value of the differential gain.

The layout of the proposed standard-cell OTA was generated by means of an automatic place and route flow by using the Cadence Innovus tool and is shown in Figure 12. The OTA occupies an area of 16.4 × 10 μm² that is very limited, notwithstanding the use of large inverters to minimize the mismatches. The layout has been generated automatically starting from a Verilog netlist of the circuit, which is reported in the Appendix A.

Table 4. Comparison with the literature.

Ref	This Work	[30]	[31]	[17]	[18]	[46]	[10]	[12]	[35]	[36]	[3]
Year	2022	2021	2021	2022	2022	2020	2020	2020	2019	2019	2015
Tech. [nm]	130	180	180	130	130	180	65	180	130	130	65
VDD [V]	0.3	0.55	0.3	0.3	0.3	0.3	0.25	0.5	0.3	0.25	0.35
AVD [dB]	28.3	87	30	38.1	52.9	39	70	79.5	49.8	25	43
GBW [kHz]	15,420	3150	0.25	24.14	35.16	0.9	9.5	36	9100	7.23	3600
mφ [°]	54	65	90	60	52	90	89	65	76	90	56
CL [pF]	1.5	250	150	50	50	10	15	15	2	30	3
SRAVG [V/ms]	9075	2.7	0.085	14.23	15.06	--	2	9.7	3800	--	5600
Pd [nW]	4406	8200	2.4	59.9	21.9	0.6	26	60	1800	55	17,000
Area [μm2]	164	88.3	982	2700	5200	472	2000	3395	--	52,000	5000
Type	STD	STD	DIG	BD	BD	IB	BD	BD	IB	IB	BD
FOMS [MHz pF/μW]	5.25	96.04	15.62	20.15	80.31	15	5.48	9	10.11	3.94	0.63
FOML [V pF/μs μW]	3.09	0.08	5.31	11.88	34.40	--	1.15	2.42	4.22	--	0.99
FOMS,A [MHz pF/μW μm2]	32.01	1088	15.9	7.46	15.44	31.78	2.74	2.65	--	0.07	0.13
FOML,A [V pF/ms μW μm2]	18.84	0.93	5.4	4.4	6.61	--	0.57	0.71	--	--	0.19

STD = standard-cell-based; DIG s= DIGOTA; BD = body-driven; IB = inverter-based.

reports the comparison of the proposed OTA with other ULV OTAs from the literature. To compare the proposed OTA against state-of-the-art low-voltage amplifiers, we refer to the following commonly used figures of merit:

$$FO{M}_S=\frac{GBW C_L}{Pd}$$

(27)

$$FO{M}_L=\frac{S{R}_{AVG} C_L}{Pd}$$

(28)

$$FO{M}_{S,A}=\frac{GBW C_L}{Pd Area}$$

(29)

$$FO{M}_{L,A}=\frac{S{R}_{AVG} C_L}{Pd Area}$$

(30)

where GBW is the gain-bandwidth product, C_L the load capacitance, SR_AVG is the average slew rate and Pd is the power consumption. Subscripts S and L in (27) and (28) denote small signal and large signal, respectively, while the figures of merit (29) and (30) are normalized with respect to the layout area of the OTA. The comparison shows that the proposed circuit exhibits very good small signal performance and adequate large signal performance. Due to the very compact layout, the proposed OTA outperforms all other similar designs in terms of $FO{M}_{L,A}$. The proposed OTA also outperforms almost all other designs in terms of $FO{M}_{S,A}$. Only [30] exhibits a higher $FO{M}_{S,A}$; however, the OTA in [30] is made up of minimum-sized standard cells that result in high sensitivity to process variations and mismatches.

5. Conclusions

In this paper, we have presented a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference that allows the improvement of the CMRR of fully synthesizable standard-cell-based amplifiers and the stabilization of the dc output voltage with respect to PVT variations. A complete analysis of the circuit was presented to derive design guidelines. Simulations displayed that the use of an explicit reference input enhances the robustness of the CMFB to PVT variations.

The proposed CMFB was exploited to design a standard-cell-based OTA made up of only digital gates taken from a standard-cell library. The layout of the OTA was implemented by using a fully automated place and route flow by using the Cadence Innovus tool and starting from the Verilog netlist of the circuit. Simulation results illustrated very good values of both the small signal and large signal FOMs normalized to the area footprint of the circuits with a very good robustness of all the main performance parameters to PVT variations.

We remark that, due to the adoption of the proposed CMFB and to the design equations derived in this paper, the proposed standard-cell-based OTA results are more robust to PVT variations with respect to DIGITAL and standard-cell-based OTAs previously reported in the literature. However, it is worth noting that the performance attained by standard-cell-based OTAs is still less robust with respect to PVT and mismatch variations than that of OTAs designed with a custom analog design approach, which exhibit a well-defined bias current. Moreover, one of the main drawbacks of standard-cell single-ended OTAs is that the D2S converter (the last stage of the proposed OTA) cannot achieve good performance under PVT and mismatch variations, resulting in low and variable CMRR, thus reducing the ICMR of the whole architecture. Therefore, one of the goals of future works will be to achieve better ICMR and CMRR performance by standard-cell D2S converters in order to enhance the performance of standard-cell-based OTAs.