Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors
Abstract
:1. Introduction
2. Background and Related Designs
2.1. The Predictive Model Referenced
2.2. Sample RFET-Based Digital Circuits
3. The Proposed Designs
4. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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FA | #FETs | Estimated Area [nm2] | PStatic [W] | Pdyn [W] | Delay [ps] | |||
---|---|---|---|---|---|---|---|---|
Sum-AB | Cout-AB | Sum-Cin | Cout-Cin | |||||
Mirror CMOS | 28 | 11,760 | 1.65 × 10−6 | 6.25 × 10−6 | 10.8 | 8.3 | 10.7 | 8 |
TG-FET [11] | 14 | 14,504 | 1.23 × 10−9 | 1.55 × 10−6 | 7.5 | 40.7 | 11 | 28.5 |
New LSB | 15 | 15,540 | 1.42 × 10−9 | 1.69 × 10−6 | 7.7 | 36.6 | 11.7 | 17.1 |
New NLSB | 13 | 13,468 | 0.84 × 10−9 | 1.29 × 10−6 | 7.7 | 36.6 | 10.2 | 16.1 |
Adder | Tech. | n | #FETs | Estimated Area [nm2] | PStatic [μW] | Edyn [fJ] | Worst-Case Delay [ps] | EDP [J × ps] | |
---|---|---|---|---|---|---|---|---|---|
Sn−1-C0 | Cn-C0 | ||||||||
CMOS * | FinFet | 4 | 112 | 47,040 | 6.32 | 2.1 | 44 | 33 | 92.4 × 10−15 |
RCA * [11] | TG-FET | 4 | 56 | 58,016 | 4.08 × 10−3 | 0.51 | 102.2 | 106.5 | 54.3 × 10−15 |
NRCA* | TG-FET | 4 | 54 | 55,944 | 3.84 × 10−3 | 0.32 | 75.1 | 85.2 | 27.3 × 10−15 |
CMOS | FinFet | 8 | 224 | 94,080 | 14.09 | 1023 × 10−3 | 67.7 | 64.03 | 6.93 × 10−14 |
RCA [11] | TG-FET | 8 | 112 | 116,032 | 7.79 × 10−3 | 50.86 × 10−3 | 302 | 314.5 | 1.60 × 10−14 |
NRCA | TG-FET | 8 | 106 | 109,816 | 6.9 × 10−3 | 15.28 × 10−3 | 143.1 | 152.9 | 2.34 × 10−15 |
CMOS | FinFet | 16 | 448 | 188,160 | 29.52 | 3.9 | 130 | 126.4 | 5.07 × 10−13 |
RCA [11] | TG-FET | 16 | 224 | 232,064 | 18.24 × 10−3 | 0.57 | 1000 | 1030 | 5.87 × 10−13 |
NRCA | TG-FET | 16 | 210 | 217,560 | 15.52 × 10−3 | 0.063 | 299.2 | 309.4 | 1.95 × 10−14 |
CMOS | FinFet | 32 | 896 | 376,320 | 55.52 | 15.03 | 254.7 | 251 | 3.83 × 10−12 |
RCA [11] | TG-FET | 32 | 448 | 464,128 | 36.76 × 10−3 | 5.76 | 3500 | 3670 | 2.11 × 10−11 |
NRCA | TG-FET | 32 | 418 | 433,048 | 30.72 × 10−3 | 0.24 | 612.2 | 622.7 | 1.49 × 10−13 |
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Spagnolo, F.; Corsonello, P.; Frustaci, F.; Perri, S. Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors. J. Low Power Electron. Appl. 2024, 14, 24. https://doi.org/10.3390/jlpea14020024
Spagnolo F, Corsonello P, Frustaci F, Perri S. Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors. Journal of Low Power Electronics and Applications. 2024; 14(2):24. https://doi.org/10.3390/jlpea14020024
Chicago/Turabian StyleSpagnolo, Fanny, Pasquale Corsonello, Fabio Frustaci, and Stefania Perri. 2024. "Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors" Journal of Low Power Electronics and Applications 14, no. 2: 24. https://doi.org/10.3390/jlpea14020024