A Hybrid Quasi-Single-Stage AC-DC Converter with Low Twice-Line-Frequency Output Voltage Ripple

Abstract

Power factor correction (PFC) converters have been frequently employed in various switching power supply devices to reduce input current harmonics. However, the PFC converter suffers from an obvious twice-line-frequency output voltage ripple due to the instantaneous power imbalance between constant output power and variable input power. Suppression of twice-line-frequency ripple usually can be realized by the post-stage DC-DC converter of the two-stage cascade PFC converter; however, the two-stage cascade PFC structure is challenging to realize high efficiency since the energy is transferred twice. To achieve high power factor, high efficiency, and low twice-line-frequency ripple, a hybrid quasi-single-stage (QSS) AC-DC converter is presented in this paper, which consists of a dual output hybrid Boost/Flyback PFC converter and a Buck ripple compensation circuit (RCC). The fundamental principles of the proposed converter and the critical conditions of operation mode transition are discussed in the paper. To confirm that the twice-line-frequency ripple is effectively suppressed, the small signal model of Buck RCC is built and analyzed. Moreover, the main characteristics, including operation mode transition angle, input current, power factor, and switching frequency of the proposed hybrid QSS AC-DC converter, are analyzed. By building a 120 W experimental prototype to validate the feasibility of the proposed hybrid QSS AC-DC converter, the experimental results show that the proposed converter can realize PFC function with high efficiency and extremely low twice-line-frequency output voltage ripple.

1. Introduction

Due to the serious harmonic current pollution caused by the use of a large number of power electronic equipment, power factor correction (PFC) converters, which can decrease input current harmonic, have received increasing attention [1,2,3]. To satisfy different application requirements, PFC converters often utilize topologies such as Boost, Buck, Buck-Boost, Cuk, SEPIC converters, etc. [4,5,6,7,8].

Boost PFC converter operating in discontinuous conduction mode (DCM) or critical conduction mode (CRM) is widely employed due to the advantages of simple control zero-current turn-off of power switch [5,6]. The twice-line-frequency ripple of output voltage results from the instantaneous power imbalance between constant output power and variable input power of the Boost PFC converter [9,10,11,12,13]. The suppression of twice-line-frequency ripple can be realized using the post-stage DC-DC converter of the two-stage cascade PFC converter, and besides PFC function is achieved using the pre-stage converter of the two-stage cascade PFC converter [14,15]. However, the two-stage cascade PFC converter is not cost-effective for low-power applications due to high cost, large size, and power loss caused by the extra post-stage DC-DC stage of the two-stage cascade PFC converter [16,17,18].

The single-stage topologies employing switch multiplexing technology, such as Boost-Flyback PFC converter, quadratic Boost PFC converter, etc., are also suited for low-power applications [19,20,21,22]. The quadratic Boost PFC converter, which uses a single switch and is generated from two cascaded Boost converters, can achieve a high power factor and low twice-line-frequency ripple of output voltage [19,20]. However, compared to the Boost PFC converter, the quadratic Boost PFC converter cannot achieve high efficiency because the power is transferred twice. Similar to the quadratic Boost PFC converter, the Boost-Flyback PFC converter can achieve PFC and low output voltage ripple with a single switch but suffers from high intermediate capacitor voltage and big power loss [22,23,24,25,26].

In [27], by connecting a bidirectional DC-DC converter in parallel with the PFC converter, a load current compensator for output voltage ripple is proposed to suppress twice-line-frequency output ripple. However, high efficiency cannot be realized in paralleled-type PFC converters compared to conventional single-stage converters due to the effects of high voltage stress on components [27].

Quasi-single-stage (QSS) PFC converter is presented to realize high efficiency and low twice-line-frequency ripple, which is realized by connecting the output of the PFC converter in series with a ripple compensation circuit (RCC) [11,12,13]. Methods based on the reducing audio susceptibility and increasing virtual impedance of RCC to enhance suppression performance of QSS PFC converter on twice-line-frequency ripple which is proposed in [11,12]. In [11,12,13], although most of the power is transmitted to the output through only one stage conversion in the QSS PFC converter, the conversion efficiency is limited because of the poor efficiency of the Flyback PFC converter [28,29,30].

In this paper, a hybrid QSS AC-DC converter consists of a dual output hybrid Boost/Flyback PFC converter and a Buck RCC, which is proposed. In dual output hybrid Boost/Flyback PFC converter, the power inductor of the Boost and the primary winding of the Flyback share the same winding of the magnetic component. Buck RCC is connected in series with the main output of dual output hybrid Boost/Flyback PFC converter, a twice-line-frequency ripple which is the same amplitude and opposite phase of the main output of dual output hybrid Boost/Flyback PFC converter is generated using Buck RCC to achieve low twice-line-frequency ripple of output voltage. Since most of the power of the proposed converter is transferred to the output load only through one-stage Boost conversion, while a small amount of input power is converted to the output load using a Flyback converter and RCC two-stage conversion, high efficiency is easy to implement. The operating principles, the critical condition of operation mode transition, and the main characteristics, including operation mode transition angle, input current, power factor, and switching frequency of hybrid QSS AC-DC converter, are analyzed. The small signal model of Buck RCC is built to verify that the twice-line-frequency ripple is effectively suppressed. By building a 120 W experimental prototype to validate the feasibility of the proposed hybrid QSS AC-DC converter, the experimental results show that the hybrid QSS AC-DC converter can achieve PFC with high efficiency and extremely low twice-line-frequency output voltage ripple over the whole input voltage range.

This paper is organized into five sections as follows. In Section 2, the operation principle of a hybrid QSS AC-DC converter is analyzed. In Section 3, the parameters design is presented, and the main characteristics are analyzed. In Section 4, the experimental results are presented to verify the theoretical analysis. The conclusion is expressed in Section 5.

2. Operation Principle of the Hybrid QSS AC-DC Converter

For simplicity’s sake of analyzing the circuit, unless otherwise specified, it is assumed that: (1) The switching frequency of all switches is much higher than the line frequency; (2) All power switches and diodes are ideal.

2.1. Basic Operation Principle of Topology and Control Strategy

Figure 1a depicts the topology and control strategy of the hybrid QSS AC-DC converter that comprises of dual output hybrid Boost/Flyback PFC converter and Buck RCC. Circuit of hybrid QSS AC-DC converter contains one rectifier bridge D₁, input LC filter L_f and C_f, transformer T₁, Buck inductor L₂, power switch S₁, S₂, diode D₂, D₃, D_S, output capacitor C₁, C₂, C₃, and output load R_o. Figure 1b depicts the key waveforms of v_o, v_o1, and v_B of the proposed converter, where v_o1.rip and v_B.rip are twice-line-frequency ripples of v_o1 and v_B.

In Figure 1a, L_p of the Boost converter can be integrated effectively with the primary of the Flyback converter using a transformer T₁ of the hybrid QSS AC-DC converter. The inductor L_p acts as a traditional boost inductor of the Boost converter and supplies power to output. It also serves as the primary winding connected to the Flyback transformer and generates current on the secondary winding. The winding turns ratio N₁/N₂ of transformer T₁ is designed to realize that a small amount of power is sent to output through the secondary of the Flyback converter, and the majority of power is sent to output through the Boost converter in dual output hybrid Boost/Flyback converter. Then, the output of the Boost converter and Flyback converter is used as the main output and auxiliary output of the dual output hybrid Boost/Flyback PFC converter. Therefore, there is an obvious twice-line-frequency ripple of v_o1 of the Boost converter. To suppress the twice-line-frequency ripple of v_o1 of Boost converter, a series connection between Buck RCC and the output of Boost converter is built, and a twice-line-frequency ripple that has the same amplitude and opposite phase which is generated using Buck RCC as shown in Figure 1b. To achieve high efficiency, the proposed converter should make as much power as possible go through only one stage conversion, the total output voltage v_o, main output voltage v_o1, which has undergone one stage conversion, auxiliary output voltage v_B, which is the output voltage of Buck RCC and undergone two stages conversion are 400 V, 380 V, and 20 V, respectively.

A constant on-time CRM control is employed to achieve the PFC function for a hybrid Boost/Flyback PFC converter. Peak current mode (PCM) control is employed for Buck RCC to improve the response speed of the proposed converter and achieve low output voltage ripple [11,31]. The error signal v_comp1 is generated by comparing the 2.5 V reference voltage V_{ref_1} and the voltage feedback signal v_FB.bst generated by resistance R₁ and R₂ sampling main output voltage v_o1 of dual output hybrid Boost/Flyback PFC converter. v_o1 is equal to V_{ref_1}(R₁ + R₂)/R₂. Turn on-time of S₁ is obtained by comparing the error signal v_comp1, and the sawtooth waveform signal v_saw. CRM control is achieved by detecting the zero crossing of inductor current through the signal v_ZCD. v_FB is the sensed signal of total output voltage v_o divided by the resistance R₃ and R₄ in the control circuit of the Buck RCC; the error signal v_comp1 is obtained by comparing the voltage feedback signal v_FB and the 1.205 V reference voltage V_{ref_2}. Total output voltage v_o is equal to V_{ref_2}(R₃ + R₄)/R₄. The duty cycle of driving signal v_g1 for the switch S₂ of Buck RCC is obtained by the PWM modulator comparing error signal v_comp1 and the inductor L₂ current sensing signal v_cs.bck. In addition, due to the high side, the N-Mosfet of Buck RCC needs an extra driver circuit; it is best to choose a controller with integrated the level shifted gate driver for the external high side N-Mosfet of the Buck RCC control chip in order to simplify circuit design.

2.2. Operating Mode of Dual Output Hybrid Boost/Flyback PFC Converter

Figure 2 depicts the waveforms of the primary current i_Lp and secondary current i_Ds of transformer T₁ in a half line cycle. From the key waveforms of Figure 2, there are two operating modes, including Boost mode and Flyback mode, in a half line cycle. α and π-α are the transition angles of operation mode, Boost mode operates in [α, π-α], and Flyback mode operates in [0, α] and [π-α, π].

Observing Figure 2, it is shown that the inductor L_p is operated in CRM. The waveform of the primary inductor current i_Lp in [α, π-α] is identical to that of the conventional CRM Boost converter, the waveforms of i_Lp and i_Ds in [0, α] and [π-α, π] are identical to that of the conventional CRM Flyback converter.

Figure 1a shows that v_rec is the rectified input voltage, v_TP is the voltage of transformer T₁ primary winding, v_TS is the voltage of transformer T₁ secondary winding. The output voltage v_o2 of the Flyback converter should be much lower than the output voltage v_o1 of the Boost converter because only a small amount of power is sent to the output through the secondary of the Flyback converter. The operation principle of the two modes and the critical condition of operation mode transition is as follows. The equivalent circuits of Boost mode and Flyback mode of dual output hybrid Boost/Flyback PFC converter are shown in Figure 3 and Figure 4, respectively.

The equivalent circuits of the Boost mode of dual output hybrid Boost/Flyback PFC converter are shown in Figure 3. Buck RCC, which is powered by C₂, operates independently without the effects of two modes, i_o2 is the output current of auxiliary output. As shown in Figure 2 and Figure 3a, when S₁ is turned on, the current i_Lp flowing through L_p and S₁ starts to increase from zero, and v_TP is equal to v_rec. As shown in Figure 2 and Figure 3b, when S₁ is turned off, the diode D₂ is forward biased, the diode D_S is reverse biased, and the direction of the voltage of L_p is converted due to the direction of the inductor current cannot be changed abruptly, the current i_Lp flowing through L_p, D₂, and C₁ decreases.

The equivalent circuits of the Flyback mode of dual output hybrid Boost/Flyback PFC converter are shown in Figure 4. As shown in Figure 2 and Figure 4a, when S₁ is turned on, L_p is charged, the current i_Lp flowing through L_p and S₁ starts to increase from zero, v_TP is equal to v_rec. As shown in Figure 2 and Figure 4b, when S₁ is turned off, the diode D_S is forward biased, D₂ is reverse biased, at this time, the sum of v_TP and v_rec is less than v_o1, the diode D₂ remains reversely biased, the current i_Ds flowing through secondary side winding of transformer T₁, D_S, and C₂ decreases.

The dual output hybrid Boost/Flyback PFC converter operates in Boost mode when D_S is reversed biased, and D₂ is forward biased during S₁ turned off because v_TS reflected from v_TP is lower than v_o2 during S₁ turned off near the peak rectified input voltage v_rec. Otherwise, the dual output hybrid Boost/Flyback PFC converter operates in Flyback mode when D_S is forward biased, and D₂ is reversed biased near the cross zero point of rectified input voltage v_rec.

According to the above operation analysis, the critical condition for the operation mode transition of dual output hybrid Boost/Flyback PFC converter can be expressed as

$$\{\begin{array}{l}{v}_{o1}<N{v}_{o2}+V_m\left|\sin (\omega t)\right|,\omega t\in (\alpha ,\pi -\alpha )\\ v_{o1}>N{v}_{o2}+V_m\left|\sin (\omega t)\right|,\omega t\in (0,\alpha )\cup (\pi -\alpha ,\pi )\end{array}$$

(1)

where V_m represents the magnitude of AC input voltage, N represents winding turns ratio N₁/N₂, and ω represents the angular frequency of AC input voltage.

From (1), it can be seen that the operation mode transition is not related to the control strategy but rather to input voltage, turn ratio N, v_o1, and v_o2. During the half-line cycle, first, dual output hybrid Boost/Flyback PFC converter operates in Flyback mode when ωt is from 0 to α; second, the converter enters Boost mode when ωt is from α to π − α; finally, the converter operates in Flyback mode again when ωt is from π − α to π.

2.3. Analysis of Output Voltage Ripple Suppression of Buck RCC

To analyze the suppression ability of twice-line output voltage ripple for Buck RCC, the equivalent circuit and small signal model of Buck RCC are shown in Figure 5 and Figure 6, respectively. Figure 5 shows that v_o1 and v_o2 of the dual output hybrid Boost/Flyback converter can be equivalent to two DC sources because the twice-line frequency is substantially less than the switching frequency of Buck RCC. v_B and i_B are considered as the output voltage, and the output current of Buck RCC and output impedance can be considered as Z_RCC, as shown in Figure 5 [11,12,13]. Although the output load of the proposed converter is usually a post-stage DC-DC converter, the output load can be assumed as a pure resistive load during analyzing the suppression ability of twice-line output voltage ripple for Buck RCC [11,12,13].

According to Figure 5, a small signal model of Buck RCC is built, as shown in Figure 6. Supposed D_b is the steady-state duty cycle of Buck RCC.

Load impedance R_o and output impedance Z_RCC(s) are in series connection and jointly divide the twice-line-frequency ripple of v_o1. For the convenience of investigating the suppression ability of Buck RCC on twice-line-frequency ripple, output voltage ripple ratio k of v_o.rip and v_o1.rip is defined as $k=v_{o.rip}/v_{o1.rip}$. Observing Figure 6, output voltage ripple ratio k also can be considered as the ratio of load impedance R_o and output impedance Z_RCC(s) [11,12,13]; k can be expressed as

$$k=\frac{R_o}{R_o+\left|Z_{RCC}(s)\right|}$$

(2)

According to the definition of k, a low twice-line frequency output voltage ripple means that v_o.rip is much smaller than v_o1.rip. Therefore, to achieve low output voltage ripple, the amplitude of Z_RCC(s) at twice-line frequency should be much greater than load impedance R_o.

According to Figure 6, open loop output impedance Z_RCC(s) is obtained as

$$Z_{RCC}(s)={\frac{{\widehat{v}}_o(s)}{{\widehat{i}}_o(s)}|}_{{\widehat{v}}_{o1}(s)={\widehat{v}}_{o2}(s)={\widehat{d}}_b(s)=0}=\frac{s{L}_2{R}_o}{s^2{C}_3{L}_2{R}_o+s{L}_2+R_o}$$

(3)

From Figure 6, the following open loop transfer function G_o1(s) of total output voltage to main output voltage, G_o2(s) of total output voltage to auxiliary output voltage, and G_d(s) of total output voltage to duty cycle can be given as

$$G_{o1}(s)={\frac{{\widehat{v}}_o(s)}{{\widehat{v}}_{o1}(s)}|}_{{\widehat{v}}_{o2}(s)={\widehat{d}}_b(s)=0}=\frac{s^2{C}_3{L}_2{R}_o+R_o}{s^2{C}_3{L}_2{R}_o+s{L}_2+R_o}$$

(4)

$$G_{o2}(s)={\frac{{\widehat{v}}_o(s)}{{\widehat{v}}_{o2}(s)}|}_{{\widehat{v}}_{o1}(s)={\widehat{d}}_b(s)=0}=\frac{D_b{R}_o}{s^2{C}_3{L}_2{R}_o+s{L}_2+R_o}$$

(5)

$$G_d(s)={\frac{{\widehat{v}}_o(s)}{{\widehat{d}}_b(s)}|}_{{\widehat{v}}_{o1}(s)={\widehat{v}}_{o2}(s)=0}=\frac{V_{o2}{R}_o}{s^2{C}_3{L}_2{R}_o+s{L}_2+R_o}$$

(6)

According to the control circuit of Buck RCC, as shown in Figure 1a, and the analysis method of ac small signal model of Buck RCC under PCM control in [11,12], small signal perturbation of D_b can be expressed as

$${\widehat{d}}_b(s)=F_c\left[F_{ref}(s)\left({\widehat{v}}_{ref}(s)-H{\widehat{v}}_o(s)\right)-{\widehat{i}}_{L2}(s)-F_{o2}{\widehat{v}}_{o2}(s)-F_o{\widehat{v}}_B(s)\right]$$

(7)

where ${\widehat{v}}_o(s)$, ${\widehat{v}}_{o2}(s)$, ${\widehat{v}}_B(s)$, ${\widehat{v}}_{ref}(s)$ and ${\widehat{i}}_{L2}(s)$ represents small signal perturbation of v_o, v_o2, v_B, v_ref, and i_L2, H is the sampling factor of total output voltage v_o, F_ref(s) is the transfer function of the compensator which is the Type II compensator in the voltage loop of Buck RCC control circuit, and F_c, F_o2, F_o, F_ref(s) are shown as

$$F_c=\frac{1}{m_s{T}_b}$$

(8)

$$F_{o2}=\frac{D_b^2{T}_b}{2L_2}$$

(9)

$$F_o=\frac{1-2D_b}{2L_2}{T}_b$$

(10)

$$F_{ref}(s)=\frac{1+s{R}_6{C}_5}{s{R}_5(C_4+C_5)(1+s{R}_6\frac{C_4{C}_5}{C_4+C_5})}$$

(11)

where m_s is considered as the sawtooth slope of the compensation signal in the current control loop, and T_b is the switching period of S₂ in Buck RCC.

According to Figure 6, the relation between the current and voltage of Buck RCC is given by

$${\widehat{i}}_{L2}(s)=s{C}_3{\widehat{v}}_B(s)+{\widehat{i}}_B(s)$$

(12)

$${\widehat{v}}_o(s)={\widehat{v}}_{o1}(s)+{\widehat{v}}_B(s)$$

(13)

$${\widehat{v}}_B(s)=D_b{\widehat{v}}_{o2}(s)+{\widehat{d}}_b(s)V_{o2}-s{L}_2{\widehat{i}}_{L2}(s)$$

(14)

According to (7) and (12)–(14), the close loop output impedance Z_{B_RCC}(s) is given by

$$Z_{B\_RCC}(s)=\frac{s{L}_2+F_c{V}_{o2}+R_{o}H{F}_{ref}(s)F_c{V}_{o2}}{s^2{L}_2{C}_3+s{C}_3{F}_c{V}_{o2}+1+F_o{F}_c{V}_{o2}}$$

(15)

From (2) and (15), the output voltage ripple ratio k is given by

$$k=\frac{R_o}{R_o+Z_{B\_RCC}(s)}$$

(16)

As shown in

Table 1. Key circuit parameters of the hybrid QSS AC-DC converter.

Symbol	Design Parameter	Value
vin	RMS value of AC input voltage	100~240 V
vo1	Main output voltage	380 V
vo	Output voltage	400 V
Po	Output power	120 W
f	Line frequency	50 Hz
Tb	Switching period of Buck RCC	6.667 μs
Lp	Primary inductance of T1	0.5 mH
	Transformer core model	PQ32/25
L2	Inductance of Buck RCC	100 µH
N1:N2:N3	Winding turns ratio of T1	60:12:6
C1	Output capacitor of Boost mode	100 μF
C2	Output capacitor of Flyback mode	330 μF
C3	Output capacitor of Buck RCC	10 μF
S1	Switch of hybrid Boost/Flyback PFC converter	FCPF190N65FL1
S2	Switch of Buck RCC	FDMS86200
D3	Freewheeling diode of Buck RCC	MBR40250
D2	Freewheeling diode of Boost mode	RHRP1560
DS	Freewheeling diode of Flyback mode	U1560

, the related main parameters of Buck RCC are: L₂ = 100 µH, C₃ = 10 µF, C₄ = 220 pF, C₅ = 100 nF, R_o = 1.333 kΩ, R₅ = 100 kΩ, R₆ = 1 kΩ, T_b = 6.667 μs, m_s = 0.06 A/µs, V_B = 20 V, H = 3 × 10⁻³. Based on the calculation result later, V_o2 is around 63 V with 110 Vac input voltage and rated load current. According to (16), the Bode plot of the output voltage ripple ratio k is shown in Figure 7.

Based on the definition of k, it can be known that the smaller the value of k, the more effectively the output voltage ripple is suppressed. According to Figure 7, the magnitude of the Bode plot of k from 1 Hz to 100 Hz is about −55.87 dB, and the value of k is about 1.6 × 10⁻³ with 110 Vac input voltage, so the suppression ability of twice-line output voltage ripple for Buck RCC is achieved well.

3. Parameters Design and Characteristics Analysis

3.1. Operation Mode Transition Angle

The critical conditions of operation mode transition angle α are presented in the above analysis. In order to calculate operation mode transition angle α, conduction time t_on, input and output power of the proposed converter are analyzed. t_on is constant when the proposed converter operates in both modes with stable input voltage and output load because the converter is controlled using the classical constant on-time control strategy of CRM.

The average current i_Lp.bst of L_p of dual output hybrid Boost/Flyback PFC converter operates in Boost mode is obtained as

$$i_{Lp.bst}(t)=\frac{V_m\left|\sin (\omega t)\right|}{2L_p}{t}_{on}$$

(17)

where the conduction time of switch S₁ in a switching period is represented by t_on.

Input power P_in.bst in Boost mode during half line cycle is obtained as

$$P_{in.bst}=V_{o1}{I}_o=\frac{1}{\pi }{\displaystyle {\int }_{\alpha }^{\pi -\alpha }{V}_m\left|\sin (\omega t)\right|i_{Lp.bst}(t)d(\omega t)}=\frac{V_m^2{t}_{on}}{2\pi L_p}(\frac{\pi }{2}-\alpha +\frac{\sin (2\alpha )}{2})$$

(18)

where I_o represents the output current through load resistor R_O, and V_o1 represents the average value of v_o1.

According to (18), conduction time t_on can be expressed as

$$t_{on}=\frac{2\pi V_{o1}{I}_o{L}_p}{V_m{}^2(\frac{\pi }{2}-\alpha +\frac{\sin 2\alpha }{2})}$$

(19)

Peak current i_peak.flk of the primary winding of transformer T₁ in Flyback mode can be given as

$$i_{peak.flk}(t)=\frac{V_m\left|\sin (\omega t)\right|}{L_p}{t}_{on}$$

(20)

The conduction time t_Ds(t) of D_S is expressed as

$$t_{Ds}(t)=\frac{i_{peak.flk}(t)L_p}{N{V}_{o2}}=\frac{V_m\left|\sin \left(\omega t\right)\right|}{N{V}_{o2}}{t}_{on}$$

(21)

where V_o2 represents the average value of v_o2.

The switching period T_s.flk of S₁ which is variable since the primary inductor L_p is operated in CRM, then the period T_s.flk can be expressed as

$$T_{s.flk}(t)=t_{on}(1+\frac{V_m}{N{V}_{o2}}\left|\sin (\omega t)\right|)$$

(22)

Input power P_in.flk of the proposed converter operating in Flyback mode during half line cycle can be expressed as

$$P_{in.flk}=V_B\cdot I_o=\frac{1}{\pi }\left({\displaystyle {\int }_0^{\alpha }\frac{L_p{i}^2{}_{peak.flk}(t)}{T_{s.flk}(t)}}d(\omega t)\right)=\frac{V_m^2{t}_{on}}{\pi L_p}{\displaystyle {\int }_0^{\alpha }\frac{{\sin }^2(\omega t)}{(1+\frac{V_m}{N{V}_{o2}}\left|\sin (\omega t)\right|)}}d(\omega t)$$

(23)

where V_B represents the average value of v_B.

From (23), the expression of conduction time t_on can be obtained as

$$t_{on}=\frac{\pi L_p{V}_B{I}_o}{V_m^2{\displaystyle {\int }_0^{\alpha }\frac{{\sin }^2(\omega t)}{1+\frac{V_m}{N{V}_{o2}}\left|\sin (\omega t)\right|}}d(\omega t)}$$

(24)

According to (1), when ωt is α, NV_o2 is equal to V_o1 − V_m sinα. The conduction time t_on during two operation modes should be constant, from (19) and (24); the below equation can be obtained.

$$\frac{V_B}{2V_{o1}}(\frac{\pi }{2}-\alpha +\frac{\sin 2\alpha }{2})={\displaystyle {\int }_0^{\alpha }\frac{{\sin }^2\left(\omega t\right)}{(1+\frac{V_m\left|\sin (\omega t)\right|}{V_{o1}-V_m\sin \alpha })}}d(\omega t)$$

(25)

From (25) and the main parameters in Table 1, the curve of operation mode transition angle α with input voltage is shown in Figure 8.

Figure 8 shows that the operation mode transition angle α increases from π/5.99 to π/5.41 with the variation of input voltage v_in from 100 Vac to 240 Vac.

3.2. Design of Transformer T₁

According to (19) and volt-second balance, the switching frequency f_s.bst of S₁ as the proposed converter operates in Boost mode, L_p can be expressed as

$$L_p=\frac{\left(V_{o1}{V}_m^2-V_m^3\left|\sin (\omega t)\right|\right)(\frac{\pi }{2}-\alpha +\frac{\sin 2\alpha }{2})}{2\pi V_{o1}^2{I}_o{f}_{s.bst}}$$

(26)

As shown in the parameters of the hybrid QSS AC-DC converter in Table 1, V_o1 is 380 V, I_o is 0.3 A according to (26), through setting the lowest switching as 30 kHz, the curve of the maximum inductance with different input voltage is shown in Figure 9.

According to Figure 9, to ensure the switching frequency is greater than 30 kHz, the inductance of L_p should be less than 0.54 mH, so the inductance L_p of transformer T₁ in this paper is taken as 0.5 mH.

According to (19) and (24), the relation of NV_o2 and input voltage v_in can be expressed as

$${\displaystyle {\int }_0^{\alpha }\frac{{\sin }^2\left(\omega t\right)}{(1+\frac{V_m\left|\sin (\omega t)\right|}{N{V}_{o2}})}}d(\omega t)=\frac{V_B}{2V_{o1}}(\frac{\pi }{2}-\alpha +\frac{\sin 2\alpha }{2})$$

(27)

According to Figure 8 and (27), with the condition of V_B = 20 V and V_o1 = 380 V, the curve of NV_o2 with input voltage variation from 100 Vac to 240 Vac is shown in Figure 10. According to Figure 10, it is shown that NV_o2 decreases from 323 V to 232 V with the variation of input voltage v_in from 100 Vac to 240 Vac. To achieve high efficiency and low voltage stress of S₂, D₃, and C₂, the voltage of V_o2 should be as close as possible to the auxiliary output voltage v_B. However, to ensure the stability of PCM control of Buck RCC, it is better to maintain the duty cycle of Buck RCC to be smaller than 50%. Therefore, considering the efficiency, cost, and stability of Buck RCC comprehensively, the turn ratio N is set as 5, and the theoretical value of V_o2 is from 64.6 V to 46.4 V with the variation of input voltage v_in from 100 Vac to 240 Vac.

3.3. Input Current

From (17) and (20), input current i_in(t) of the hybrid QSS AC-DC converter can be written as

$$i_{in}(t)=\{\begin{array}{l}\frac{\pi V_{o1}{I}_o\left|\sin (\omega t)\right|}{V_m(\frac{\pi }{2}-\alpha +\frac{\sin (2\alpha )}{2})},\omega t\in \left(\alpha ,\pi -\alpha \right)\\ \frac{\pi V_{o1}{I}_o\left|\sin (\omega t)\right|}{V_m(\frac{\pi }{2}-\alpha +\frac{\sin (2\alpha )}{2})\left(1+\frac{V_m\left|\sin (\omega t)\right|}{V_{o1}-V_m\sin \alpha }\right)},\omega t\in (0,\alpha )\cup (\pi -\alpha ,\pi )\end{array}$$

(28)

According to (28), the curve of input current within half line cycle at 100 Vac, 110 Vac, 220 Vac, and 240 Vac input voltage is shown in Figure 11. From Figure 11, it can be seen that the curve of input current is close to sinusoidal. However, significant distortion appeared in the input current due to difference between the input current of the two Boost and Flyback modes occurring at operation mode transition angle α.

3.4. Power Factor and Total Harmonic Distortion

According to (28), the power factor (PF) of the hybrid QSS AC-DC converter can be expressed as

$$PF=\frac{\frac{2}{\pi }{\displaystyle {\int }_0^{\alpha }{i}_{in.flk}(t)V_m\sin (\omega t)d\left(\omega t\right)}+\frac{1}{\pi }{\displaystyle {\int }_{\alpha }^{\pi -\alpha }{i}_{in.bst}(t)V_m\sin (\omega t)d\left(\omega t\right)}}{\frac{1}{\sqrt{2}}{V}_m\sqrt{\frac{2}{\pi }{\displaystyle {\int }_0^{\alpha }{\left(i_{in.flk}(t)\right)}^{2}d\left(\omega t\right)}+\frac{1}{\pi }{\displaystyle {\int }_{\alpha }^{\pi -\alpha }{\left(i_{in.bst}(t)\right)}^{2}d\left(\omega t\right)}}}$$

(29)

where i_in.flk(t) and i_in.bst(t) are the expressions of the input current of the hybrid QSS AC-DC converter operating in Flyback mode and Boost mode, respectively.

According to (29), it is assumed that the phase difference between AC input voltage and input current is ignored, and the total harmonic distortion (THD) of the input current of the hybrid QSS AC-DC converter can be expressed as

$$\mathrm{THD}=\sqrt{\frac{1}{{\left(\frac{\frac{2}{\pi }{\displaystyle {\int }_0^{\alpha }{i}_{in.flk}(t)V_m\sin (\omega t)d\left(\omega t\right)}+\frac{1}{\pi }{\displaystyle {\int }_{\alpha }^{\pi -\alpha }{i}_{in.bst}(t)V_m\sin (\omega t)d\left(\omega t\right)}}{\frac{1}{\sqrt{2}}{V}_m\sqrt{\frac{2}{\pi }{\displaystyle {\int }_0^{\alpha }{\left(i_{in.flk}(t)\right)}^{2}d\left(\omega t\right)}+\frac{1}{\pi }{\displaystyle {\int }_{\alpha }^{\pi -\alpha }{\left(i_{in.bst}(t)\right)}^{2}d\left(\omega t\right)}}}\right)}^2}-1}\times 100\%$$

(30)

From (29) and (30), the curves of PF and input current THD with different input voltage are depicted in Figure 12. From Figure 12, it is shown that high PF and low THD can be achieved, although there is slight input current distortion during the operation mode transition. The highest PF is 0.9993, and the lowest THD is 3.52% when v_in is 100 Vac; the lowest PF is 0.9932, and the highest THD is 11.6% when v_in is 240 Vac.

3.5. Switching frequency

According to (22) and (26), the operating frequency of S₁ can be expressed as

$$f_S=\{\begin{array}{l}\frac{\left(V_{o1}{V}_m^2-V_m^3\left|\sin (\omega t)\right|\right)(\frac{\pi }{2}-\alpha +\frac{\sin 2\alpha }{2})}{2\pi L_p{V}_{o1}^2{I}_o},\omega t\in (\alpha ,\pi -\alpha )\\ \frac{V_m{}^2\left(V_{o1}-V_m\sin \alpha \right)(\frac{\pi }{2}-\alpha +\frac{\sin 2\alpha }{2})}{\left(V_{o1}-V_m\sin \alpha +V_m\left|\sin (\omega t)\right|\right)2\pi L_p{V}_{o1}{I}_o},\omega t\in (0,\alpha )\cup (\pi -\alpha ,\pi )\end{array}$$

(31)

From (31), the curve of the operating frequency of S₁ with the variation of v_in from 100 Vac to 240 Vac is shown in Figure 13.

In Figure 13, the switching frequency at ωt = π/2 with input voltage 110 Vac is about 57 kHz. The range of switching frequency is from 50 kHz to 460 kHz. The design of the primary inductance and winding turn of L_p depends on the minimum frequency and peak current i_Lp flowing through the primary winding of L_p [32]. Because of the wide variation range of switching frequency, the cut-off frequency of the input EMI filter should be lower than the lowest switching frequency. Moreover, to avoid extremely high switching frequencies that damage the Mosfet and Diode, the CRM PFC controller usually limits the maximum switching frequency or minimum turning-off time.

4. Experimental Verification

A 120 W experimental prototype is built in the laboratory to verify the correctness of the theoretical analysis. The specifications and main component parameters of the hybrid QSS AC-DC converter in the experiment are shown in Table 1.

The experimental prototype and platform of the hybrid QSS AC-DC PFC converter are shown in Figure 14 and Figure 15.

The experimental waveforms of input voltage v_in, input current i_in, total output voltage v_o, main output voltage v_o1, and auxiliary output voltage v_B with 110 Vac and 220 Vac are shown in Figure 16. From waveforms, it is shown that the twice-line-frequency ripple of v_o1 is suppressed using Buck RCC, and input current i_in is in phase with input voltage v_in. Compared to i_in within input voltage 110 Vac, there is a more significant distortion appearing in input current i_in with input voltage 220 Vac as seen in Figure 16. The PF is 0.996 and 0.984 at input voltages 110 Vac and 220 Vac, which is measured using the power analyzer, so the hybrid QSS AC-DC PFC converter can realize the PFC function.

The experimental waveforms of v_rec, i_Lp, and i_Ds with 110 Vac input voltage and rated output load are shown in Figure 17. Figure 17a illustrates that the hybrid QSS AC-DC PFC converter operates at Flyback mode near the cross zero point of rectified input voltage v_rec, and the hybrid QSS AC-DC PFC converter operates at Boost mode near the peak of rectified input voltage v_rec. As illustrated in Figure 17b,c, L_p operates in CRM during both Boost and Flyback modes; the switching frequency is about 50 kHz near the peak of v_rec during Boost mode.

The experimental waveforms of v_rec, i_Lp, i_Ds with 110 Vac input voltage at 50% and 10% output load conditions are shown as Figure 18 and Figure 19, respectively. According to Figure 18 and Figure 19, it can be seen that the proposed converter can operate well at 50% and 10% output load, and the operation mode transition process of 50% and 10% output load are similar to rated output load. Moreover, comparing the switching frequency in Figure 17, Figure 18 and Figure 19, it can be concluded that the smaller the output load power, the higher the switching frequency; this conclusion is consistent with the formula (30).

The total output voltage v_o and its ripple v_o.rip with input voltage 110 Vac is shown in Figure 20. The ripple v_o.rip is about 500 mV, and the ripple amplitude ranges within 0.125% of the total output voltage amplitude. According to experimental results, twice-line-frequency ripple is effectively suppressed in the hybrid QSS AC-DC converter.

With rated output power, the experimental results of PF, efficiency, and THD curves of the proposed converter within the input voltage from 100 Vac to 240 Vac are shown in Figure 21. In the overall input voltage range, the PF almost remains above 0.978, the maximum efficiency of the system is up to 96%, and the THD can be low to 4.5%. Comparing the theoretical analysis in Figure 12 and the experimental results in Figure 21, it can be seen that the experimental result of PF is lower than the theoretical prediction; the experimental result of THD is higher than the theoretical prediction, especially at high input voltage. When conducting theoretical derivation of PF and THD, it is supposed that there is no phase difference between input voltage and input current, and the conduction time t_on of switch S₁ is constant within half line cycle. However, the capacitor of the EMI filter and C_f of the LC filter after rectifier D₁ can cause the input current phase to lead the input voltage phase, especially at high input voltage, the slight twice line frequency ripple of the output voltage v_comp1 of error amplifier of PFC control circuit can cause slight variation of conduction time t_on of switch S₁. Therefore, the variation of the conduction time of S₁ and the phase difference between the input voltage and input current will make the PF and THD of the experimental result worse than the theoretical prediction.

The experimental results of PF, efficiency, and THD curves of the proposed converter at the 110 Vac and 220 Vac input voltage within from 10% to 100% output load power are shown in Figure 22. From Figure 22a, the PF of the proposed converter is increased from 0.958 to 0.996 with output load power variation from 10% to 100% at 110 Vac input voltage, and PF is increased from 0.75 to 0.984 with output load power variation from 10% to 100% at 220 Vac input voltage. From Figure 22b, the efficiency is increased from 71.9% to 92.5% with output load power variation from 10% to 100% at 110 Vac input voltage, and the efficiency is increased from 82.1% to 95.8% with output load power variation from 10% to 100% at 220 Vac input voltage. From Figure 22c, THD is decreased from 16% to 5.19% with an output load power variation of 10% to 100% at 110 Vac input voltage, and THD is decreased from 39% to 14.31% with output load power variation from 10% to 100% at 220 Vac input voltage.

The comparison results of IEC61000-3-2 Class C requirements and the harmonic content test results of input current with rated 120 W output power, 110 Vac, and 220 Vac input voltage are shown in Figure 23. It shows that the proposed hybrid QSS AC-DC converter can meet the harmonic standard limit of IEC61000-3-2 Class C.

The comparison of key performance parameters between the proposed converter, traditional CRM Boost PFC converter, quadratic Boost PFC converter, and QSS Flyback PFC converter at 110 Vac and 220 Vac are shown in

Table 2. Performance comparison.

	h (%)		PF		THD (%)		Efficiency (%)
	110 V	220 V	110 V	220 V	110 V	220 V	110 V	220 V
Traditional Boost PFC converter [33]	7%	9%	0.993	0.956	4.2	7.8	94.8	96.7
Quadratic Boost PFC converter [20]	0.25%	0.57%	0.983	0.924	16.99	36.44	89.8	93.1
Quasi-single-stage Flyback PFC converter [12]	0.21%	0.6%	0.992	0.976	10.12	25.82	85.5	88.1
Proposed hybrid QSS AC-DC converter	0.125%	0.3%	0.996	0.984	5.19	14.31	92.5	95.8

.

In order to be convenient to indicate the value of output voltage ripple, the ratio h of output voltage ripple and total output voltage is defined as

$$h=\frac{v_{o.rip}}{v_o}\times 100\%$$

(32)

Table 2 shows that compared to the quadratic Boost PFC converter and QSS Flyback PFC converter, PF and efficiency of the hybrid QSS AC-DC converter are significantly improved; the efficiency of the proposed converter is slightly lower that of traditional Boost PFC converter, THD of the proposed converter is slightly higher than that of traditional Boost PFC converter because of slight distortion of the input current of the proposed converter during Boost mode and Flyback mode transition, but more effective suppression of twice-line-frequency ripple is realized by proposed converter in this paper [12,20,33]. Therefore, the proposed hybrid QSS AC-DC converter can conveniently achieve high PF, high efficiency, low THD, and extremely low twice-line frequency output voltage ripple simultaneously.

5. Conclusions

A hybrid QSS AC-DC converter consisting of a dual output hybrid Boost/Flyback PFC converter and a Buck RCC is proposed in this paper. To achieve a low twice-line-frequency ripple of output voltage, Buck RCC is connected in series with the main output of dual output hybrid Boost/Flyback PFC converter, a twice-line-frequency ripple which is the same amplitude and opposite phase of the main output of dual output hybrid Boost/Flyback PFC converter is generated using Buck RCC. Since only a small amount of input power is converted to output load through the Flyback converter and RCC two-stage conversion, high efficiency is easy to implement. The operation principle, the critical condition of operation mode transition, and the main characteristics, including operation mode transition angle, input current, power factor, and switching frequency, are presented, and a small signal model of Buck RCC verifies that the twice-line-frequency ripple is effectively suppressed. Based on the experimental results of the 120 W experimental prototype, it is verified that the proposed hybrid QSS AC-DC converter can conveniently achieve high PF, high efficiency, low THD, and extremely low twice-line frequency output voltage ripple simultaneously.