Decoupling Capacitors Placement at Board Level Adopting a Nature-Inspired Algorithm

Abstract

Decoupling capacitors are fundamental keys for the reduction of transient noise in power delivery networks; their arrangement and values are crucial for reaching this goal. This work deals with the optimization of the decoupling capacitors of a power delivery network by using a nature-inspired algorithm. In particular, the capacitance value and the location of three decoupling capacitors are optimized in order to obtain an input impedance below a specific mask, by using a nature-inspired algorithm, the genetic one, in combination with two electromagnetic solvers used to compute the objective function. An experimental board is designed and manufactured; measurements are performed to validate the numerical results.

1. Introduction

The requests, coming from the market and incorporated by the industry, are more and more steered toward a miniaturization of the devices with the target to improve their performances. All these efforts are not costless: Shrinking the device dimensions implies a non-negligible number of problems such as degradation of the signal quality, increase in heat dissipation problems, and manufacturing complexity. All these aspects result in a collection of power and signal integrity issues [1,2].

Among the several causes that can lead to signal integrity (SI) problems, the power integrity (PI) related to the power/ground supply voltage at board level is one of the central requirements of modern design; having a power distribution network (PDN) defined by a high inductance or spending not enough time and effort on the PDN impedance design can cause severe PI issues [3]. Adopting decoupling capacitances (decaps) [4] is an effective solution in the optic of the reduction of transient noise caused by voltage droop due to the switching currents. A manual placement of decaps can lead to not optimal solution and can be time consuming; for these reasons, CAD tools and new algorithms [5,6,7,8] try to propose automatic procedures for the decaps arrangement. However, handling a large amount of decaps can lead to an increase of the power consumption, to reliability issues, and to a decrease of component space available on board [9]. As a result, a trade-off between the number of decaps, as well as their values, and their proper arrangement on board is a must for today’s board design to fulfill all the requirements.

At the early stage of a printed circuit board (PCB) design and in particular its PDN, an optimization procedure might help and assist the designers providing a powerful tool from the selection of the electrical and geometrical parameters of the stack-up, to the appropriate placement of each decaps. This convenient and rational design aims to drastically reduce the signal and power integrity issues.

The nature-inspired algorithms (NIAs) [10,11] are a class of optimization algorithms inspired by natural mechanisms. They also include particle swarm optimization (PSO) [12], evolutionary algorithms (EA) [12], and genetic algorithms (GA) [13,14]. PSO is a population-based stochastic optimization technique; compared to EA and GA, the advantages of PSO are that it is easy to implement and there are few parameters to adjust. At the same time, not having evolution operators such as crossover and mutation, its efficiency in exploring the solution domain of the considered problem is limited. On the other hand, for the considered application, EA and GA have shown the highest efficiency from the computational point of view. Between them, GAs have a simpler architecture of the code. Computational efficiency and software architecture simplicity have stirred the choice of GAs as optimization algorithm for this work. The aim of this work is to explore, starting from simple configurations, the use of GAs as suitable algorithms for the optimization of the decoupling capacitance on a PDN at board level. In the following, a GA is adopted for finding the optimum number and values of decaps to be mounted on a simple PDN of a printed circuit board (PCB) with the goal to have an input impedance of the PDN below a specific mask selected by the designer based on the design specifications. The input impedance is evaluated through two different tools: EZpp [15,16,17] and PI/EMI analysis module within design force (from now on named “DF PI”) (by Zuken [18]). The results will be the base for more realistic and complex analysis that will be carried out in the continuation of this research.

The paper is organized as follow: Section 2 describes the test board, in terms of geometry, stack-up, and materials. In the same section, there is a part concerning the main differences between the two solvers EZpp and DF PI. Section 3 is devoted to the GA describing the steps composing the algorithm. Section 4 shows the results of the optimization of decaps value; Section 5 reports the results of the optimization of both decaps value and their position. In Section 6, the proposed approach is validated by comparing the computed results with those measured on a specifically designed PDN board. Finally Section 7 discusses the significant outcomes and introduces the future steps of this research.

2. Overview of the Test Board

The test structure considered in this investigation, as shown in Figure 1, is a two-layer board built by two copper planes (electrical conductivity σ_cu = 58 MS/m, thickness t_cu = 0.03 mm) representing a PDN with power (PWR) and ground (GND) planes, separated by a FR4 dielectric slab (relative dielectric permittivity ε_r = 4.3, loss tangent tgδ = 0.02, thickness t_FR4 = 0.25 mm).

Figure 1 also shows the port P, from which the input impedance Z_in of the PDN is evaluated during the optimization process. The target of the optimization is to find suitable values for the capacitances of N_pos = 3 decaps (C₁, C₂, C₃) placed at fixed positions near the input port P (blue squares in Figure 1a). In Section 5, the position of the decaps will become an optimization variable. Capacitors’ parasitic inductance (ESL) and resistance (ESR) are kept fixed and equal to 50 nH and 30 mΩ, respectively. These stray parameters can be considered a sort of average values among those associated to the 0603 to the 0805 packages of the AVX Y5V series. The coordinates of the input port P and of the three decaps are summarized in

Table 1. Coordinates of the input port P and the three decoupling capacitors (C₁, C₂, C₃).

Parameter	Description	x (mm)	y (mm)
P	Input Port	30	110
C1	Decoupling capacitance	10	160
C2	Decoupling capacitance	90	160
C3	Decoupling capacitance	90	80

.

Before proceeding with the optimization task, a comparison between the outputs from EZpp and those from DF PI has been done in order to detect the possible differences between the results. Consequently, the Z_in without decoupling capacitances has been computed by the two solvers and compared (Figure 2). Up to almost 50 MHz, the predominant factor is the capacitance of the planes, as justified by the capacitive trend of Z_in at low frequency. The equivalent capacitance can be quantified as:

$$C_{theory}={\epsilon }_r{\epsilon }_0\frac{A}{d}$$

(1)

where ε₀ is the vacuum permittivity, A is the area of the board and t_FR4 = 0.25 mm is the distance between the two planes. EZpp and DF PI provide a capacitance value very close to Equation (1), as reported in

Table 2. Capacitance value extracted at 1 MHz from Z_in (Figure 2).

Solver	Capacitance (nF)
EZpp	10.86
DF PI	10.75
Theory (Equation (1))	10.78

.

The largest difference between the results from the two solvers can be appreciated at high frequency, where Z_in from DF PI exhibits an excess of inductance with respect to that from EZpp. This inductance can be quantified importing, in the circuit simulator Advanced Design System (ADS) [19], the S-parameters from the simulations without decaps and then adding a tunable series inductance between the termination port and the S-Parameter block of the circuit associated to the EZpp results, as depicted in Figure 3a. Tuning the inductance L1, the matching between the frequency spectra of the input impedance from the two solvers (Figure 3b) is reached using an inductance of L1 = 1.20 nH. According to the IEEE Standard P1597 [20], the feature selective validation technique [20,21,22] is used to quantify the matching of the two curves in Figure 3b. The matching is classified as “excellent” [20] being the FSV figure of merits GRADE = 1 and SPREAD = 1.

The extra inductance L1 is introduced by the DF PI model due to the presence of traces and vias (see inset of Figure 3b), which create the connections of each component with the GND and PWR planes.

This conclusion is corroborated by a procedure in which the trace length l_trace (Figure 4a) is changed and the behavior of the input impedance is analyzed. In fact, if l_trace is changed from 0 (no traces, but vias) to 10 mm, Z_in undergoes variations at high frequencies, as highlighted in Figure 4b.

3. Implementation of the Optimization Algorithms

The NIA chosen to optimize the capacitance values of the three capacitors is the genetic algorithm (GA) [13,14] inspired by the principles of natural selection. The aim of this section is to briefly describe how this algorithm works and how it is interfaced with the two tools, EZpp and DF PI.

3.1. The Genetic Algorithm

The genetic algorithm is a technique allowing a population, composed by N_p so-called chromosomes (chrom), to evolve according to specific laws toward a state able to minimize a cost function. The cost function f_cost is a mathematical function whose input is each chromosome of the population and the output is generally a value used for creating a rank among the N_p chromosomes; in this work, the f_cost is defined as follows:

$$f_{cost}=N_1+\frac{N_2}{{10}^7}$$

(2)

where N₁ is the number of the frequency points (361 in the specific case) of Z_in that are larger than a specific mask, Z_mask (Figure 5), defined by the user, and N₂ is the area between the mask and Z_in. The factor 10⁷ is introduced in order to avoid that N₂ becomes predominant with respect N₁.

The target of a GA is to find a vector (chromosome) of N_g = 3 entries (genes) as,

$$chro{m}_i=\left\{C_1,C_2,C_3\right\}$$

(2)

representing the capacitance of three decaps placed around P in a fixed position according to Figure 1a.

The objective of the GA is to minimize f_cost; that is to say, to find the best member of the population, chrom_best, able to provide the smallest f_cost as possible.

The first step of the GA is the definition of the initial population, composed by N_p chromosomes, chosen by a random technique [13] from a minimum value, C_min = 10 nF, and a maximum value, C_max = 1 µF, resulting in a N_p × N_g matrix. The next step is the selection: For each chromosome, the algorithm evaluates the cost function and ranks the population from the fittest (lowest f_cost) to the unfittest (highest f_cost) electing the best ones for the next step. The number of chromosomes discarded is selected through the variable X_r: The discarded chromosomes are deleted. In the present study, X_r = 0.5, meaning that half population survives, forming the mating pool, and it will be used for the generation of the offspring replacing the discarded chromosomes. Through a “Roulette Wheel” procedure [13], a pair of chromosomes is chosen for generating a pair of offspring; this procedure, called mating, takes place until all the X_r∙N_p discarded chromosomes are replaced. The crossover point is randomly chosen between the first and the last genes of the parents’ chromosomes; in this way, each parent donates part of its genes to the resulting offspring.

The subsequent step is the mutation, whose purpose is to introduce diversity in the population randomly altering one or more genes. The number of mutations is regulated by the mutation factor µ which, in the present study, is chosen as µ = 20%.

Once the mutation is applied, the cost function of the brand-new population is evaluated again. The entire procedure, described so far, is iterated until the maximum number of generations (max_gen) is reached or the convergence is reached (f_cost = 0). The outcome is the optimum values of the three capacitances C₁, C₂, C₃.

3.2. Optimization Flow Using EZpp and DF PI

The genetic algorithm described in the previous subsection is implemented by using EZpp and DF PI as computational engines and is depicted in Figure 6a,b, respectively.

EZpp [17] is a tool, developed at the EMC Laboratory of the University of Missouri Science and Technology, based on a cavity model [15,16] able to find the S- and Z-Parameters of a PDN, once adding decoupling capacitors at any location over the board itself. All the geometrical and electrical parameters of the board, as well as the locations of input port and decaps, are stored in a text file (.ppf file).

On the other hand, DF PI by Zuken is a 3D PCB design suite which allows to draw the board, define material properties, and place components, selected from a vast library. The PI/EMI analysis tool engine implemented inside DF PI is able to provide the profile of the Z_in at the input port, as well as its spatial distribution, for specified frequencies.

The two flows in Figure 6a,b have similarities and differences. The main similarity is in their architecture: The logical position of the launching of the computational engine (EZpp or DF PI) for the evaluation of the cost function is the same to ensure a degree of uniformity in the software structure when the computational engine changes. The main difference between the two flows is how the software handles their input. Concerning EZpp, the N_p chromosomes forming the populations are written inside the N_p single.ppf files and used as input for EZpp. The resulting N_p input impedances, as .csv files, are compared with the mask for obtaining the cost function. Instead, DF PI introduces more flexibility: The entire population, composed by N_p chromosomes is written in a single .xml file which, through a batch procedure, is read by DF PI for the generation of as many input impedances.

4. Optimization of the Decoupling Capacitance Value

Figure 7a shows the result of the optimization using EZpp when the maximum number of generations is max_gen = 10 and is max_gen = 100. The resulting input impedances are very similar except at low frequency, around 2 MHz, where the Z_in from 10 generations exhibits a peak crossing the mask. As a consequence the case with max_gen = 10 is characterized by a higher f_cost, as confirmed by

Table 3. Best solution provided by EZpp for the decaps value.

maxgen	C1,opt (nF)	C2,opt (nF)	C3,opt (nF)	N1	N2/107	fcost
10	251.2	79.7	199.0	175	196	371
100	237.3	126.0	170.8	172	196	368

. The optimum value for the capacitor C₁, C_1,opt, is very similar in both cases, confirming that the closest capacitor to the input port has the highest impact on the input impedance. In the direction of identify the optimal trade-off between computational time and accuracy of the solution, one can adjust the number of the maximum generations max_gen: The higher the value of max_gen, the lower the value of f_cost; all this process is translated in an increasing of the computational time for the optimization algorithm. In the present case, max_gen = 100 introduces a slight improvement, in terms of Z_in, at low frequencies, where the capacitances have more effect.

Adopting DF PI as solver for the optimization gives a Z_in as illustrated in Figure 8a. Also in this case, there is a slight difference between max_gen = 10 and max_gen = 100, at low frequency. The main difference with respect to EZpp is an aftermath of the excess inductance discussed in Section 2. This has a huge impact on the value of f_cost, especially for N₂. A higher inductance implies a higher value of the impedance at high frequency, which means a larger value of the area between the mask and the Z_in resulting from the optimization, so explaining the higher value of f_cost, reported in

Table 4. Best solution provided by DF PI for the decaps value.

maxgen	C1,opt (nF)	C2,opt (nF)	C3,opt (nF)	N1	N2/107	fcost
10	119.2	138.8	265.5	250	668	918
100	169.7	258.2	101.2	249	667	916

, with respect the values from EZpp in Figure 7. Figure 8b testifies, once again, how an increase of the max_gen causes a decreasing of f_cost.

5. Optimization of Decaps Value and Position

The previous section is devoted to the optimization of the value of three decaps, when their position is fixed. The same algorithm used for this task can be adapted for the optimization of the three decaps value as well as their position on the board. Different from the previous scenario, now the decaps values cannot vary from a minimum value (C_min = 10 nF) and a maximum value (C_max = 1 µF) in a continuous way, but in discrete steps. Defined C_elem = 100 nF (ESR = 30 mΩ; ESL = 50 nH) as an elementary capacitance, in each of the N_pos = 3 positions the algorithm can place from N_dec,min = 1 to N_dec,max = 5 elementary capacitances in parallel. The positions on the boards are not arbitrary, but they are uniformly distributed on a grid, as depicted in Figure 9a. Additional relevant difference concerns the solver DF PI: As described in previous sections, because of the presence of 2 mm traces connecting the capacitance component to the vias, Z_in coming from DF PI exhibits higher inductance compared with the Z_in from EZpp, which does not take into account neither vias and traces. So, in the direction of carrying on a more consistent comparison between the two solvers, the 2 mm traces have been deleted and now the capacitor is directly connected with PWR and GND planes through vias (Figure 9b).

The i-th chromosome has the following form:

$$chro{m}_i=\left\{Po{s}_1,Po{s}_2,Po{s}_3,N_{dec,C1},N_{dec,C2},N_{dec,C3}\right\}$$

(3)

where Pos₁, Pos₂, Pos₃ represent three of the 52 possible grid positions and N_dec,C1, N_dec,C2, and N_dec,C3 are the number of elementary capacitors in each position.

Figure 10a and Figure 11a show the output of the optimization, for max_gen = 10 and max_gen = 100, by using as computational engines EZpp and DF PI, respectively. Both solvers are able to fulfill the condition of an input impedance under the mask, especially at low frequency where the decaps are more effective. Increasing the number of maximum generations from 10 to 100 leads to a slight improvement in terms of cost function: 427 to 429 for DF PI and 326 to 330 for EZpp, as shown by Figure 10b and Figure 11b. The insets in the same figures present the positions and the number of elementary decaps chosen by the GA. The placement resulting from EZpp sees the decaps closer to the input port with respect the position given by the optimization using DF PI. However, both solvers choose a number of decaps very close to the maximum N_dec,max = 5 and, more relevant, at least one position in the proximity of the input port P.

As mentioned, the benefit of decaps on the input impedance is more evident at low frequency so an optimization limited to f_max = 10 MHz has been carried out to better exploit the performances of EZpp and FD PI. Figure 12a and Figure 13a show the profile of Z_in obtained by the two above-mentioned computational engines.

When f_max = 1 GHz, due to the numerous resonances at high frequency, Z_in tends to more easily change its profile with the variation of number and position of the decaps and a stable cost function is reached after the 40th generation; when the optimization is limited up to f_max = 10 MHz, the convergence of the cost function is reached only after 20 generations as shown in

Table 5. Best solution provided by DF PI and EZpp for the optimization of decaps value and position, changing the maximum optimization frequency (f_max) and the maximum number of generations (max_gen).

Solver	fmax	maxgen	Ndec,C1	Ndec,C2	Ndec,C3	N1	N2/107	fcost
DF PI	1 GHz	10	5	4	5	137	292	429
		100	5	5	5	135	292	427
	10 MHz	10	5	4	5	57	11.5	68.5
		100	5	5	5	56	11.3	67.3
EZpp	1 GHz	10	5	5	5	142	188	330
		100	5	5	5	139	187	326
	10 MHz	10	5	5	5	57	2	59
		100	5	5	5	56	2	58

. In addition, now the placement emerging from the optimization is characterized by decaps closer to the input port (Figure 12b and Figure 13b). Finally, a remark on the computational efficiency. The two relevant parameters considered are the convergence (the number of generations needed to have a constant cost function) and the CPU time. In all cases considered, the maximum number of generations needed for convergence is a little less than 100 (Figure 8b) with an average of 49 over all test performed. This indicates that the implemented GA properly covers the search space. The maximum computational time for 100 generations is 109 min, including the plot and storage of the results.

6. Measurements

In order to support the results of this work (and also those related to the next steps of the project as indicated in the next section), a test vehicle of a PDN board has been designed and manufactured, whose geometry and electrical characteristics are similar to that described in Section 2 and Section 5. Figure 14 shows the top view of the manufactured board in which either the footprint of the SMA connectors (ports) and the grid of pads for the decoupling capacitors are visible (as illustrated in Figure 9a).

As a first check, the input impedance at the left bottom port P of the PDN board without capacitors (bare board) has been measured paying attention to also de-embed the mainly inductive effects of the connector. The comparison between the frequency spectrum of the magnitude of the measured input impedance and the same impedance computed by DF PI (the computational engine of the proposed optimization procedure) is shown in Figure 15.

After having run an optimization instance, the proposed algorithm generates the positions of six decoupling capacitors as indicated in Figure 16.

Figure 17 shows the comparison of the measured frequency spectrum of the magnitude of the input impedance of the PDN board with the decoupling capacitors mounted as in Figure 16 and the corresponding computed values.

From Figure 17, it appears that the proposed computational procedure is able to catch either the low-frequency (capacitive) behavior of the PDN board or its high-frequency (inductive) one. Between 100 MHz and 1 GHz, the resonant modes of the physical board are well matched with those computed. The number of measured frequency point is less than the number of computed one. This is the reason for the difference of depth between the two notches at around 5 GHz.

7. Conclusions

Decoupling capacitance is used for the reduction of transient noise in power supply network, but at the same time, a redundant number of them can lead to a considerable series of design issues. A systematic procedure for decaps quantification and placing has to be followed at different steps of the design. This work applies a nature-inspired algorithm to the definition of the decoupling capacitors on a PDN. The optimal position, the number of elementary decaps, and some figures of merit of the algorithm (such as the minimum significant number of generations) are evaluated using a GA, in cooperation with two software tools, EZpp and DF PI. Both software tools are suitable calculation engines; they are able to provide an optimal solution in a limited number of iterations with a very limited difference in their results, cross validating each other.

The computed numerical results in terms of the frequency spectrum of the input impedance are validated by means of the comparison with the measured values of the same impedance measured on a specifically designed PDN board.

The next steps of this research project target to apply the proposed procedure to the design of a real and more complex PDN considering some constraints in the cost function (such as minimum number of decaps, reliability issues, weight) and to introduce an artificial neural network (ANN), which will be able, once properly trained, to replace the use of complex software calculations engines as EZpp and DF PI, with a direct impact in the reduction of the simulation and optimization time.