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Electronics
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Design, Fabrication and Testing of Integrated Circuits and Systems
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Design, Fabrication and Testing of Integrated Circuits and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 December 2023) | Viewed by 9265

Special Issue Editors

Prof. Dr. Andrzej Jan Kos

E-Mail Website
Guest Editor
Department of Electronics, AGH University of Science and Technology, 30-059 Krakow, Poland
Interests: VLSI/ULSI design; SoC; embedded systems; micro- and nano-systems; thermal issues; high-speed computation hardware; computing acceleration; green energy; zero power systems; bioengineering; artificial intelligence; medical equipment; equipment for disabled people; reliability; sensors and education design; prefix; electric generators; thermoelectric cooling; coolers
Prof. Dr. Marcin Janicki

E-Mail Website
Guest Editor
Department of Microelectronics and Computer Science, Lodz University of Technology, 90-924 Lodz, Poland
Interests: multidomain simulation of electronic devices and systems; VLSI technology

Special Issue Information

Dear Colleagues,

Nowadays, electronics is placing increasing demands on the functionality of integrated circuits., with users expecting them to be very fast, reliable, low-energy. We are approaching our limits in terms of reducing the channel length of the transistor, forcing us to search for new qualities, technologies, and architectures.

The aim of this Special Issue is for all people involved in the design, production, and testing of integrated circuits and systems to be able to share their thoughts and experiences with this field of research. We aim to make progress in this field and to facilitate access to the latest developments for all interested parties.

Very important problems include modeling these systems, especially in relation to systems with transistors with a channel length of several nanometers, reducing static and dynamic energy losses, reliability, and universality.

We encourage you to share your achievements in designing various types of integrated circuits and systems, not only those with the highest frequency of operation or minimum power consumption, but any achievements contributing to the development of this field of science and engineering.

Thank you in advance for the articles sharing your achievements and experiences.

Prof. Dr. Andrzej Jan Kos
Prof. Dr. Marcin Janicki
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • general design of integrated circuits and systems
  • low-energy and/or high-frequency integrated systems
  • production and testing of reliable integrated devices
  • application specified integrated circuits
  • architecture of integrated devices
  • power ics for automotive applications

Published Papers (5 papers)

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Research

13 pages, 6432 KiB  
Article
A Reconfigurable Hybrid ADC Using a Jump Search Algorithm
by Sung Kwang Oh, Kwang Sub Yoon and Jonghwan Lee
Electronics 2024, 13(3), 606; https://doi.org/10.3390/electronics13030606 - 1 Feb 2024
Viewed by 571
Abstract
This paper presents a reconfigurable hybrid Analog to Digital Converter (ADC) designed specifically for bio-signal processing, aiming to achieve low power consumption and high area efficiency. The proposed ADC utilizes a combination of 10-bit Most Significant Bit (MSB) Successive Approximation Register (SAR) and [...] Read more.
This paper presents a reconfigurable hybrid Analog to Digital Converter (ADC) designed specifically for bio-signal processing, aiming to achieve low power consumption and high area efficiency. The proposed ADC utilizes a combination of 10-bit Most Significant Bit (MSB) Successive Approximation Register (SAR) and 2–4-bit Least Significant Bit (LSB) Single Slope (SS) architectures. The SS architecture incorporates the Dummy Capacitor Quantization Method (DCQM) which employs a 10-bit MSB dummy capacitor. This dummy capacitor can be configured to represent the 2-LSBs or reconstruct 4-LSBs. The reconfigurability of the ADC is achieved through the control of the reset timing of a 5-bit counter enabled by an external signal. The proposed ADC was fabricated using a Complementary Metal Oxide Semiconductor (CMOS) n-well 1-poly 8-metal process. Experimental measurements revealed that the ADC operates at a speed of 454 kS/s with power consumption of 18.7 μW. The Effective Number of Bits (ENoB) achieved by the ADC is 10.9 bits based on a 14-bit scale or 10.2 bits based on a 12-bit scale. The Figure of Merit (FoM) for the ADC is calculated to be 21.5 fJ/step for the 14-bit scale and 22.1 fJ/step for the 12-bit scale. Full article
(This article belongs to the Special Issue Design, Fabrication and Testing of Integrated Circuits and Systems)
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14 pages, 5569 KiB  
Article
Design, Fabrication, and Characterization of a PTAT Sensor Using CMOS Technology
by Michał Szermer, Mariusz Jankowski and Marcin Janicki
Electronics 2024, 13(2), 429; https://doi.org/10.3390/electronics13020429 - 19 Jan 2024
Viewed by 798
Abstract
This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage [...] Read more.
This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage was linearly proportional to the absolute temperature in a wide range of temperature values. The measurement results coincide very well with the results of the process corner analysis. Certain non-linearities occurring at high temperature values are investigated in this paper in more detail. Additionally, the influence of neighboring circuits present in the manufactured integrated circuit on the sensor temperature response is studied. Full article
(This article belongs to the Special Issue Design, Fabrication and Testing of Integrated Circuits and Systems)
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17 pages, 9184 KiB  
Article
Influence of a PCB Layout Design on the Efficiency of Heat Dissipation and Mutual Thermal Couplings between Transistors
by Krzysztof Górecki and Krzysztof Posobkiewicz
Electronics 2023, 12(19), 4116; https://doi.org/10.3390/electronics12194116 - 1 Oct 2023
Cited by 2 | Viewed by 1322
Abstract
This article presents the results of the investigations concerning the influence of the printed circuit board (PCB) layout design on self and transfer transient thermal impedances characterizing thermal phenomena occurring in the network containing two power MOSFETs. The tested devices have the case [...] Read more.
This article presents the results of the investigations concerning the influence of the printed circuit board (PCB) layout design on self and transfer transient thermal impedances characterizing thermal phenomena occurring in the network containing two power MOSFETs. The tested devices have the case D2PAK and are soldered to the PCB using the surface mount technology (SMT). The measurement method is described. The tested transistors are presented with the used PCBs on which they are mounted. The obtained measurement results of the mentioned thermal parameters of the tested transistors operating on all the tested PCBs are shown and discussed. The influence of a cooling area of the tested PCBs on the parameters describing self and transfer transient thermal impedances is analyzed. Full article
(This article belongs to the Special Issue Design, Fabrication and Testing of Integrated Circuits and Systems)
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18 pages, 5722 KiB  
Article
VES-BJT: A Lateral Bipolar Transistor on SOI with Polysilicon Emitter and Collector
by Piotr Mierzwinski and Wieslaw Kuzmicz
Electronics 2023, 12(8), 1871; https://doi.org/10.3390/electronics12081871 - 15 Apr 2023
Viewed by 1566
Abstract
This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. However, the basic VESTIC cell can be used not [...] Read more.
This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. However, the basic VESTIC cell can be used not only to make field effect transistors but also to make bipolar transistors. Their structures differ in many ways from existing structures of bipolar transistors. The investigations reported here aim to answer the question: can VESTIC-based lateral bipolar transistors be useful as active devices, and can they be made technologically compatible with field effect VESTIC devices? The theoretical studies were followed by the fabrication and measurements of VESTIC-based p-n-p and n-p-n bipolar devices. Although the manufacturing technology available was far from optimal, working bipolar devices were obtained. The results show that VESTIC-based bipolar devices may achieve acceptable parameters if made with state-of-the-art manufacturing technology. The main outcome of the research reported in the paper is that p-n-p and n-p-n bipolar transistors with acceptable parameters may be fabricated, together with field effect devices, in VESTIC-based integrated circuits. As a result, the VESTIC technology could become the new original BiCMOS technology. Full article
(This article belongs to the Special Issue Design, Fabrication and Testing of Integrated Circuits and Systems)
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18 pages, 4281 KiB  
Article
Variable Delayed Dual-Core Lockstep (VDCLS) Processor for Safety and Security Applications
by Krzysztof Marcinek and Witold A. Pleskacz
Electronics 2023, 12(2), 464; https://doi.org/10.3390/electronics12020464 - 16 Jan 2023
Cited by 5 | Viewed by 3898
Abstract
Dual-Core Lockstep (DCLS) is one of the most commonly used techniques in applications requiring functional safety. As the semiconductor process nodes keep shrinking, the DCLS technique is also more and more frequently seen in industrial or even consumer electronics. The paper presents the [...] Read more.
Dual-Core Lockstep (DCLS) is one of the most commonly used techniques in applications requiring functional safety. As the semiconductor process nodes keep shrinking, the DCLS technique is also more and more frequently seen in industrial or even consumer electronics. The paper presents the novel approach to the DCLS technique. While the typical approach is to set the slave core delay as a fixed number of clock cycles, we allow the checker core to run freely behind the main core within the constrained boundaries of clock cycles. This increases the temporal diversity needed for common mode failure mitigation. The system integrity provided by DCLS may also be used in the area of security applications. In this paper, we show that the proposed Variable Delayed Dual-Core Lockstep technique can flatten the power consumption correlation between the running cores, essential for a wide range of attacks. The proposed technique was implemented in the RISC-V processor core and verified in the Xilinx VCU108 FPGA platform. Full article
(This article belongs to the Special Issue Design, Fabrication and Testing of Integrated Circuits and Systems)
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