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3 pages, 154 KiB

Open AccessEditorial

High-Density Solid-State Memory Devices and Technologies

by Christian Monzio Compagnoni and Riichiro Shirota

Electronics 2022, 11(4), 538; https://doi.org/10.3390/electronics11040538 - 11 Feb 2022

Cited by 1 | Viewed by 1662

Abstract

The relevance of solid-state memories in the world of electronics is on the constant rise [...] Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

Research

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13 pages, 1209 KiB

Open AccessFeature PaperArticle

A Noise-Resilient Neuromorphic Digit Classifier Based on NOR Flash Memories with Pulse–Width Modulation Scheme

by Gerardo Malavena, Alessandro Sottocornola Spinelli and Christian Monzio Compagnoni

Electronics 2021, 10(22), 2784; https://doi.org/10.3390/electronics10222784 - 13 Nov 2021

Cited by 1 | Viewed by 1514

Abstract

In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when [...] Read more.

In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (

V_{T}

) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell

V_{T}

instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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11 pages, 2750 KiB

Open AccessFeature PaperArticle

A Systematic Assessment of W-Doped CoFeB Single Free Layers for Low Power STT-MRAM Applications

by Siddharth Rao, Sebastien Couet, Simon Van Beek, Shreya Kundu, Shamin Houshmand Sharifi, Nico Jossart and Gouri Sankar Kar

Electronics 2021, 10(19), 2384; https://doi.org/10.3390/electronics10192384 - 29 Sep 2021

Cited by 4 | Viewed by 2221

Abstract

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology is considered to be the most promising nonvolatile memory (NVM) solution for high-speed and low power applications. Dual MgO-based composite free layers (FL) have driven the development of STT-MRAMs over the past decade, achieving data [...] Read more.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology is considered to be the most promising nonvolatile memory (NVM) solution for high-speed and low power applications. Dual MgO-based composite free layers (FL) have driven the development of STT-MRAMs over the past decade, achieving data retention of 10 years at the cost of higher write power consumption. In addition, the need for tunnel magnetoresistance (TMR)-based read schemes limits the flexibility in materials beyond the typical CoFeB/MgO interfaces. In this study, we propose a novel spacerless FL stack comprised of CoFeB alloyed with heavy metals such as tungsten (W) which allows effective modulation of the magnet properties (M_s, H_k) while retaining compatibility with MgO layers. The addition of W results favours a delayed crystallization process, in turn enabling higher thermal budgets up to 180 min at 400 °C. The presence of tungsten reduces the total FL magnetization (M_s) but simultaneously increasing its temperature dependence, thus, enabling a dynamic write current reduction of ~15% at 2 ns pulse widths. Reliable operation is demonstrated with a WER of 1 ppm and endurance >10¹⁰ cycles. These results pave the way for alternative designs of STT-MRAMs for low power electronics. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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18 pages, 8919 KiB

Open AccessFeature PaperArticle

Assessing the Role of Program Suspend Operation in 3D NAND Flash Based Solid State Drives

by Cristian Zambelli, Lorenzo Zuolo, Antonio Aldarese, Salvatrice Scommegna, Rino Micheloni and Piero Olivo

Electronics 2021, 10(12), 1394; https://doi.org/10.3390/electronics10121394 - 10 Jun 2021

Cited by 5 | Viewed by 2716

Abstract

3D NAND Flash is the preferred storage medium for dense mass storage applications, including Solid State Drives and multimedia cards. Improving the latency of these systems is a mandatory task to narrow the gap between computing elements, such as CPUs and GPUs, and [...] Read more.

3D NAND Flash is the preferred storage medium for dense mass storage applications, including Solid State Drives and multimedia cards. Improving the latency of these systems is a mandatory task to narrow the gap between computing elements, such as CPUs and GPUs, and the storage environment. To this extent, relatively time-consuming operations in the storage media, such as data programming and data erasing, need to be prioritized and be potentially suspendable by shorter operations, like data reading, in order to improve the overall system quality of service. However, such benefits are strongly dependent on the storage characteristics and on the timing of the single operations. In this work, we investigate, through an extensive characterization, the impacts of suspending the data programming operation in a 3D NAND Flash device. System-level simulations proved that such operations must be carefully characterized before exercising them on Solid State Drives to eventually understand the performance benefits introduced and to disclose all the potential shortcomings. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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Review

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52 pages, 28425 KiB

Open AccessFeature PaperReview

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

by Takayuki Ohba, Koji Sakui, Shinji Sugatani, Hiroyuki Ryoson and Norio Chujo

Electronics 2022, 11(2), 236; https://doi.org/10.3390/electronics11020236 - 12 Jan 2022

Cited by 7 | Viewed by 8971

Abstract

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW [...] Read more.

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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16 pages, 8058 KiB

Open AccessReview

Recent Progress on 3D NAND Flash Technologies

by Akira Goda

Electronics 2021, 10(24), 3156; https://doi.org/10.3390/electronics10243156 - 18 Dec 2021

Cited by 51 | Viewed by 18933

Abstract

Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 Gb/mm² with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling [...] Read more.

Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 Gb/mm² with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling enabled the density scaling. Logical scaling has been successfully realized, too. TLC (triple-level cell, 3 bits per cell) is now the mainstream in 3D NAND, while QLC (quad-level cell, 4 bits per cell) is increasing the presence. Several attempts and partial demonstrations were made for PLC (penta-level cell, 5 bits per cell). CMOS under array (CuA) enabled the die size reduction and performance improvements. Program and erase schemes to address the technology challenges such as short-term data retention of the charge-trap cell and the large block size are being investigated. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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15 pages, 14382 KiB

Open AccessReview

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

by Yung-Yueh Chiu and Riichiro Shirota

Electronics 2021, 10(20), 2492; https://doi.org/10.3390/electronics10202492 - 13 Oct 2021

Cited by 4 | Viewed by 2888

Abstract

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D [...] Read more.

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (

Δ G_{m, m a x}

) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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24 pages, 14833 KiB

Open AccessFeature PaperReview

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

by Akinobu Teramoto

Electronics 2021, 10(15), 1759; https://doi.org/10.3390/electronics10151759 - 22 Jul 2021

Cited by 8 | Viewed by 3863

Abstract

Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories [...] Read more.

Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor field-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current flows at the interface of different materials, such as SiO₂/Si. Variability of low-frequency noise increases with MOSFET shrinkage. To assess the effect of this noise on MOSFETs, we must first understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period. This study compares statistical evaluation methods of low-frequency noise to the trend of conventional evaluation methods, and this study’s findings are presented. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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21 pages, 7532 KiB

Open AccessReview

by Hiroshi Watanabe and Hsin-Jyun Lin

Electronics 2021, 10(11), 1287; https://doi.org/10.3390/electronics10111287 - 28 May 2021

Cited by 1 | Viewed by 2171

Abstract

A basic mechanism for storing data in memory cells is to record changes in electronic charges, material phases, resistivities, magnetic properties, and so forth. The change in electronic charge has been widely used in the majority of mass-produced memories, such as dynamic random-access [...] Read more.

A basic mechanism for storing data in memory cells is to record changes in electronic charges, material phases, resistivities, magnetic properties, and so forth. The change in electronic charge has been widely used in the majority of mass-produced memories, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), NOR Flash, and NAND Flash. Other emerging memories have collected widespread attention for acquiring extra advantages which cannot be achieved using the change in electronic charge. Many years of studies have told us that reliability problems are critically important in the development of both conventional and emerging memories, in order to improve the product yield. However, the topics related to these problems are too wide to cover in these limited pages. In this review chapter, we address several interesting examples of trap-related problems in dielectrics for use in various memory cells. For engineering purposes, it is very important to grasp the relation of the achieved physical intuitions and electronic characteristics of dielectrics. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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22 pages, 3362 KiB

Open AccessFeature PaperReview

In-Memory Computing with Resistive Memory Circuits: Status and Outlook

by Giacomo Pedretti and Daniele Ielmini

Electronics 2021, 10(9), 1063; https://doi.org/10.3390/electronics10091063 - 30 Apr 2021

Cited by 37 | Viewed by 7772

Abstract

In-memory computing (IMC) refers to non-von Neumann architectures where data are processed in situ within the memory by taking advantage of physical laws. Among the memory devices that have been considered for IMC, the resistive switching memory (RRAM), also known as memristor, is [...] Read more.

In-memory computing (IMC) refers to non-von Neumann architectures where data are processed in situ within the memory by taking advantage of physical laws. Among the memory devices that have been considered for IMC, the resistive switching memory (RRAM), also known as memristor, is one of the most promising technologies due to its relatively easy integration and scaling. RRAM devices have been explored for both memory and IMC applications, such as neural network accelerators and neuromorphic processors. This work presents the status and outlook on the RRAM for analog computing, where the precision of the encoded coefficients, such as the synaptic weights of a neural network, is one of the key requirements. We show the experimental study of the cycle-to-cycle variation of set and reset processes for HfO

_{2}

-based RRAM, which indicate that gate-controlled pulses present the least variation in conductance. Assuming a constant variation of conductance

σ_{G}

, we then evaluate and compare various mapping schemes, including multilevel, binary, unary, redundant and slicing techniques. We present analytical formulas for the standard deviation of the conductance and the maximum number of bits that still satisfies a given maximum error. Finally, we discuss RRAM performance for various analog computing tasks compared to other computational memory devices. RRAM appears as one of the most promising devices in terms of scaling, accuracy and low-current operation. Full article

(This article belongs to the Special Issue High-Density Solid-State Memory Devices and Technologies)

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