Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsStrengths: Thoroughness and Profundity: The study stands out for its thorough coverage and profound analysis, examining several TDC technologies and comparing them using important performance indicators. This is consistent with the advantages of genetic algorithms in generating a wide range of useful solutions by thoroughly exploring potential spaces.
Comprehensive Evaluation: We thoroughly examine each TDC technique in terms of accuracy, precision, non-linearities, and resource efficiency, similar to how artificial intelligence systems assess performance based on multiple criteria and aim to optimise them.
Weaknesses and Recommendations for Improvement: Practical Applications The research fails to offer specific examples of how these technologies could effectively function in real-life scenarios. Genetic algorithms can address this deficiency by providing concrete examples of how they can enhance TDC designs in real-world scenarios.
Future Trends: There is limited discussion about upcoming innovations. Genetic algorithms, a subset of artificial intelligence, have the potential to offer useful insights into the integration of FPGA technologies with AI, therefore propelling progress in the field.
Metric Comparison Accuracy and Efficiency: The study provides comprehensive metrics for assessing resource precision and utilization. Genetic algorithms have the potential to improve these metrics by optimizing user interfaces and tailoring solutions to specific needs.
The study examines several technologies but fails to investigate their ability to successfully adapt to dynamic contexts. Genetic algorithms, renowned for their capacity to adapt to changing circumstances, serve as an illustration of how to attain this level of flexibility.
Author Response
Thank you very much for your valuable comment.
Please see the attached file.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for Authors
The manuscript by Real and Calvo entitled „Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review,” presents an overview of low-resource TDC designs. Although there are number of review papers about different time-to-digital conversion methods, the reviewed manuscript has advantages of been strictly related to FPGA-based low-resource designs mainly based on additional dedicated functional blocks. While I have found the paper interesting there are number of errors that need to be corrected. Also the topic described does not fully fit to the scope of the Sensors journal.
1. (Major) Please explain why the topic of your article fit the scope of the selected journal. Note that TDCs are not essentially sensors.
2. (Minor) line 18, what does it mean “Voltage-Temperature-Consumption (!) stable”?
3. (Minor) line 18, “IODELAYS” – “IODELAYs”.
4. (Minor) line 46, is there and difference between “Nutt” and “interpolation” architectures? This is what I can understand if “or” is put in between.
5. (Major) lines 49-50, I don’t agree that GCO TDC is one of the most used low-resource interpolation methods, this is rather new approach, not much popular (I know just a few paper describing it). Also interpolation methods combines GCO or MPSC (or any other methods) with a coarse measurement. In this sense, I would not say that GCO or MPSC are “interpolation methods”. This should be rewritten.
6. (Major) lines 81-82, what "number of pulses per bin” do you mean? This is unclear.
7. (Major) Eq. (2), lines 87-88, can you provide any reference or this equation? What does it mean “input witdh”? Why DNL is calculated using “number of pulses” but the corresponding INL is based on “input width” or average “pulse width”?
8. (Minor) line 94, “calibration” is not a parameter. Note that in Section 2 you indicate TDC “parameters”.
9. (Minor) line 107, what does it mean “can be extended as needed”? Are you sure there are no restrictions here?
10. (Minor) line 114, same as in remark 4.
11. (Minor) line 121, “TDL and VRO have achieved considerable reduction in the use of resources” – is this what you mean? Has the implementation of the TDL method reduced resources in recent years? I think that while the resolution of such converters has improved, the resource consumption is still rather high.
12. (Minor) line 125, “TLD”-“TDL”.
13. (Major) lines 127-128, “while the precision is determined by the uniformity of the delay tap” - this is just one of the factors.
14. (Major) line 133, where in [37] can I find information about TDL composed of LUTs?
15. (Major) lines 136-137, in [39] the resolution (as defined in your paper) is (1/350MHz)/172=16.6 ps, while the “time resolution” is 14 ps. Both values doesn’t fit to your statement (“<10 ps resolution”).
16. (Minor) line 144, Xilinx defines CLB as a Configurable Logic Block, is this what you mean?
17. (Minor) line 148, typically manual placement is more important than routing for high performance FPGA TDC.
18. (Minor) lines 151-153, parallel delay lines can nowadays achieve 1 ps resolution or even better. As a remedy for high logic resource utilization one can use some variants of the wave union method or combine parallel lines with wave union. I think this can be shortly commented in your paper.
19. (Minor) lines 157-162, in [44, 45] the authors optimized the data encoder but the TDL TDC is implemented in a typical way. To lower resource consumption one can use LUTs as delay elements or omit some TDL taps as in [65], but does it really have sense? TDL TDCs are used to get high resolution, for low resource consumption there are other methods that are often also PVT-resistant and calibration-free.
20. (Minor) line 155, form the user point of view the IODELAY is a programmable delay line, not a tapped delay line (it is not possible to simultaneously use different taps of IODELAY).
21. (Major) line 186, I wonder why Noise-Shaping TDC is included in this review? So far, there are just a few papers about implementation of this method in FPGA, and it consumes a lot of logic resources. So in my opinion this doesn’t fit to the main scope of the paper.
22. (Minor) line 226, there are some tricks to improve signal skew to FFs. With some manual placement and routing it is possible to improve it below MPSC resolution.
23. (Minor) line 233, “Yonggang” – “Wang” (correct also in [57]).
24. (Major) lines 246-250, actually, in [65] the authors didn’t manage to properly implement MPSC TDC (they were able to use 2 phases only). The results that you refer to are about the so called single-phase shift clock TDC, which is in fact a TDL TDC where only selected taps are in use. Overall, many information included in this paper about MPSC are misleading.
25. (Major) Table 1:
a. this table is referenced just at the beginning of the paper (page 2) but appears on page 8;
b. The caption of this table must be changed (it doesn’t only compare resource utilization, resource utilization or consumption is repeated 3 times);
c. Ref. [65] should be classified in TDL TDC.
d. How is it possible that MPSC TDCs didn’t need any PLLs?
e. I have found a paper Szplet et al. “Precise Time Digitizer Based on Counting Method and Multiphase In-Period Interpolation” EFTF/IFC 2019, where MPSC TDC achieved 43 ps resolution and precision below 36 ps. I think you can consider this paper in the table.
26. (Minor) line 276, “ARTIX-7”-“Artix-7”
27. (Major) line 283, something here doesn’t look correct to me, from the basic quantization theory it is not possible to get 56 ps precision while resolution is only 321 ps. Also I couldn’t file this “56 ps” value in [7].
28. (Minor) line 284, “Imrem et al.” – “Imrek et al. [6]”.
29. (Minor) line 292, “the granular delay provided by Xilinx” this should be rewritten, the granular delay is provided by IODELAY element.
30. Section 9, the multistage interpolation were described in many papers. While other methods are rather well referenced, this section is poor. The oldest paper that comes to my mind is Szymanowski and Kalisz “Field programmable gate array time counter with two-stage interpolation“, Review of Scientific Instruments, 2005. I suggest to improve this section to make more thorough analysis of multistage interpolation TDCs. Also pros and cons of this method should be analyzed.
31. (Minor) line 300, “two interpolation methods” – “two-step/stage interpolation”.
32. (Major) line 305, the idea of combining MPSC with IODELAY was in fact noted in [7] (see the end of Section II.B). The 321 ps resolution TDC was shown as a proof of concept but it was written that up to 75 ps resolution is achievable (in an old Virtex-5). With this regard, I do not see a point to include [73] where the same idea is presented with worse resolution (416 ps).
33. (Major) Table 2, I do not understand how IODELAY can be used as a “tapped” delay line? As for me it is just programmable delay line. I suggest to remove the term “TDL” next to IODELAY. The table is unnecessarily so large, and it is unclear why so much empty space was left on page 10.
34. (Minor) lines 325-326, the GCO TDCs have in fact similar resolution and precision as th]MPSC TDCs. Better parameters were achieved in [55] due to the use of 2-stage interpolation, i.e. sampling each GCO output by 8 DFFs.
35. (Major) line 332, the IODELAY are indeed interesting due to the fact that it is PVT-resistant bur as I have already noted – this is not a tapped delay line from the user point of view. We cannot replace a classic TDL with the IODELAY.
Comments on the Quality of English Language
The manuscript is rather correctly written from the linguistic point of view, it needs only minor corrections.
Author Response
Thank you for your valuable feedback. Please find the attached file.
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsThis work briefly introduced the TDC main parameters and evaluated the low-resource TDCs methods, offering a comprehensively overview. Therefore recommended for publication.
Author Response
Thank you very much for your valuable comments.
