Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review
Abstract
:1. Introduction
2. TDC Main Parameters
- Resolution refers to the smallest detectable time interval or the smallest distinguishable step-in-time measurement that the TDC can achieve. The smallest resolvable time interval is represented by the Least Significant Bit (LSB), which establishes the resolution of the TDC.
- Dead-time refers to the minimum time interval required between two consecutive events or pulses for accurate detection and measurement. It is the period during which the TDC is temporarily unable to respond to incoming signals due to internal processing, resetting, or recovery time. Dead-time is an inherent characteristic of TDCs and is primarily caused by the time required for data acquisition, signal conditioning, digitization, and internal circuitry operations.
- Precision refers to the repeatability and consistency of time measurements performed by the TDC. It is directly affected by the non-linearities of the TDC.
- Differential non-linearities (DNLs) can be defined as the deviation of a single quantization step from the ideal LSB. They quantify the step size variation between consecutive output codes. DNL is typically expressed as the difference between the measured step size and the ideal step size (in LSB). The DNL is evaluated by comparing the number of pulses per LSB bin () with the mean value ():
- Integral non-linearities (INLs) describe the greatest deviation in the transfer function of a TDC from the ideal linear relationship. The INL value provides information about the linearity and precision of the TDC’s measurements. It can be determined by performing the following calculation [18]:
- Range refers to the time intervals that the TDC is capable of accurately measuring. It represents the minimum and maximum values that the TDC can handle within its specified operating conditions.
- Clock Frequency refers to the frequency at which the TDC’s internal clock operates, influencing the resolution and measurement capabilities.
- Calibration parameters: some TDCs, in order to compensate for non-linearities and enhance accuracy, require a calibration process. Usually, the calibration system increases the use of resources.
- Resource occupancy concerns the utilization of FPGA resources, such as lookup tables (LUTs), flip-flops (FFs), memory blocks, interconnects, or other FPGA hardware, such as SerDes or IOs delays, to implement the TDC functionality. The present review is dedicated to TDCs which are implemented with low resource use.
3. The Basics: The Counter and the Interpolator
4. Tapped Delay Line TDCs
Expanding Precision and Resolution beyond the Delay Cell
5. Vernier Ring Oscillator TDCs
6. Noise-Shaping TDCs
7. Gray Code Oscillator TDCs
8. Multi-Phase Shift Clock TDCs
8.1. SerDes TDC
8.1.1. One-SerDes TDCs
8.1.2. Two-SerDes TDCs
8.1.3. Four-SerDes TDCs
9. Two-Stage Interpolation TDCs
10. Discussion
11. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
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Work | Res. (ps) | Pre. (ps) | DNL/INL(LSB) | LUTs | FFs | Primitive | BRAM (kB) | FPGA |
---|---|---|---|---|---|---|---|---|
NS | ||||||||
Kha-21 [59] | 0.18 | NR | NR/NR | NR | 311 | 5 PLL | 2000 | Stratix-IV |
TDL | ||||||||
Choi-21 [39] | 4.88 | 8.03 | 0.51/0.51 | 2962 | 4157 | 0 | 0 | Artix-7 |
Pars-21 [49] | 22.2 | 26.04 | 2.13/3.97 | 216 | 678 | 0 | 90 | Artix-7 |
Pars-22 [50] | 22.1 | 22.35 | 1.18/2.75 | 216 | 678 | 0 | 90 | Artix-7 |
Lusa-23 [78] | 156.25 | 93 | 0.23/0.26 | 295 | 446 | 0 | 0 | Artix-7 |
Lusa-23 [78] | 312.5 | 93 | 0.26/0.2 | 238 | 431 | 0 | 0 | Artix-7 |
Lusa-23 [78] | 625 | 255.5 | 0.045/0.045 | 212 | 336 | 0 | 0 | Artix-7 |
VRO | ||||||||
Cui-17 [56] | [23, 37] | [32, 39] | 0.8/1.7 | 104 | 319 | 0 | 0 | Virtex-6 |
Cui-20 [57] | 24.5 | 28 | 0.45/0.85 | 172 | 986 | 0 | 0 | Virtex-6 |
GCO | ||||||||
Wu-19 [22] | 256 | 160 | 1.25/NR | NR | NR | 0 | NR | Kintex-7 |
Mach-20 [60] | 380.9 | 290 | 0.76/0.71 | NR | NR | 0 | NR | Virtex-7 |
Arau-21 [12] | 69 | 54.99 | 1.76/1.5 | NR | NR | 0 | NR | Ultrascale+ |
Wang-23 [61] | 20.97 | 17.11 | 0.087/0.224 | 455 | 368 | 0 | 54 | Ultrascale+ |
Wang-23 [61] | 36.01 | 27.37 | 0.102/0.262 | 453 | 367 | 0 | 54 | Ultrascale |
Wang-23 [61] | 34.84 | 32.33 | 0.078/0.203 | 437 | 368 | 0 | 54 | Virtex-7 |
Wang-23 [61] | 256.41 | N/R | 0.65/3.1 | 380 | 333 | 0 | 54 | Virtex-7 |
MPSC | ||||||||
Frie-02 [62] | 1400 | 750 | 0.4/NR | NR | NR | 0 | 0 | Virtex-5 |
Buch-12 [64] | 160 | 64 | 0.4/NR | 125 | 198 | 0 | 0 | Virtex-5 |
Wang-13 [63] | 138 | NR | 0.29/NR | NR | NR | 0 | 0 | Virtex-5 |
Ball-14 [16] | 625 | 255 | 0.05/0.05 | 68 | 274 | 0 | 0 | Virtex-5 |
Suwa-15 [65] | 1000 | 500 | 0.52/0.39 | NR | NR | 0 | 0 | Spartan-6 |
Sano-16 [67] | 280 | NR | 0.28/0.3 | NR | NR | 0 | 0 | Kintex-7 |
Sano-17 [68] | 780 | 350 | 0.53/2.8 | NR | NR | 0 | 0 | IGLOO-2 |
Li-17 [66] | 1000 | 430 | NR/NR | NR | NR | 0 | 0 | Spartan-6 |
Jia-18 [69] | 138 | 73.6 | NR/NR | NR | NR | 0 | 0 | Artix-7 |
Szplet-19 [79] | 43 | 36 | 1.91/NR | NR | NR | 0 | 0 | Kintex-7 |
MPSC SerDes | ||||||||
Bogd-05 [70] | 1200 | 1200 | 0.17/NR | NR | NR | 1 SER | 0 | Stratix |
Calv-21 [18] | 1000 | NR | 0.03/0.12 | NR | NR | 1 SER | 0 | Kintex-7 |
Kong-23 [71] | 100 | 169 | NR/NR | NR | NR | 1 SER | 0 | Kintex-7 |
Xian-14 [72] | 156 | 56 | 0.32/1 | 109 | 238 | 2 SER | 0 | Artix-7 |
Bai-17 [73] | 803 | 229 | 0.05/NR | 30 | 42 | 2 SER 1 IOD | 0 | Artix-7 |
Arpi-10 [7] | 321.5 | NR | 0.3/0.65 | NR | NR | 4 SER 4 IOD | 0 | Virtex-4 |
Imre-10 [6] | 312 | NR | 0.6/NR | NR | NR | 4 SER 4 IOD | 0 | Virtex-4 |
Fino-24 [74] | 100 | 42 | 0.35/NR | NR | NR | 4 SER 3 IOD | 0 | Artix-7 |
Two-stage | ||||||||
Dong-20 [75] | 78.13 | 35 | 0.8/0.94 | 199 | 347 | 1 SER 1 IOD | 0 | Kintex-7 |
Wang-24 [77] | 10.05 | 19.81 | 2.85/13.61 | 293 | 385 | 0 | 0 | Virtex-7 |
Wang-24 [77] | 4.57 | 22.88 | 4.36/18.26 | 440 | 570 | 0 | 0 | Ultrascale |
Real-24 [76] | 415.84 | 186 | 0.2/0.15 | 102 | 115 | 1 IOD | 0 | Artix-7 |
Type | Advantages | Drawbacks |
---|---|---|
TDL | High-resolution | Calibration |
PVT | ||
Resource consumption | ||
TDL:IODELAY | Resource-efficient | Moderate resolution |
PVT-compensated | Limited number | |
Delay granularity | ||
VRO | High-resolution | Resource consumption |
slightly linear | ||
high dead-time | ||
GCO | Resource-efficient | Calibration |
PVT | ||
MPSC | Resource-efficient | Moderate resolution |
Highly linear | ||
MPSC:SerDes | Resource-efficient | Moderate resolution |
Highly linear | Limited number |
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Real, D.; Calvo, D. Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review. Sensors 2024, 24, 5512. https://doi.org/10.3390/s24175512
Real D, Calvo D. Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review. Sensors. 2024; 24(17):5512. https://doi.org/10.3390/s24175512
Chicago/Turabian StyleReal, Diego, and David Calvo. 2024. "Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review" Sensors 24, no. 17: 5512. https://doi.org/10.3390/s24175512