Next Article in Journal
Bicycle Traffic Model for Sustainable Urban Mobility Planning
Previous Article in Journal
Exploring the Exhaust Emission and Efficiency of Algal Biodiesel Powered Compression Ignition Engine: Application of Box–Behnken and Desirability Based Multi-Objective Response Surface Methodology
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

Analysis of Allowable Unbalanced Load Conditions for T-Type Three-Level PWM Converter

Department of Electrical Engineering, Korea National University of Transportation, Chungju 27469, Korea
Energies 2021, 14(18), 5969; https://doi.org/10.3390/en14185969
Submission received: 1 September 2021 / Revised: 16 September 2021 / Accepted: 17 September 2021 / Published: 20 September 2021

Abstract

:
Since a T-type three-level PWM converter has several advantages in terms of harmonics and conduction loss, it has been widely adopted for various low voltage applications. However, a neutral point voltage control is necessarily required for stable system operation, and an offset voltage can effectively provide the required neutral point current under unbalanced load conditions. Nevertheless, all types of unbalanced loads cannot be accommodated; in other words, there is a limitation on how much unbalanced load conditions can be allowed. Therefore, this paper analyzed the maximum allowable unbalanced load conditions in the T-type three-level PWM converter. This result can be properly utilized for an effective design verification considering unbalanced load conditions as well as a comprehensive approach for the stable system operation. The feasibility of the analytical result is verified through simulation and experimental tests.

1. Introduction

The T-type three-level PWM converter has a merit in terms of harmonic reduction by generating a multi-level output voltage waveform compared to the traditional 2-level PWM converter. Also, it can reduce conduction loss compared to a similar NPC three-level PWM converter, so it is widely considered as a candidate in low voltage applications [1,2]. Therefore, many studies are being conducted to utilize the T-type three-level PWM converter in various applications [2,3,4,5,6,7].
However, in the T-type three-level PWM converter, neutral point voltage control is essential for stable operation, and it carries out various neutral point voltage control between the upper and lower DC-link voltages depending on the application field [3,8]. To accomplish this purpose, an offset voltage is normally used, and the resultant neutral point current is inserted to the output DC-link side.
In a balanced load condition, the offset voltage is not necessary because the required neutral point current is zero. On the other hand, in an unbalanced load condition, an enough offset voltage should be provided to generate the required neutral point current value. Since this offset voltage does not affect the whole DC-link voltage and three-phase sinusoidal input current, only upper and lower DC-link voltages control can be effectively performed. However, the amount of offset voltage that can be applied is limited and varies depending on the given system specification. This implies that the balance control of the upper and lower DC-link voltages may not be achieved according to the unbalanced load condition, and means that the maximum allowable unbalanced load condition exists in the T-type three-level PWM converter.
Therefore, in this paper, based on the analytical modeling derived for the neutral point current in the T-type three-level PWM converter [9], the maximum allowable unbalanced load condition for the balance control between the upper and lower DC-link voltages is theoretically analyzed. Through this, it is possible to verify in advance how much the unbalanced load condition can be accommodated for the stable operation in the T-type three-level PWM converter system. To analyze this condition, a space vector PWM-based T-type three-level PWM converter operation was assumed, and simulations and experimental tests were conducted to verify its effectiveness.

2. Average Neutral Point Current

2.1. Circuit Configuration

Figure 1 shows a grid-connected power conversion system based on the T-type three-level PWM converter using an L filter. The converter was assumed to be operated as a rectifier mode; in other words, the total power flows from the AC input to the DC output.
The output loads are replaced by two current sources (iH and iL), and when independent loads are connected to the upper and lower ends of the output DC voltage as shown in Figure 1, the fluctuation of the neutral point voltage due to load difference is inevitable. Thus, the effective neutral point voltage control method is required.
Figure 2 shows the phasor diagram for the T-type three-level PWM converter operation in the steady state. Based on the grid voltage (Vg), it is assumed that the input grid current (Ig) flows with a delay of Φ1. Considering the voltage drop of the inductor (L) filter including the equivalent series resistor (R), the output voltage (Vo) of the converter is applied with a delay of Φ2 compared to the input current (Ig). In general, in the case of a grid-connected power conversion system, Φ1 is controlled to be zero in order to maximize active power, but in this paper, a condition in which Φ1 is not zero is assumed to consider a more general case.

2.2. Neutral Point Current Modeling

To maintain the upper and lower DC-link voltages equivalently under unbalanced load conditions, the neutral point current (io) should be controlled relevantly. To obtain the amount of required neutral point current (io) in the given system specification, the analytical modeling has been performed.
For convenience of analysis, it is assumed that each DC-link voltage is well regulated equivalently (vH = vL = 0.5 × vDC), and also the three-phase sinusoidal grid voltages and currents are assumed to be in balanced states. Meanwhile, it is assumed that an unbalanced load is applied to each DC-link voltage in order to consider the situation in which the neutral point current is required. Figure 3 shows the main waveforms in the steady state, and the related equations are as follows.
v g a v g b v g c = V g cos ω t cos ω t 2 π / 3 cos ω t + 2 π / 3
i g a i g b i g c = I g cos ω t ϕ 1 cos ω t 2 π / 3 ϕ 1 cos ω t + 2 π / 3 ϕ 1
d a d b d c = m cos ω t ϕ 1 ϕ 2 cos ω t 2 π / 3 ϕ 1 ϕ 2 cos ω t + 2 π / 3 ϕ 1 ϕ 2
Here, the three-phase grid voltages (vga, vgb, and vgc) and currents (iga, igb, and igc) have a phase delay of Φ1 where Vg and Ig are the maximum value. Also, the three-phase duties (da, db, and dc) have an additional phase delay of Φ2 where m is the modulation index.
The relationship between the output voltage of the converter and the duty is as follows:
v o a v o b v o c = V D C 2 d a d b d c
Using the above equations, the modulation index (m) can be obtained as (5).
m = V g I g cos θ 1 2 + I g Z s i n θ 1 2 0.5 V D C
Here, Z is the magnitude of the impedance corresponding to the inductor (L) filter including the equivalent series resistor (R), and θ is the phase angle of the impedance.
Z = R 2 + ω L 2 θ = t a n 1 ω L R
The three-phase duties are converted to the final duties (doa, dob, and doc) as shown in the lowest waveform of Figure 3 through the space vector PWM technique [10] and the addition of offset voltage for neutral point current control.
d o a d o b d o c = d a d b d c + 1 1 1 1 1 1 d s v d o s
Here, the dsv is the duty to implement the space vector PWM technique and is given by (8), and the dos is the offset duty corresponding to the offset voltage.
d s v = 0.5 V D C V max + V min
The phase difference of Δθ in Figure 3 comes from the offset voltage and is expressed as follows.
Δ θ = π 2 cos 1 2 3 d o s m
Thus, the neutral point current can be obtained for each of the six areas (I~VI) in Figure 3, and the average value during one period of the grid voltage is calculated as follows [9].
i o , a v g = 6 d o s I g cos Δ θ cos ϕ 2 π + m I g 2 π 9 2 sin 2 Δ θ cos ϕ 2 9 Δ θ cos ϕ 2
If assuming the balanced load condition (Δθ = 0), the average neutral point current can be approximated as (11).
i o , a v g 6 d o s I g cos ϕ 2 π
Through this, it can be seen that the magnitude of the approximated average neutral point current is proportional to the maximum value of the grid current and the offset duty, and is related to Φ2 corresponding to the phase delay between the grid current and the output voltage of the converter.

3. Allowable Unbalanced Load Conditions

Based on the analytical result for the neutral point current, in order to analyze the allowable unbalanced load condition in the T-type three-level PWM converter, the equivalent circuit for the converter’s output side was used as shown in Figure 4.
Through the balanced three-phase values, the following equation is satisfied.
i p + i o + i n = 0
Here, the ip and in are the positive and negative side instantaneous output current, respectively.
In steady state, the average current flowing through the capacitor becomes zero, so the neutral point current can be expressed as follows.
I o = I n I p = I L I H
Here, the capital letters mean the average value of each current shown in Figure 4.
From (11) and (13), the required offset duty in the system is expressed as follows.
d o s I L I H π 6 I g cos ϕ 2
From (14), it can be known that the offset duty is not required under a balanced load condition (IL = IH), while some offset duty is required under unbalanced load conditions (ILIH).
However, the required offset duty should be smaller than the maximum possible offset duty that is allowable in the system, and it is given by (15) under the space vector PWM based operation.
d o s d o s _ m a x = 1 3 2 m
Here, the modulation index (m) is calculated from (5) through the system specification.
In other words, the maximum possible offset duty (dos_max) in (15) is a value determined by the converter’s topology and operational point, which means any unbalanced loads can be controlled by applying the required offset duty without changing the hardware if the condition of (15) is satisfied. However, in case of out of that condition, it can be solved through additional circuit configuration such as voltage balancer [11,12,13,14].
Figure 5 shows the maximum possible offset duty (dos_max) and the actually required offset duty (dos) under unbalanced load conditions based on the system specifications in Table 1. The grid current (Ig) in (14) can be calculated by using the output power (Po) and the grid line-to-line voltage (Vg,ll) given in Table 1.
d o s I L I H π V g , l l · cos ϕ 1 2 6 P o · cos ϕ 2
While the upper load was fixed at 100%, the change in duty was monitored by gradually decreasing the lower load as shown in Figure 5 where ΔP(%) corresponding to the horizontal axis is expressed as (17).
Δ P % = I H I L I H × 100
It can be seen that the required offset duty (dos) increases as the difference in each output power increases. Until the required offset duty (dos) is smaller than the maximum possible offset duty (dos_max), the balance control of each DC-link voltage is well performed even under unbalanced load conditions. However, when the difference in output power becomes greater than about 43%, the required offset duty (dos) exceeds the maximum possible offset duty (dos_max) so that balanced output voltage control cannot be maintained anymore. This allows determination of the maximum allowable unbalanced load conditions for a given system.

4. Simulation and Experimental Results

Simulations were performed through PSIM to verify the analyzed allowable unbalanced load conditions. Table 1 shows the system specifications and parameter values used in the simulation.
Figure 6 shows the operational waveforms under a balanced load condition. Each 100% load was applied to both upper and lower DC-link voltages, and the three-phase sinusoidal grid voltages and currents were controlled to be in phase. Since the real neutral point current (io) is a pulsating waveform due to the PWM operation, the averaged neutral point current (io_Ts) at every sampling period was measured. As expected, the average neutral point current value during one grid period was zero due to the balanced load condition. Also, it can be seen that the upper and lower DC-link voltages (vH and vL) maintained a balanced state. As well, no offset duty was applied to the final duty (doa), in other words, the final duty (doa) was symmetrical based on 0.5.
Figure 7 shows the operational waveforms under unbalanced load conditions. In both cases, 100% load was applied to the upper DC-link, and the load connected to the lower DC-link was reduced. Figure 7a is a condition where the output power deviation (ΔP) corresponds to 40%. Thus, the offset duty was included in the final duty (doa), and it can be seen that the final duty was shifted to the upper side as a whole. Nevertheless, as expected in Figure 5, it corresponds to the condition that the balance control can be performed, and the upper and lower DC-link voltages maintain a balanced state. However, Figure 7b is a condition where the output power deviation (ΔP) corresponds to 45%, and the final duty (doa) is caught at the upper limit, so the relevant balance control cannot be performed. This is also consistent with what is expected in Figure 5, and the upper and lower DC-link voltages show an unbalanced state.
Figure 8 shows the photograph for the experimental test.
Figure 9 shows the experimental waveforms under a balanced load condition. Each 100% load was applied to both the upper and lower DC-links, and the unit power factor control was satisfied by controlling the phases between the grid line-to-line voltage (vgab) and grid phase current (iga) to be π/6. Also, the neutral point current (io) was an averaged waveform at every sampling period, and it can be seen that the average value was zero due to the balanced load condition. Also, the upper and lower DC-link voltages (vH and vL) were balanced, and the final duty (doa) was symmetrical with respect to 0.5.
Figure 10 and Figure 11 show the experimental waveforms under unbalanced load conditions. First, Figure 10 shows the waveforms corresponding to 100% load at the upper DC-link and 60% load at the lower DC-link, which is a condition where the output power deviation (ΔP) corresponds to 40%. Due to the total load reduction, the peak value of the grid current (iga) was decreased compared to Figure 9, and the average value of the neutral point current (io) was also decreased to about −3.2 A because of the unbalanced load. Nevertheless, the offset duty was applied to the final duty (doa), and thus the duty was shifted upward as a whole. Thus, as expected in Figure 5, each DC-link voltage maintained a balanced state.
Figure 11 shows the waveforms corresponding to 100% load at the upper DC-link and 55% load at the lower DC-link, which is a condition where the output power deviation (ΔP) corresponds to 45%. The final duty (doa) was caught at the upper limit, and the relevant balance control was not achieved, which is consistent with what is expected in Figure 5. Therefore, it was confirmed that the upper and lower DC-link voltages are not regulated equivalently.
Thus, the analysis for the allowable unbalanced load condition in the T-type three-level PWM converter was verified through the simulation and experimental results.

5. Conclusions

In this paper, the maximum allowable unbalanced load condition in the T-type three-level PWM converter was analyzed by using the theoretical modelling for the neutral point current under the space vector PWM based operation. Based on the given system parameters, it can determine the required offset duty under an unbalanced load condition. By comparing the required offset duty with the maximum possible offset duty, it can be judged whether the system operation will be stable or not. Through this, at the design level of the system, it can be analytically confirmed how much unbalanced load can be allowed in the T-type three-level PWM converter system. The validity of the theoretical analysis proposed in this paper was verified by simulation and experimental results.

Funding

This was supported by Korea National University of Transportation in 2021.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Conflicts of Interest

The author declares no conflict of interest.

References

  1. Nabae, A.; Takahashi, I.; Akagi, H. A new neutral-point-clamped PWM inverter. IEEE Trans. Ind. Appl. 1981, IA-17, 518–523. [Google Scholar] [CrossRef]
  2. Schweizer, M.; Kolar, J.W. Design and implementation of a highly efficient three-level T-type converter for low-voltage applications. IEEE Trans. Power Electron. 2013, 28, 899–907. [Google Scholar] [CrossRef]
  3. Park, Y.; Sul, S.-K.; Lim, C.-H.; Kim, W.-C.; Lee, S.-H. Asymmetric control of dc-link voltages for separate MPPTs in three-level inverters. IEEE Trans. Power Electron. 2013, 28, 2760–2769. [Google Scholar] [CrossRef]
  4. Alemi, P.; Jeung, Y.-C.; Lee, D.-C. DC-link capacitance minimization in T-type three-level AC/DC/AC PWM converters. IEEE Trans. Power Electron. 2015, 62, 1382–1391. [Google Scholar] [CrossRef]
  5. Lee, J.-S.; Lee, K.-B. New modulation techniques for a leakage current reduction and a neutral-point voltage balance in transformerless photovoltaic systems using a three-level inverter. IEEE Trans. Power Electron. 2014, 29, 1720–1732. [Google Scholar] [CrossRef]
  6. Shao, Z.; Zhang, X.; Wang, F.; Cao, R. Modeling and elimination of zero-sequence circulating currents in parallel three-level T-type grid-connected inverters. IEEE Trans. Power Electron. 2015, 30, 1050–1063. [Google Scholar] [CrossRef]
  7. Anthon, A.; Zhang, Z.; Andersen MA, E.; Holmes, D.G.; McGrath, B.; Teixeira, C.A. The benefits of SiC MOSFETS in a T-type inverter for grid-tie applications. IEEE Trans. Power Electron. 2017, 32, 2808–2821. [Google Scholar] [CrossRef] [Green Version]
  8. Xing, X.; Chen, A.; Zhang, Z.; Chen, J.; Zhang, C. Model predictive control method to reduce common-mode voltage and balance the neutral-point voltage in three-level T-type inverter. In Proceedings of the 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, USA, 20–24 March 2016; pp. 3453–3458. [Google Scholar]
  9. Lee, K.-J. Analytical Modeling of Neutral Point Current in T-type Three-level PWM Converter. Energies 2020, 13, 1324. [Google Scholar] [CrossRef] [Green Version]
  10. Blasko, V. A hybrid PWM strategy combining modified space vector and triangle comparison methods. In Proceedings of the 27th Annual IEEE Power Electronics Specialists Conference, Baveno, Italy, 23–27 June 1996; pp. 1872–1878. [Google Scholar]
  11. Kakigano, H.; Miura, Y.; Ise, T. Low-Voltage Bipolar-Type DC Microgrid for Super High Quality Distribution. IEEE Trans. Power Electron. 2010, 25, 3066–3075. [Google Scholar] [CrossRef]
  12. Zhang, X.; Gong, C. Dual-Buck Half-Bridge Voltage Balancer. IEEE Trans. Ind. Electron. 2013, 60, 3157–3164. [Google Scholar] [CrossRef]
  13. Wang, F.; Lei, Z.; Xu, X.; Shu, X. Topology Deduction and Analysis of Voltage Balancers for DC Microgrid. IEEE J. Emerg. Sel. Topics Power Electron. 2017, 5, 672–680. [Google Scholar] [CrossRef]
  14. Zhang, X.; Gong, C.; Yao, Z. Three-Level DC Converter for Balancing DC 800-V Voltage. IEEE Trans. Power Electron. 2015, 30, 3499–3507. [Google Scholar] [CrossRef]
Figure 1. T-type three-level PWM converter system.
Figure 1. T-type three-level PWM converter system.
Energies 14 05969 g001
Figure 2. Phasor diagram of steady state operation.
Figure 2. Phasor diagram of steady state operation.
Energies 14 05969 g002
Figure 3. Theoretical steady state operational waveforms.
Figure 3. Theoretical steady state operational waveforms.
Energies 14 05969 g003
Figure 4. Equivalent circuit of output DC-link side.
Figure 4. Equivalent circuit of output DC-link side.
Energies 14 05969 g004
Figure 5. Maximum possible offset duty (dos_max) and required offset duty (dos) according to load variation under unbalanced condition.
Figure 5. Maximum possible offset duty (dos_max) and required offset duty (dos) according to load variation under unbalanced condition.
Energies 14 05969 g005
Figure 6. Operational waveforms under balanced load condition.
Figure 6. Operational waveforms under balanced load condition.
Energies 14 05969 g006
Figure 7. Operational waveforms under unbalanced load condition. (a) Output power deviation (ΔP): 40% (b) Output power deviation (ΔP): 45%.
Figure 7. Operational waveforms under unbalanced load condition. (a) Output power deviation (ΔP): 40% (b) Output power deviation (ΔP): 45%.
Energies 14 05969 g007
Figure 8. Photograph of the experimental test.
Figure 8. Photograph of the experimental test.
Energies 14 05969 g008
Figure 9. Experimental waveforms under balanced load condition. (a) vgab: grid line-to-line voltage; iga: grid current; doa: final duty; io: averaged neutral point current. (b) vgab: grid line-to-line voltage; iga: grid current; vH, vL: DC-link voltage.
Figure 9. Experimental waveforms under balanced load condition. (a) vgab: grid line-to-line voltage; iga: grid current; doa: final duty; io: averaged neutral point current. (b) vgab: grid line-to-line voltage; iga: grid current; vH, vL: DC-link voltage.
Energies 14 05969 g009
Figure 10. Experimental waveforms under unbalanced load condition corresponding to 40% deviation of output power. (a) vgab: grid line-to-line voltage; iga: grid current; doa: final duty; io: averaged neutral point current. (b) vgab: grid line-to-line voltage; iga: grid current; vH, vL: DC-link voltage.
Figure 10. Experimental waveforms under unbalanced load condition corresponding to 40% deviation of output power. (a) vgab: grid line-to-line voltage; iga: grid current; doa: final duty; io: averaged neutral point current. (b) vgab: grid line-to-line voltage; iga: grid current; vH, vL: DC-link voltage.
Energies 14 05969 g010
Figure 11. Experimental waveforms under unbalanced load condition corresponding to 45% deviation of output power. (a) vgab: grid line-to-line voltage; iga: grid current; doa: final duty; io: averaged neutral point current. (b) vgab: grid line-to-line voltage; iga: grid current; vH, vL: DC-link voltage.
Figure 11. Experimental waveforms under unbalanced load condition corresponding to 45% deviation of output power. (a) vgab: grid line-to-line voltage; iga: grid current; doa: final duty; io: averaged neutral point current. (b) vgab: grid line-to-line voltage; iga: grid current; vH, vL: DC-link voltage.
Energies 14 05969 g011
Table 1. System Specifications.
Table 1. System Specifications.
Output power (Po)3.2 kW
Output DC-link voltage (vH, vL)200 V
Grid line-to-line voltage (Vg,ll)220 Vrms
Filter inductance (L)3 mH
Equivalent series resistance (R)0.1 Ω
Output DC-link capacitance (C)1680 uF
Switching frequency (fs)10 kHz
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Share and Cite

MDPI and ACS Style

Lee, K.-J. Analysis of Allowable Unbalanced Load Conditions for T-Type Three-Level PWM Converter. Energies 2021, 14, 5969. https://doi.org/10.3390/en14185969

AMA Style

Lee K-J. Analysis of Allowable Unbalanced Load Conditions for T-Type Three-Level PWM Converter. Energies. 2021; 14(18):5969. https://doi.org/10.3390/en14185969

Chicago/Turabian Style

Lee, Kui-Jun. 2021. "Analysis of Allowable Unbalanced Load Conditions for T-Type Three-Level PWM Converter" Energies 14, no. 18: 5969. https://doi.org/10.3390/en14185969

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop