Design Centering of Compact Microwave Components Using Response Features and Trust Regions

Abstract

Fabrication tolerances, as well as uncertainties of other kinds, e.g., concerning material parameters or operating conditions, are detrimental to the performance of microwave circuits. Mitigating their impact requires accounting for possible parameter deviations already at the design stage. This involves optimization of appropriately defined statistical figures of merit such as yield. Although important, robust (or tolerance-aware) design is an intricate endeavor because manufacturing inaccuracies are normally described using probability distributions, and their quantification has to be based on statistical analysis. The major bottleneck here is high computational cost: for reliability reasons, miniaturized microwave components are evaluated using full-wave electromagnetic (EM) models, whereas conventionally utilized analysis methods (e.g., Monte Carlo simulation) are associated with massive circuit evaluations. A practical approach that allows for circumventing the aforementioned obstacles offers surrogate modeling techniques, which have been a dominant trend over the recent years. Notwithstanding, a construction of accurate metamodels may require considerable computational investments, especially for higher-dimensional cases. This paper brings in a novel design-centering approach, which assembles forward surrogates founded at the level of response features and trust-region framework for direct optimization of the system yield. Formulating the problem with the use of characteristic points of the system response alleviates the issues related to response nonlinearities. At the same time, as the surrogate is a linear regression model, a rapid yield estimation is possible through numerical integration of the input probability distributions. As a result, expenditures related to design centering equal merely few dozens of EM analyses. The introduced technique is demonstrated using three microstrip couplers. It is compared to recently reported techniques, and its reliability is corroborated using EM-based Monte Carlo analysis.

1. Introduction

Microwave design workflows, including optimization procedures, are most often concerned with nominal designs, where possible uncertainties of geometry and material parameters are not accounted for. At the same time, fabrication tolerances, incomplete knowledge of material characteristics (e.g., dielectric permittivity of the substrate) or operating conditions (temperature, geometrical distortions, input signal power), might all alter the electrical performance parameters of the system [1,2]. Fabrication tolerances result from from manufacturing inaccuracies (e.g., chemical etching in the case of microstrip components), and its quantification can be performed using probability distribution, e.g., uniform or Gaussian, with a given maximum deviation or variance, respectively. Tolerance-based parameter deviations may hamper fulfilling the assumed performance specifications by the system under design. Therefore, the assessment of their effects on the circuit characteristics is of practical importance. The same can be said about making the design more robust, which involves a reduction of appropriately defined statistical figures of merit [3]. Because microwave design tasks are often formulated using minimax type of specifications (e.g., lower or upper bounds for return loss, transmission, power split, etc., over certain frequency ranges), the most appropriate metric is a yield [4]. The second type of the aforementioned uncertainties (often referred to as epistemic ones [5]) is normally tackled by making sure that the system works properly for the assumed range of operating conditions (e.g., the temperature, input signal power) [6].

Quantification of uncertainties is associated with statistical analysis [7], which—when carried out directly using electromagnetic (EM) simulation models—is impractically expensive. For example, estimation of the yield using Monte Carlo simulation typically requires hundreds of circuit evaluations because the process is slowly convergent [8]. On the other hand, utilization of EM analysis is mandatory for reliability reasons. This is particularly the case for miniaturized devices featuring strong EM cross-couplings (e.g., due to transmission line folding [9] or incorporation of compact microstrip cells [10]). For such circuits, equivalent network or analytical models are simply too inaccurate. Acceleration of uncertainty quantification procedures can be accomplished in various ways, including simplification of the problem. A representative example is worst-case analysis [11], which is, however, of limited accuracy (i.e., leading to pessimistic estimations of the circuit performance). Undeniably, the most widespread approaches today are surrogate-assisted methods, where statistical analysis or yield optimization are carried out using a fast replacement model (e.g., neural networks [12], response surface approximation [13], polynomial chaos expansion, PCE [14,15,16]). A practical limitation is the dimensionality of the parameter space, i.e., the number of training data samples (translating into a computational cost of its acquisition) required for a construction of a reliable surrogate quickly increases with the number of the circuit parameters (also called the curse of dimensionality [17]). Available mitigation techniques include diminishing a number of directly handled dimensions [18], the usage of advanced modeling techniques (e.g., PC kriging, in which traditional trend functions, such as polynomials of low order, are substituted with PCE [19]), incorporation of model order reduction [20], as well as variable-resolution methods (co-kriging [21], space mapping [22]).

Understanding (and being able to quantify) how uncertainties affect the electrical characteristics, and the performance of circuits, is important, yet making the designs immune to tolerances is even more crucial. Increasing the likelihood of satisfying specifications under parameter deviations is known as robust design, yield-driven design, design centering or tolerance-aware design [23,24,25]. Its practical realization requires maximization of relevant statistical performance metrics (e.g., yield). Alternatively, in design centering, the aim is to allocate the design as much as possible in the center of the feasible region (i.e., possibly away from the feasible region boundary). Because evaluation of the performance metric (e.g., yield) has to be executed at all stages of the robust design process, its computational cost is substantial. As a matter of fact, straightforward EM-driven yield optimization is normally prohibitive. Utilization of surrogate modeling techniques is a practical workaround [26,27,28], with neural networks [29], polynomial chaos expansion [30,31], and space mapping [32] being the most popular approaches. Here also, the bottleneck is an expected high cost of surrogate model construction, especially that the domain of the model is larger due to expected design relocation across the optimization path. Sequential approximate optimization (SAO) [33] can be used to mitigate this problem by creating a sequence of surrogates rendered over smaller domains, which are moved along the optimization path. Although the model has to be constructed repeatedly, the cost of acquiring training data within each domain is significantly lower than in the larger one. Yet another approach is utilization of response feature technology [34]. Here, the surrogate only models the coordinates of apposite characteristic points of the system responses (the ones that permit assessment of satisfying/violating, given design specs). Since characteristic points are in nearly linear relationship with the circuit dimensions, the metamodel can be obtained using sparse training data sets [35].

Here, we propose a novel framework for expedited design centering of microwave components. Our methodology employs forward surrogate models constructed at the level of response features corresponding to the performance figures of interest (bandwidth, power split ratio), as well as trust-region framework for direct maximization of the surrogate-estimated circuit yield. Reformulating the uncertainty quantification task in the context of response features mitigates the dimensionality and nonlinearity-related issues. Furthermore, as the surrogate itself is a linear regression model, numerical evaluation of the yield is straightforward and fast through numerical integration of the input probability distributions. The presented technique has been demonstrated using three microstrip couplers, two single- and a dual-band one. For all structures, the cost of design centering was remarkably low, below forty EM analyses of the respective circuit, which is considerably less than for the state-of-the-art surrogate-based methods employed as benchmark. The yield estimation reliability is confirmed using direct EM-based Monte Carlo analysis.

2. Microwave Design Centering by Response Features and Trust Regions

This section formulates the introduced design centering procedure. We start by formulating the design centering task (Section 2.1), whereas Section 2.2 discusses response features in the context of microwave couplers, which are used here for demonstrating the methodology. Yield maximization using feature-based forward regression surrogates and trust regions is described in Section 2.3. Numerical verification of the framework involving three microstrip couplers will be provided in the next section.

2.1. Formulation of Design Centering Problem

For the sake of illustration, this work focuses on compact microstrip couplers, where effects of the manufacturing tolerances are primarily visible through alterations of the power split ratios as well as the shifts of the operating frequencies. The goal of design centering is to increase the likelihood that the specs will be fulfilled given the tolerances. The specifications are formulated here for a general case of multi-band coupler, where x refers to a vector of designable parameters, f_L.k and f_R.k stand for the lower and upper ends of the kth operating band, k = 1, …, N, whereas D_k are maximum allowed power split errors for the kth operating frequency f_0.k = [f_R.k − f_L.k]/2, with S_k being the respective target power split ratios. The circuit at the design x is said to satisfy the specifications if

$$\max \left\{f\in {\displaystyle {\cup }_{k=1}^N\left[f_{L.k},f_{R.k}\right]}\hspace{0.17em}:\hspace{0.17em}|S_{11}(\mathit{x},f)|\right\}\le S_{\max }$$

(1)

$$\max \left\{f\in {\displaystyle {\cup }_{k=1}^N\left[f_{L.k},f_{R.k}\right]}\hspace{0.17em}:\hspace{0.17em}|S_{41}(\mathit{x},f)|\right\}\le S_{\max }$$

(2)

$$\left||S_{31}(\mathit{x},f_{0.k})|-|S_{21}(\mathit{x},f_{0.k})|-S_k\right|\le D_k\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}k=1,\dots ,N$$

(3)

For simplicity of notation, whenever |S_j1(x,f)| is used, it is understood as dB-valued entity. In particular, the left-hand sides of Equations (1)–(3) contain logarithms of the respective circuit responses, whereas the entities of the right-hand sides of the said equations (i.e., the threshold S_max, and the power split error D_k) are also expressed in dB. Here, S_max is the acceptance threshold for the matching and isolation characteristics, e.g., S_max = −20 dB. The scattering parameters in (1)–(3) are marked as explicitly dependent on parameters x and frequency f. If the aforementioned conditions are satisfied, the circuit features a sufficient bandwidth (at the S_max level) and realizes a required power split (within the assumed tolerances D_k) at all operating frequencies simultaneously.

In the following, x⁽⁰⁾ refers to the nominal design. It is a design obtained without accounting for manufacturing tolerances, so that the circuit matching |S₁₁| and isolation |S₄₁| are improved as much as possible within the target frequency ranges, while maintaining the required power split ratios. This design can be found by solving the constrained minimax task of the form

$${\mathit{x}}^{(0)}=\arg \underset{\mathit{x}}{\min }\left\{\max \left\{f\in {\displaystyle {\cup }_{k=1}^N\left[f_{L.k},f_{R.k}\right]}\hspace{0.17em}:\hspace{0.17em}\max \left\{\right|S_{11}(\mathit{x},f)|,|S_{41}(\mathit{x},f)\left|\right\}\right\}\right\}$$

(4)

with equality constraints

$$|S_{31}(\mathit{x},f_{0.k})|-|S_{21}(\mathit{x},f_{0.k})|=S_k\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}k=1,\dots ,N$$

(5)

In practice, the constraints can be handled using a penalty function approach because they are expensive to evaluate [36]. The solution of (4), (5) features the best achievable matching and isolation in the frequency bands of interest as well as target power split ratios at the respective centre frequencies.

For the purpose of design centering, we will denote by dx the vector of parameter deviations from nominal values, resulting from fabrication tolerances characterized by probability distributions, specific to a given manufacturing technology, e.g., joint Gaussian G (0,σ), or uniform of maximum deviation d_max. As mentioned before, one of the most popular statistical performance metrics is yield Y [37], described as

$$Y({\mathit{x}}^{(0)})={\displaystyle \underset{X_f}{\int }p(\mathit{x},{\mathit{x}}^{(0)})d\mathit{x}}$$

(6)

In (6), p(x,x⁽⁰⁾) stands for a joint probability density function describing statistical variations of the design x w.r.t. the nominal design x⁽⁰⁾. Further, X_f is the feasible space, i.e., the set of designs conforming to the assumed performance requirements (e.g., in the form of (1)–(3) for the case of a multi-band coupler). Evaluation of the yield requires numerical integration of (6), which, in practice, can be realized using Monte Carlo simulation. Therein, Y is estimated as

$$Y({\mathit{x}}^{(0)})=N_r^{-1}{\displaystyle {\sum }_{k=1}^{N_r}H({\mathit{x}}^{(0)}+d{\mathit{x}}^{(k)})}$$

(7)

where dx^(k), k = 1, …, N_r, are random deviation vectors following the probability distribution p(.). The function H(x) in (7) is defined to assume a value of one if the condition (1)–(3) is satisfied; otherwise, H(x) is set to zero. Having (7), the maximum-yield design is defined as

$${\mathit{x}}^{*}=\arg \underset{\mathit{x}}{\min }\{-Y(\mathit{x})\}$$

(8)

Note that optimization of the yield requires evaluation of (7) throughout the process, which is a computationally expensive task. As mentioned in Section 1, it is often accelerated using surrogate modeling techniques, where Y is estimated using a fast replacement model of EM-simulated system characteristics. At the same time, construction of the surrogate may be an expensive procedure by itself, in particular, for higher-dimensional parameter spaces. Here, we use feature-based surrogates (cf. Section 2.2), which allow for reliable estimation of yield using only a handful of data samples.

2.2. Design Specifications Verification Using Response Features

In this work, design centering is realized as an iterative process. The underlying algorithm is gradient search [38], in which estimation of the yield is realized using forward surrogate models established at the level of appositely appointed response features. Figure 1 shows responses of an exemplary microwave circuit with the response features defined to account for the design specifications formulated in (1)–(3).

It can be observed that for certain points, specifically those corresponding to −20 dB levels of matching and isolation response, we are only interested in the frequency coordinates, whereas for others (here, those corresponding to transmission responses) we only need the level coordinates. The aggregated feature vector can be therefore written as

$$\mathit{P}(\mathit{x})={[p_1(\mathit{x})\hspace{0.17em}{p}_2(\mathit{x})\hspace{0.17em}\dots \hspace{0.17em}{p}_6(\mathit{x})]}^T={[f_1(\mathit{x})\hspace{0.17em}{f}_2(\mathit{x})\hspace{0.17em}{f}_3(\mathit{x})\hspace{0.17em}{f}_4(\mathit{x})\hspace{0.17em}{l}_1(\mathit{x})\hspace{0.17em}{l}_2(\mathit{x})]}^T$$

(9)

where f₁ and f₂ are the frequencies corresponding to –20 dB level of |S₁₁|, f₃ and f₄ are the frequencies corresponding to −20 dB level of |S₄₁|, and l₁ and l₂ are the levels of |S₂₁| and |S₃₁|, respectively, at the target operating frequency of the coupler. For a multi-band coupler, we will have

$$\begin{array}{c}\mathit{P}(\mathit{x})={[p_1(\mathit{x})\hspace{0.17em}{p}_2(\mathit{x})\hspace{0.17em}\dots \hspace{0.17em}{p}_{6N}(\mathit{x})]}^T=\\ {[f_{1.1}(\mathit{x})\hspace{0.17em}{f}_{2.1}(\mathit{x})\hspace{0.17em}{f}_{3.1}(\mathit{x})\hspace{0.17em}{f}_{4.1}(\mathit{x})\hspace{0.17em}{l}_{1.1}(\mathit{x})\hspace{0.17em}{l}_{2.1}(\mathit{x})\hspace{0.17em}\hspace{0.17em}\dots \hspace{0.17em}\hspace{0.17em}{f}_{1.N}(\mathit{x})\hspace{0.17em}{f}_{2.N}(\mathit{x})\hspace{0.17em}{f}_{3.N}(\mathit{x})\hspace{0.17em}{f}_{4.N}(\mathit{x})\hspace{0.17em}{l}_{1.N}(\mathit{x})\hspace{0.17em}{l}_{2.N}(\mathit{x})]}^T\end{array}$$

(10)

where the second subscript indicates the operating band (from 1 to N). Clearly, a particular definition of the vector P depends on the design specifications. The feature points themselves are readily derived from EM-simulated circuit characteristics.

Using the feature vector P, the design specification conditions (1)–(3) can be reformulated as

$$f_{1.k}(\mathit{x})\le f_{L.k},\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{f}_{3.k}(\mathit{x})\le f_{L.k}, k=1, \dots , N$$

(11)

$$f_{2.k}(\mathit{x})\ge f_{R.k},\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{f}_{4.k}(\mathit{x})\ge f_{R.k}, k=1, \dots , N$$

(12)

$$|l_{1.k}(\mathit{x})-l_{2.k}(\mathit{x})|\le D_k, k=1, \dots , N$$

(13)

The primary advantage of working at the level of response features rather than the entire circuit responses is weakly-nonlinear dependence of the feature points on geometry parameters of the system, which allows for constructing accurate surrogates using smaller training data sets. In the case of design centering, this would translate into improved reliability of the optimization process as well as its computational efficiency.

2.3. Design Centering by Means of Feature-Based Surrogates and Trust Regions

The proposed design centering procedure solves the yield maximization problem (8) using a trust-region (TR)-based algorithm that renders approximations x⁽ⁱ⁾, i = 0, 1, …, to x* [38]. In each iteration, the new approximation x⁽ⁱ⁺¹⁾ is obtained by solving

$${\mathit{x}}^{(i+1)}=\arg \underset{\left|\right|\mathit{x}-{\mathit{x}}^{(i)}\left|\right|\le d^{(i)}}{\min }\{-Y_P(\mathit{x})\}$$

(14)

where the predicted yield Y_P is obtained from the conditions (11)–(13) evaluated using the auxiliary linear regression model L⁽ⁱ⁾ of the feature vector P(x)

$${\mathit{L}}^{(i)}(\mathit{x})=\mathit{P}({\mathit{x}}^{(i)})+{\mathit{J}}_P({\mathit{x}}^{(i)})\cdot (\mathit{x}-{\mathit{x}}^{(i)})$$

(15)

in which the Jacobian matrix J_P is defined as

$${\mathit{J}}_P({\mathit{x}}^{(i)})={\left[\begin{array}{ccc}\frac{\partial p_1({\mathit{x}}^{(i)})}{\partial {\mathit{x}}_1}& \cdots & \frac{\partial p_1({\mathit{x}}^{(i)})}{\partial {\mathit{x}}_n}\\ ⋮& \ddots & ⋮\\ \frac{\partial p_{2N}({\mathit{x}}^{(i)})}{\partial {\mathit{x}}_1}& \cdots & \frac{\partial p_{2N}({\mathit{x}}^{(i)})}{\partial {\mathit{x}}_n}\end{array}\right]}^T$$

(16)

The partial derivatives in (16) can be computed based on the sensitivities of the circuit S-parameters which, in turn, are obtained using finite differentiation at the cost of n additional EM simulations of the circuit under optimization (n being the number of independent parameters). The vector x⁽ⁱ⁺¹⁾ is accepted if the gain ratio, computed as r = [Y_P#(x⁽ⁱ⁺¹⁾) − Y_P(x⁽ⁱ⁾)]/[Y_P(x⁽ⁱ⁺¹⁾) −Y_P(x⁽ⁱ⁾)], is positive. Here, Y_P# is computed using a linear model similar to (15) but with P(x⁽ⁱ⁾) replaced by P(x⁽ⁱ⁺¹⁾) extracted from EM-simulated circuit response at x⁽ⁱ⁺¹⁾. It should be noted that the employment of Y_P# is a computationally efficient way of validating the candidate design (at the cost of only one EM analysis of the circuit at hand), and it assumes that the feature point sensitivities do not alter considerably while relocating the design from x⁽ⁱ⁾ to x⁽ⁱ⁺¹⁾. This assumption is reasonable as the expected relocations are small in the norm sense (i.e., ||x⁽ⁱ⁺¹⁾ − x⁽ⁱ⁾||), more specifically, comparable to d_max. The trust region size is updated after each iteration using standard rules [38], i.e., the TR region size is increased if the gain ratio is sufficiently large (e.g., r > 0.75), and decreased if it is too small (e.g., r < 0.25). Additionally, as previously mentioned, the candidate design is only accepted if the gain ratio r > 0. If this is not the case, the iteration is repeated with a reduced trust region.

Estimation of the yield using the feature-based regression model L⁽ⁱ⁾ is carried out through Monte Carlo integration [39] of (6). It is arranged using a large number of random samples (in our numerical experiments, 100,000) generated according to the joint probability distribution p(). For each sample x_r, the regression model response L⁽ⁱ⁾(x_r) is tested against the conditions (11)–(13). The process is vectorized to ensure rapid evaluation of (6) (a typical evaluation time is 40 ms in Matlab, which is negligible compared to EM simulation time of the circuit). At the same time, using a large random set leads to a very small variance of yield estimation (less than 0.1%).

2.4. Complete Algorithm

Figure 2 shows the flow diagram of the proposed design centering procedure. The input parameter is the nominal design x⁽⁰⁾. In the first two steps, the EM analysis of the circuit is performed along with estimation of its response sensitivities, followed by extraction of the feature vectors and construction of the feature-based regression model. The latter is then applied to render a candidate design x⁽ⁱ⁺¹⁾, which is accepted if it leads to a positive gain ratio. At the same time, the trust region size is adjusted as well. Termination condition is based on convergence in argument ||x⁽ⁱ⁺¹⁾ − x⁽ⁱ⁾|| < ε or shrinking the trust region size beyond the termination threshold d⁽ⁱ⁺¹⁾ < ε. In the numerical experiments of Section 3, we use ε = 10⁻³.

3. Numerical Verification

This section provides numerical verification of the proposed design centering procedure using three examples of microstrip couplers, including two single-band structures, and a dual-band one. The computational efficiency of our technique is compared to several surrogate-based yield optimization methods. Furthermore, direct EM-based Monte Carlo analysis is employed to validate reliability of yield estimation using feature-based regression model at both the nominal and optimized designs.

3.1. Case Studies

The proposed design centering procedure is validated using three microstrip circuits, a compact rat-race coupler, RRC (Circuit I) [40] shown in Figure 3a, a miniaturized branch-line coupler, BLC (Circuit II) [41] shown in Figure 3b, and a dual-band branch-line coupler (Circuit III) [42], shown in Figure 3c. The relevant information concerning the three structures, including the substrate parameters, geometry parameters, nominal design, and performance requirements, can be found in

Table 1. Validation circuits.

	Case Study 1
	Circuit I	Circuit II	Circuit III
Substrate	RO4003 (εr = 3.38, h = 0.76 mm)	AD300 (εr = 2.97, h = 0.76 mm)	RO4003 (εr = 3.5, h = 0.51 mm)
Design parameters	x = [l1 l2 l3 d w w1]T	x = [g l1r la lb w1 w2r w3r w4r wa wb]T	x = [Ls Ws l3r w1 w2 w3 w4 w5 wv]T
Other parameters	d1 = d + |w − w1|, d = 1.0, w0 = 1.7, and l0 = 15	L = 2dL + Ls, Ls = 4w1 + 4g + s + la + lb, W = 2dL + Ws, Ws = 4w1 + 4g + s + 2wa, l1 = lbl1r, w2 = waw2r, w3 = w3rwa, and w4 = w4rwa	dL = dW = 10 mm, L = 2dL + Ls, W = 2dW + 2w1 + (Ws − 2wf), l1 = Ws/2, l2 = l321/2, l3 = l3r((Ls − w3)/2 − w4/21/2), lv1 = l3/3, lv3 = Ls/2 − w3/2 − l3 + lv1; wf = 1.15 mm
Operating bands	0.89 GHz–1.11 GHz	1.45 GHz–1.55 GHz	2.36 GHz–2.44 GHz 5.16 GHz–5.24 GHz
Maximum power split error	0.4 dB at 1 GHz	0.5 dB at 1.5 GHz	0.5 dB at 2.4 GHz 0.5 dB at 5.2 GHz
Nominal design	x(0) = [4.50 11.08 21.81 0.65 0.94 0.86]T	x(0) = [0.63 5.90 9.34 12.45 1.29 2.02 0.99 0.32 2.81 0.22]T	x(0) = [25.05 0.85 0.76 1.90 1.23 0.36 0.71 0.30 0.30]T

¹ Parameters with subscript r are relative, and their deviations are recalculated accordingly, in order to have the corresponding absolute parameters following the assumed probability distribution (here, Gaussian with variance of 0.017 mm).

. The EM-simulation models are implemented in CST Microwave Studio and evaluated using the time-domain solver. Design centering is carried out assuming that geometry parameter deviations follow independent Gaussian probability distribution with variance 0.017 mm with maximum deviations limited to 0.05 mm (about triple variance).

3.2. Reference Algorithms

For the sake of benchmarking, the yield optimization results obtained using the proposed procedure are compared to those produced by several surrogate-based methods. The reference techniques are briefly characterized in the remaining part of this section.

Reference algorithm 1: This is a surrogate-assisted approach incorporating a metamodel established in a relatively large vicinity of the nominal design to enable sufficient relocation of the design during yield optimization. The problem (8) is solved using local optimization algorithm. Here, the metamodel is constructed using kriging interpolation [43], whereas the domain is defined as an interval [x⁽⁰⁾ − d, x⁽⁰⁾ + d]. The entries of the size vector d = [d₁ … d_n]^T are set to d_k = 10d_max, k = 1, …, n (recall that d_max is the maximum parameter deviation, which, in our experiments is 0.05 mm). This size of domain normally creates a sufficient room for design relocation in the yield maximization process. The advantage of this procedure is implementation simplicity. The drawback is a potentially high cost of training data acquisition, which is especially troublesome to structures described by larger numbers of geometry parameters.

Reference algorithm 2: This procedure adopts the sequential approximate optimization (SAO) approach [33], in which the original problem (8) is solved iteratively as

$${\mathit{x}}^{(i+1)}=\arg \underset{\mathit{x}}{\min }\{-Y_s^{(i)}(\mathit{x})\}$$

(17)

where x⁽ⁱ⁾, i = 0, 1, …, are approximations to the optimum design x*. The yield estimated in the ith iteration, Y_s⁽ⁱ⁾, is computed based on the surrogate model established in the current domain being the interval [x⁽ⁱ⁾ — d_l, x⁽ⁱ⁾ — d_l], with x⁽ⁱ⁾ = [x₁⁽ⁱ⁾ … x_n⁽ⁱ⁾]^T, i.e., the domain is always centred at the current iteration point. Because the surrogate models are constructed along the optimization path, their domains can be considerably smaller than for the first reference algorithm (here, d_l = [d_l.1 … d_l.n]^T is set to d_l.k = 3d_max, k = 1, …, n).

The problem (17) is constrained to satisfy x_k⁽ⁱ⁾ − d_l.k + d_max ≤ x_k ≤ x_k⁽ⁱ⁾ + d_l.k − d_max, k = 1, …, n, which ensures that the solution is located in the domain interior and at the distance at least d_max from its boundary. The latter allows researchers to carry out Monte Carlo simulation within the region of validity of the metamodel. The advantage of this procedure is a lower cost of setting up the surrogate as compared to the previous method. However, several iterations are normally required to approach the optimum solution.

Reference algorithm 3: This procedure incorporates the performance-drive modeling concept [44]. It relies on a single metamodel. The latter is rendered in the domain spanned by the most relevant directions within the parameter space, specifically those that affect the likelihood of satisfying the assumed design requirements in the most significant manner. The relevant directions are found through auxiliary local optimizations [45]. The principal advantage of this method is the low volume of the surrogate model domain, which is however of sufficient size wherever necessary. Consequently, the third algorithm effectively combines the advantages of the first and the second reference methods. The conceptual illustration of the metamodel domain definition can be found in Figure 4.

3.3. Results and Discussion

The numerical results obtained using the proposed design centering approach as well as the reference algorithms outlined in Section 3.2 have been gathered in

Table 2. Design centering results for Circuit I (Figure 3a).

Optimization Algorithm	Initial Yield		Optimized Yield		CPU Cost 1
	Estimated by Surrogate Model	EM-Based	Estimated by Surrogate Model	EM-Based
Reference algorithm 1	50%	42%	100%	97%	400
Reference algorithm 2	45%	42%	97%	97%	200 2
Reference algorithm 3	44%	42%	98%	98%	82
This work (Section 2)	45%	42%	99%	98%	25

¹ Optimization cost in number of EM simulations of the considered circuit. ² The algorithm convergence after three iterations (surrogate setup cost 50 training samples per iteration).

through 4 for Circuit I, II, and III, respectively. The following final (yield-optimized) designs were obtained:

• Circuit I: x* = [4.65 11.22 21.73 0.73 0.94 0.86]^T;
• Circuit II: x* = [0.64 5.50 9.27 12.49 1.27 2.06 1.05 0.32 2.85 0.24]^T;
• Circuit III: x* = [25.16 0.80 0.77 1.89 1.25 0.42 0.75 0.30 0.30]^T.

The computational cost of the design centering process was very low and corresponded to only 25, 37, and 32 EM simulations of Circuit I, II, and III, respectively. It can be observed that this cost is considerably lower than that required by the reference algorithms. In particular, the average computational savings over the reference algorithm 1 are as high as 95 percent, 89 percent over the reference algorithm 2, and about 68 percent over the reference algorithm 3. The improvements in terms of computational efficiency are primarily due to the usage of response features and incorporation of a simple (here, linear) surrogate. The accuracy of the latter is a result of constructing the metamodel at the level of feature point coordinates, which, as previously mentioned, are in weakly-nonlinear relationship with the geometry parameters of the circuit (as compared to that of the entire circuit responses), which allows for constructing accurate surrogates using smaller training data sets. At the same time, as the surrogate is a linear regression model, a rapid yield estimation is possible through numerical integration of the input probability distributions. As a result, expenditures related to design centering equal merely a few dozen EM analyses. Observe also, that embedding the yield maximization process in the trust-region framework ensures convergence of the entire process.

The quality of the designs obtained using the proposed approach regarding the final yield values are similar to those produced by other methods. On the other hand, the predictions of the feature-based surrogate are comparable or better than those of the reference algorithms. This is corroborated through direct EM-driven Monte Carlo (MC) simulations at the nominal and the yield-optimized designs as indicated in Figure 5, Figure 6 and Figure 7. Limited predictive power is particularly pertinent to the reference Algorithm 1: although the surrogate models, therein, were constructed using a relatively large number of samples (400 for Circuit I and 800 for Circuits II and III), the relative RMS error of the metamodels is about 3.5% (Circuits I and II) and 6.1% (Circuit III), which is insufficient to render accurate yield estimation.

At the same time, it can be noticed that the accuracy of yield estimation using a feature-based surrogate is not as good as for other techniques for Circuit III. This indicates that the relationships between the geometry parameters of this circuit and response feature coordinates are more nonlinear than for other considered structures. This does lead to slightly inferior results in terms of the final yield (as confirmed by EM-driven Monte Carlo simulation), and further improvements are needed, which will be addressed in the future work. Graphical illustrations of EM-driven MC for the nominal and yield-optimized designs can be found in Table 2,

Table 3. Design centering results for Circuit II (Figure 3b).

Optimization Algorithm	Initial Yield		Optimized Yield		CPU Cost 1
	Estimated by Surrogate Model	EM-Based	Estimated by Surrogate Model	EM-Based
Reference algorithm 1	82%	77%	93%	88%	800
Reference algorithm 2	76%	77%	94%	93%	320 2
Reference algorithm 3	79%	77%	92%	93%	112
This work (Section 2)	79%	77%	90%	92%	37

¹ Optimization cost in number of EM simulations of the considered circuit. ² The algorithm convergence after three iterations (surrogate setup cost 50 training samples per iteration).

and

Table 4. Design centering results for Circuit III (Figure 3c).

Optimization Algorithm	Initial Yield		Optimized Yield		CPU Cost 1
	Estimated by Surrogate Model	EM-Based	Estimated by Surrogate Model	EM-Based
Reference algorithm 1	80%	71%	99%	93%	800
Reference algorithm 2	88%	71%	96%	91%	500 1
Reference algorithm 3	74%	71%	94%	92%	123
This work (Section 2)	71%	71%	93%	89%	32

¹ Optimization cost in number of EM simulations of the considered circuit. ² The algorithm convergence after three iterations (surrogate setup cost 50 training samples per iteration).

for Circuit I, II, and III, respectively. The analysis has been performed using 500 random samples. A comparison between the left- and the right-hand-side panels indicates a noticeable increase in the number of samples satisfying the prescribed specifications at the optimized design as compared to the nominal one.

4. Conclusions

This paper presented a novel technique for low-cost design centering of microwave components. Our methodology involves feature-based forward regression surrogates, which allow for accurate prediction of the fabrication yield under the assumed parameter deviation, as well as facilitate numerical integration of the corresponding probability density functions. The yield maximization process is embedded in the trust-region framework to ensure convergence of the process. The proposed approach has been demonstrated using three microstrip couplers, including single-band rat-race and branch-line coupler, as well as dual-band branch-line coupler. The accuracy and computational efficiency has been benchmarked against three state-of-the-art surrogate-assisted algorithms. CPU savings of up to 95 percent have been demonstrated while maintaining yield prediction reliability. In absolute terms, the cost of design centering procedure is as low as the cost of a few dozen EM analyses of the respective circuit (25 EM simulations for the compact rat-race coupler, 37 simulations for the single-band branch-line coupler, and 32 simulations for the dual-band BLC). Additional advantage of the presented approach is simple implementation. The presented design centering framework may be considered an attractive alternative to existing (especially conventional) uncertainty quantification methods, especially when rapid yield improvement is of concern. The proposed technique may be applied for EM-driven design centering of other microstrip high-frequency structures (such as antennas or filters). The example structures presented in the manuscript (i.e., the couplers and power dividers) have served merely as case studies, and were applied to demonstrate the proposed technique.