Design of Interleaved Winding for Multilayer Planar Inductor and Its Application in Reducing Current Ringing of LLC Resonant Converter

Abstract

To enhance the power density of LLC resonant converters, multilayer planar inductors are required. However, multilayer planar inductors have high parasitic capacitance, which may cause inductor current ringing in LLC resonant converters, leading to EMI problems. In this paper, it is found that by using interleaved winding inductors, compared with traditional winding inductors, the parasitic capacitance of multilayer planar inductors is reduced, which can reduce current ringing, without sacrificing power density and increasing manufacturing complexity. The method used to analyze current ringing is to establish an impedance model, and the parasitic capacitance of the interleaved winding inductors is verified by FEM simulations. The analysis is validated in an LLC resonant converter prototype.

1. Introduction

High power density converters are key devices for achieving efficient energy conversion and management, and are widely used in renewable energy, smart grids, electric vehicles, and other applications. To enhance the high power density of converters, planar transformers and inductors with printed circuit board windings are used, which reduce the converter volume and facilitate production and assembly. However, the design of planar magnetic components needs to be optimized, as the inevitable parasitic capacitance of planar magnetic components alters the impedance characteristics of the circuit and causes common-mode noise and current ringing in the converter, which affects its performance and electromagnetic compatibility. Common-mode noise and current ringing can be reduced by using an optimized design for planar transformers, as verified by experiments.

In the application of resonant converters, the common-mode noise caused by the parasitic capacitance between the primary windings of the planar transformer is described in [1], where a verification experiment was conducted with an LLC resonant converter. Regarding the influence of the parasitic capacitance of the planar transformer on impedance, Refs. [2,3,4,5] conducted an impedance analysis, calculated the influence of the low-impedance transmission path of the common-mode noise, and described the current expression of the common-mode noise. To address this issue, Ref. [6] proposed the Y-capacitor method, which controls the common-mode noise conduction path and reduces EMI noise effectively, but this method cannot be applied to resonant converters. Therefore, Ref. [7] proposed a design scheme to eliminate common-mode noise in LLC resonant converters by using common-mode inductors. The implementation method is to design the resonant inductor as two series common-mode inductors, thereby eliminating common-mode noise. However, the resonant inductor needs to occupy more PCB area, which is not conducive to improving the converter power density.

For the analysis of the parasitic capacitance of the inductor, Refs. [8,9,10] give an accurate calculation model of inductor parasitic capacitance and verify it in a DAB active full-bridge converter. In [11], the causes of planar inductor parasitic capacitance were analyzed; a planar inductor structure optimization scheme was designed; and the parasitic capacitance was reduced. Moreover, Ref. [12] defined the resonance frequency caused by the parasitic capacitance of the inductor as the first resonance frequency, and gave an accurate calculation. Furthermore, Ref. [13] analyzed the parasitic capacitance in series and parallel windings, and used the method of combining the series and parallel windings to reduce the parasitic capacitance of the inductor. Methods for reducing the parasitic parameters of planar magnetic components were summarized in [14], and it was verified that the parasitic capacitance can be effectively reduced by optimizing the winding design. Reducing current ringing can decrease the EMI issues of converters, as demonstrated in [15,16,17,18]; thus, mitigating current ringing is an important technique to reduce the EMI problems in converters.

In this paper, an optimized design of a resonant inductor for a high-power density converter based on LLC resonant topology is proposed, which reduces the current ringing of the converter. Therefore, the structure of this paper is as follows: Section 2 analyzes the impedance model of the LLC resonant converter with parasitic capacitance of the resonant inductor and obtains the method of calculating the ringing current. Section 3 analyzes the parasitic capacitance of the resonant inductor suitable for high power density converters. Section 4 presents the comparative experimental results, and Section 5 concludes this paper.

2. Analysis of Impedance and Current Ringing

As shown in Figure 1, the LLC resonant converter consists of a full bridge, a rectifier bridge, and resonant components. The full bridge contains four power switches $S_1$, $S_2$, $S_3$, and $S_4$, and the rectifier bridge consists of four rectifier diodes $D_1$, $D_2$, $D_3$, and $D_4$. The resonant components form the resonant tank, including the influence of the parasitic capacitance of the resonant inductance $L_r$; in this paper, the modeling of the LLC resonant converter adds the parasitic capacitance $C_{\mathit{stray}}$ of the resonant inductance. Figure 1 shows the equivalent circuit model of the LLC resonant converter with the parasitic capacitance of the resonant inductance. In this model, $v_{AB}$ and $v_{CD}$ are the two voltages generated by the full bridges on the input and output sides, respectively, and $v_1$ and $v_2$ are the node voltages.

According to previous research, the parasitic parameters have an impact on the input impedance and output impedance of the converter, and the equivalent model of the resonant inductor is shown in Figure 2. As known from previous research, the parasitic capacitance creates a low-impedance path for the high-frequency voltage content, and the higher harmonics caused by the $dv/dt$ in the circuit are the source of the ringing current. This will generate high-frequency current ringing on the primary side, resulting in oscillating energy, which causes losses and electromagnetic compatibility problems, both of which are undesirable effects. In this scenario, the voltage and impedance models should be considered. Therefore, to analyze the ringing current of the LLC resonant converter, it is necessary to establish the time domain equation of the ringing current, shown in (1).

$$i_{\mathit{ringing}}=C_{\mathit{stray}}\left(\frac{d{v}_1}{dt}-\frac{d{v}_2}{dt}\right)$$

(1)

As shown by the equivalent impedance diagram in Figure 3, $v_1$ is the node voltage value of the voltage of the parasitic capacitance of the input resonant inductor and $v_2$ is the node voltage value of the voltage of the parasitic capacitance of the output resonant inductor. According to the impedance relationship, it can be known that $v_1$ is numerically equal to the input voltage $V_{in}$ and $v_2$ is equal to the voltage of the resonant capacitor $V_{C_r}$. The voltage of the resonant capacitor $V_{C_r}$ can be obtained from the input voltage by the impedance relationship. In order to obtain $v_2$, the input impedance and partial impedance are defined, respectively, and the expressions are shown in (2).

$$\begin{gathered} Z_{\mathit{input}}=\left(Z_{R_s}+Z_{L_r}\right)//Z_{C_{\mathit{stray}}}+Z_{C_r}+Z_{L_m}//Z_{R_{\mathit{load}}}//Z_{C_{\mathit{out}}} \\ =\frac{s{L}_r+R_s}{s^2{L}_r{C}_{\mathit{stray}}+s{R}_s{C}_{\mathit{stray}}+1}+\frac{1}{s{C}_r}+\frac{s{L}_m+R_{\mathit{load}}}{s^2{L}_m{C}_{\mathit{out}}{R}_{\mathit{load}}+s{L}_m+R_{\mathit{load}}} \\ {Z}_{\mathit{section}}=Z_{C_r}+Z_{L_m}//Z_{R_{\mathit{load}}}//Z_{C_{\mathit{out}}}=\frac{1}{s{C}_r}+\frac{s{L}_m+R_{\mathit{load}}}{s^2{L}_m{C}_{\mathit{out}}{R}_{\mathit{load}}+s{L}_m+R_{\mathit{load}}} \end{gathered}$$

(2)

The input impedance $Z_{\mathit{input}}$ is defined as the total impedance from the input voltage to the load, and the partial impedance $Z_{\mathit{section}}$ is defined as the impedance excluding the resonant inductor and its parasitic capacitance. with $Z_{\mathit{input}}$ and $Z_{\mathit{section}}$, the expression of $V_{C_r}$ can be obtained from the input voltage $V_{in}$, as shown in (3), where $Z_{L_r}$ is the equal impedance of the resonant inductor and its parasitic capacitance, as shown in (4).

$$V_{C_r}=V_{in}-V_{in}\frac{Z_{\mathit{section}}}{Z_{\mathit{input}}}=V_{in}\frac{Z_{\mathit{input}}-Z_{\mathit{section}}}{Z_{\mathit{input}}}=V_{in}\frac{Z_{L_r}}{Z_{\mathit{input}}}$$

(3)

$$Z_{L_r}=\frac{s{L}_r+R_s}{s^2{L}_r{C}_{\mathit{stray}}+s{R}_s{C}_{\mathit{stray}}+1}$$

(4)

Substituting (2)–(4) into (1), the expression of current ringing represented by the parasitic capacitance $C_{\mathit{stray}}$, the input voltage $V_{in}$, and the impedances $Z_{\mathit{input}}$ and $Z_{L_r}$ can be obtained, as shown in (5), where $Z_{\mathit{ringing}}$, which is called the ringing impedance, is shown in (6).

$$i_{\mathit{ringing}}=C_{\mathit{stray}}\left(\frac{d{v}_1}{dt}-\frac{d{v}_2}{dt}\right)=C_{\mathit{stray}}\frac{d{V}_{in}}{dt}{Z}_{\mathit{ringing}}$$

(5)

$$Z_{\mathit{ringing}}=1-\frac{Z_{L_r}}{Z_{\mathit{input}}}$$

(6)

By the harmonic component analysis method, it can be known that the high-frequency harmonics contained in $d{V}_{in}/dt$ can be expressed as (7), and, after rearrangement, as shown in (8).

$$\begin{gathered} V_{\mathit{harmonic}}={\sum }_{k=1,3,5\dots }^{\infty }{b}_{k}sink\omega t \\ {b}_k=\frac{4A}{\pi }cos\left(k\alpha \right)(k=1,3,5,\dots \alpha ) \\ \alpha =\frac{2\pi t_1}{T} \end{gathered}$$

(7)

$$V_{\mathit{harmonic}}=\frac{4V_{in}}{\pi }cos\left(\frac{2\pi t_1}{T}\right)sin\omega t$$

(8)

It can be seen from (8) that the amplitude of the higher harmonics $b_k$ decreases with the increase in harmonic order. By substituting (8) into (5), the expression of current ringing can be further obtained, as shown in (9).

$$i_{\mathit{ringing}}=C_{\mathit{stray}}\cdot V_{\mathit{harmonic}}\cdot Z_{\mathit{ringing}}$$

(9)

As shown in (9), we can see that the current ringing can reduce with the decrease in parasitic capacitance. In this study, the resonant inductance value of the LLC resonant converter is set to 2 μH, where the resonant capacitance $C_r$ and the resonant inductance $L_m$ are 40 nH and 10 μH, respectively. The bode diagrams of $Z_{\mathit{input}}$ and $Z_{\mathit{ringing}}$ are calculated using Matlab (R2022a) with the parasitic capacitance of the resonant inductance set to 565 pF, as shown in Figure 4a–c.

In Figure 4a, the red curve represents the Bode diagram curve of $Z_{\mathit{input}}$ and the blue curve shown in Figure 4b depicts the Bode diagram curve of $Z_{\mathit{ringing}}$. From the Bode diagram, it is shown that the resonance point of $Z_{\mathit{input}}$ is 565 kHz, which coincides with the resonant frequency of the LLC resonant converter. From the bode diagram curves of $Z_{\mathit{input}}$ and $Z_{\mathit{ringing}}$, it can be observed that the harmonic impedance attains the minimum at 5 MHz, which leads to a low-impedance path in the LLC resonant converter, corresponding to the self-resonant frequency of the resonant inductor with parasitic capacitance. As demonstrated by the calculation results, the expression (9) can be further verified, indicating that the parasitic capacitance of the resonant inductor decreases; thus, the current ringing can be reduced.

3. Stray Capacitance of Multilayer Planar Inductor

As discussed in the previous section, the parasitic capacitance of the resonant inductor causes current ringing for the LLC resonant converter. Therefore, when the planar inductor is used as the resonant inductor of the LLC resonant converter, the parasitic capacitance of the planar inductor should be reduced by optimizing the structural design of the planar inductor winding. To satisfy the design requirements of high power density converters, the resonant inductors should also be designed with high power density. Hence, the area of the printed circuit boards for the windings of the planar inductors should be minimized. The planar inductors consist of printed circuit board windings with a wide width to enhance their current carrying and heat dissipation capabilities. To meet the inductance design parameters, the required inductance value parameters are achieved by using multilayer windings in series. Moreover, the planar inductors employ parallel-connected multiple windings to further increase their current carrying capability.

3.1. Design of Planar Inductors and Calculation of Parasitic Capacitance

In this study, we designed planar inductors with 2 µH inductance using the E22 ferrite core and the 3F4 core material from Ferroxcube. This prevented inductor saturation and allowed for the planar inductors to operate at frequencies above 1 MHz. We applied the inductor turns number design formula, as shown in (10).

$$N=\sqrt{\frac{Ll}{\mu A}}$$

(10)

where $L$ is the inductance value of the designed inductor, $l$ is the magnetic path length of the E22 core, and $A$ is the cross-sectional area of the E22 core. Using Equation (10) to calculate the required turns number of an inductor, the turns of the winding should be four turns. We designed a two-layer printed circuit board in series with a four-turn winding structure, with two turns in a single layer and a turn width of 2.5 mm in every turn. The outer turn of the winding in a single-layer printed circuit board had a length of 89.564 mm and the inner turn had a length of 54.173 mm, Figure 5b shows a cross-sectional diagram of the traditional winding design of a planar inductor.

According to the definition of parasitic capacitance of multilayer conductors, the parasitic capacitance value of the planar inductor depends on the interlayer energy and the input voltage. The calculation formula is shown in Equation (11).

$$\begin{gathered} C_{\mathit{stray}}=\frac{2E_{\mathit{total}}}{{V_{L_r}}^2} \\ {E}_{\mathit{total}}=\sum _{i=1}^N{E}_i \end{gathered}$$

(11)

$C_{\mathit{stray}}$ is the parasitic capacitance obtained by using the energy relation, also known as dynamic capacitance; $E_{\mathit{total}}$ is the total energy, which is the sum of the energy between adjacent copper layers. $V_{L_r}$ is the voltage value on the multilayer planar inductor.

The energy calculation method between adjacent copper layers is shown in Equation (12), where $∆V$ is the voltage difference between the upper and lower adjacent copper layers; $C$ is the electrostatic capacitance between the conductors, which is only determined by the dielectric constant, the overlapping area of the conductors, and the distance between the adjacent conductors; ${\epsilon }_r$ is the relative permittivity of the medium between the conductors; ${\epsilon }_0$ is the relative permittivity in vacuum; $A$ is the overlapping area of the upper and lower adjacent copper layers; and $d$ is the distance between the upper and lower adjacent copper layers.

$$\begin{gathered} E_i=\frac{1}{2}C\cdot {∆V}^2 \\ C={\epsilon }_r{\epsilon }_0\frac{A}{d^2} \end{gathered}$$

(12)

As shown in (12), optimizing the parasitic capacitance without changing the line width reduces the voltage difference between the adjacent copper layers. Since in a traditional winding method, the voltage drops to half of the voltage on the planar inductor when a single-layer two-turn winding is finished, there is a large potential difference between the upper and lower adjacent copper layers in a traditional winding method. Considering that the voltage drop in the winding is uniform, a two-turn winding that is traditionally wound on the same layer should be changed to a two-turn winding that is wound up and down; this design is an interleaved winding design, and a cross-sectional diagram of the interleaved winding design is shown in Figure 5a. Similarly, in a single-layer PCB, the width of the winding is 2.5 mm and the line width of each turn is equal, a length of the outer turn of the winding is 89.564 mm, and a length of the inner turn is 54.173 mm.

In order to reduce the cost of the verification experiment and verify the parasitic capacitance of the planar inductor with multilayer winding, a flexible printed circuit board was used to design the verification of the planar inductor with multilayer winding. The single-layer winding consisted of two turns, and six windings were connected in parallel to form a 12-layer PCB structure, which constituted a multilayer planar inductor winding. The single FPC used has two copper layers, with a thickness of 0.11 mm and a copper layer thickness of 1/3OZ. The distance between adjacent copper layers is 50 µm. Six flexible printed circuit boards are stacked and connected in parallel, as in the 3D model shown in Figure 6.

Therefore, according to Equation (12), the electrostatic capacitance values of the outer turns of the two planar inductor winding structures are both 63 pF, and the electrostatic capacitance value of the inner turn is 39 pF. The different parasitic capacitance values of the two winding structures are due to the potential difference between the upper and lower adjacent conductor layers. Assuming that the voltage on the planar inductor is 12 V, the parasitic capacitance values of the traditional and interleaved winding designs are calculated by Equation (11). The parasitic capacitance of the resonant inductor with traditional winding is 257 pF, and the parasitic capacitance of the resonant inductor with interleaved winding is 117 pF.

3.2. Finite Element Analysis and Simulation Verification of Planar Inductor Parasitic Capacitance

To verify the theoretical analysis, FEM analysis is presented to verify the parasitic capacitance of multilayer planar inductors. ANSYS Maxwell 2021 R1 is used to simulate the electric field distribution and extract the total equivalent capacitance. To reduce computational complexity, the 3D simulation results of the inductor can be easily calculated for each turn. The 3D simulation model was constructed based on the winding structure shown in Figure 6, with both inductor designs having the same thickness and width of the copper foil, number of layers per winding, distance between layers, length of the outer and inner turns of the winding, number of flexible PCB layers used per winding, and the number of windings in parallel. Specifically, the thickness of the copper foil was 1/3OZ, the width was 2.5 mm, the number of turns per winding was 4, the number of windings in parallel was 6, the number of flexible PCB layers used per winding was 2, the distance between layers was 50 µm, the length of the outer turn of the winding was 89.564 mm, and the length of the inner turn was 54.173 mm. During simulation, the same voltage excitation was applied to both winding models, with a value of 12 V and a frequency of 450 kHz.

Since the specifications of the windings were identical, with the exception of the winding method, and the voltage excitation frequency used in the simulation was consistent, the dc impedance of both winding designs was 29 mΩ. As for the AC impedance, it is primarily influenced by the skin effect and proximity effect. References [19,20] have calculated the AC impedance caused by the skin and proximity effects on copper foil, with the calculation method shown in Equation (13).

$$\begin{gathered} R_{ac}=R_{\mathit{skin}}+R_{\mathit{proximity}} \\ =R_{dc}\left[\frac{\sinh \xi \left(\eta \right)+\sin \xi \left(\eta \right)}{\cosh \xi \left(\eta \right)-\cos \xi \left(\eta \right)}+{\eta }^2{\left(2m-1\right)}^2\cdot \frac{\sinh \xi \left(\eta \right)-\sin \xi \left(\eta \right)}{\cosh \xi \left(\eta \right)+\cos \xi \left(\eta \right)}\right] \\ \xi \left(\eta \right)=\frac{\sqrt{\pi }}{2}\frac{d}{\delta \left(\eta \right)} \\ \delta \left(\eta \right)=\frac{1}{\sqrt{\pi f{\mu }_0\sigma \eta }} \\ \eta =\frac{s}{d} \end{gathered}$$

(13)

In Equation (13), $R_{\mathit{skin}}$ and $R_{\mathit{proximity}}$ represent the impedance contributions from the skin effect and proximity effect, respectively. The coefficient $\eta$ denotes the relationship between the spacing $s$ and the thickness $d$ of adjacent copper layers, $\delta \left(\eta \right)$ is the skin depth, $f$ is the frequency, ${\mu }_0$ is the permeability of free space, and $\sigma$ is the electrical conductivity of copper, with $m$ being the number of adjacent copper layers. Given that the winding designs for both inductors were such that the inner and outer turns of the same copper layer have identical lengths, and the spacing between adjacent copper layers was the same, calculations using Equation (13) reveal that the AC impedance due to the proximity effect for both winding structures was 30.16 mΩ, the AC impedance due to the proximity effect was 1.48 Ω, and the total AC impedance for both designs was 1.52 Ω.

Figure 7 and Figure 8 shows the simulation results. According to the simulation, the simulated capacitance of the planar inductor winding using the traditional winding structure is 253.6 pF, while the simulated capacitance of the planar inductor winding using the interleaved winding structure is 116.5 pF. Therefore, the parasitic capacitance of the planar inductor winding using the interleaved winding structure is only 42% of that using the traditional winding structure, and the result is very close to the theoretical analysis calculation result in Section 3.1.

3.3. Summary

In this section, the FEM analysis of the electric field distribution and the simulated parasitic capacitance are presented. The FEM simulation can verify the theory that the planar inductor winding using the interleaved winding structure can significantly reduce the parasitic capacitance of the planar inductor compared with the traditional winding structure.

4. Experiment and Verification

In order to verify the effectiveness of the inductor design scheme, the traditional winding inductor and the interleaved winding inductor shown in Figure 9 were made by using flexible printed circuit boards. Both inductors had an inductance value of 2 μH and were composed of six flexible PCBs stacked and connected in parallel. Each flexible PCB was a two-layer board, and a single flexible PCB board formed a four-turn winding. The line width and line spacing were equal, and the samples are shown in Figure 10. Compared to constructing a multilayer planar inductor with either a 12-layer traditional PCB or six 2-layer traditional PCBs in parallel, employing flexible PCBs for validating the multilayer planar inductor design can significantly reduce the fabrication costs and cycle time for experimental samples. Additionally, it ensures alignment between the experimental samples and the FEM simulation model. The cores utilized were Ferroxcube E22 ferrite cores with a core material of 3F4, suitable for the design requirements of resonant inductors in resonant converters operating at switching frequencies from 10 kHz to 2 MHz. Considering the capacitance variation of resonant capacitors at high frequencies, ceramic capacitors made of NPO material, which are less affected by high frequencies, were selected. Taking into account the potential decrease in capacitance during the high-frequency operation of the LLC resonant converter, the actual resonant capacitors chosen were slightly higher than the designed resonant capacitance value. Forty IHHEC C1812N122J302T capacitors, which were manufactured by Holy Stone Enterprise Co., Ltd. (Taipei, Taiwan), each with a capacitance of 1.2 nF, were connected in parallel. Under the influence of high frequencies, specifically within 30 MHz, the actual resonant capacitance value was 40 nF.

In order to verify the current ringing phenomenon of planar inductors, two planar transformers with different structures and the same excitation inductance and leakage inductance values were selected for comparative experiments. The two planar transformers were, respectively, a planar transformer, using two windings forming the primary and secondary windings, with a 4-layer PCB and a winding structure of P-S-S-P, and another planar transformer, using multiple windings in parallel with a 24-layer PCB and a winding structure of P-P-S-S. The cores used were Ferroxcube ER51 ferrite cores with core material of 3C95. The transformation ratio of the two planar transformers was 4:4, the structure of a single winding was the same, the excitation inductance values of the two transformers were the same, the leakage inductance values were 200 nH, and the prototypes are shown in Figure 11.

The method used to verify the current ringing was to build an LLC resonant converter test platform, under the same switching frequency test conditions, measure the resonant current waveform, measure the amplitude and frequency of the current ringing using different planar inductors and planar transformers, and measure the harmonic distortion of the resonant current. The experimental platform was built as shown in Figure 12, where the primary side of the experimental platform used a full-bridge circuit composed of GaN HEMTs with the GaN System GS66516B from GaN System, Ottawa, ON, Canada, which has the advantage of low loss, and the secondary side used a full-bridge rectifier circuit composed of diodes with Infineon IDL10G65C5. During the measurement, the voltage waveform and the resonant current waveform of the primary side of the converter were measured simultaneously. The current probe used was P6021A, manufactured by Tektronix. The voltage probe used was P5100A, manufactured by Tektronix. The oscilloscope used was DSOX1204G, from Keysight Technologies, Santa Rosa, CA, USA. The LLC resonant converter test platform used a controller with the TMSF280049C to generate the full-bridge circuit switch drive signal. The input voltage was set to 12 V, and by changing the load impedance, the resonant current with different peak-to-peak values could be obtained under different load impedance values, and the current ringing was measured. The resonant network consisted of the excitation inductor $L_m$, the resonant inductor $L_r$, and the resonant capacitor $C_r$. The design parameters of the LLC resonant converter used by the test platform are shown in

Table 1. System parameters.

Symbol	Quantity	Value (Unit)
$V_{in}$	Input voltage	12 (V)
$L_r$	Resonant inductor	2 (μH)
$C_r$	Resonant capacitor	40 (nF)
$L_m$	Magnetizing inductance	10 (μH)
$N$	Transformer turn	4:4
$f_r$	Resonant frequency	565 (kHz)
$f_s$	Switching frequency	450 (kHz)
$T_d$	Switching dead time	100 (ns)

, where the resonant frequency of the LLC resonant converter was 565 kHz, the switching frequency was set to 450 kHz, and the switching dead time was set to 100 ns.

4.1. Current Ringing of Resonant Current

Using the planar transformer with a four-layer PCB, the load resistance value of the LLC resonant converter test platform was changed, and the comparison diagram of the measured resonant current waveform is shown in Figure 13. The waveform measured in channel 1 of the oscilloscope was the voltage waveform of the primary side, and the waveform measured in channel 2 was the resonant current waveform. Among them, Figure 13a–c are the resonant current waveforms obtained by using the traditional winding inductor, respectively, at loads of 25 Ω, 30 Ω, and 50 Ω. Figure 13d–f are the resonant current waveforms obtained by using the interleaved winding inductor, respectively, at loads of 25 Ω, 30 Ω, and 50 Ω. It can be observed from Figure 13 that under the same load conditions, compared with the LLC resonant converter using the traditional winding inductor, the interleaved winding inductor can reduce the current ringing of the resonant current.

Using a planar transformer with a 24-layer PCB, changing the load resistance of the LLC resonant converter test platform, and the waveform comparison diagram obtained by measurement is shown in Figure 14. Figure 14a–c are the resonant current waveforms obtained by using the traditional winding inductor, respectively, at loads of 25 Ω, 30 Ω, and 50 Ω. Figure 14d–f are the resonant current waveforms obtained by using the interleaved winding inductor, respectively, at loads of 25 Ω, 30 Ω, and 50 Ω. From Figure 14, the same experimental phenomenon as in Figure 13 can be observed, which, using the interleaved winding inductor, can reduce the current ringing.

By reducing the time division value of the oscilloscope measurement from 500 ns/div to 200 ns/div, we obtain Figure 15 and Figure 16 based on Figure 13 and Figure 14. From Figure 15 and Figure 16, the current ringing amplitude and frequency can be measured, and the current ringing amplitude is shown in

Table 2. Resonant current peak-to-peak value and current ringing measurement.

Transformer Type	Load Resistance	Interleaved Winding Inductor Current Ringing	Interleaved Winding Inductor Resonant Current Peak-to-Peak Value	Traditional Winding Inductor Current Ringing	Traditional Winding Inductor Resonant Current Peak-to-Peak Value
4-layer PCB planar transformer	25 Ω	120.5 mA	1.47 A	300 mA	1.61 A
	30 Ω	107.38 mA	1.31 A	270 mA	1.449 A
	50 Ω	80.3 mA	0.98 A	195.65 mA	1.05 A
24-layer PCB planar transformer	25 Ω	124.7 mA	1.45 A	310 mA	1.53 A
	30 Ω	110.08 mA	1.28 A	265.42 mA	1.31 A
	50 Ω	86.86 mA	1.03 A	208.69 mA	1.03 A

. From the data results in Table 2, it can be seen that compared with the planar inductor with conventional winding, the planar inductor with interleaved winding has a lower current ringing amplitude. From Figure 15 and Figure 16, it can be observed that the waveform results obtained by using the interleaved winding inductor, as shown in Figure 15a–c and Figure 16a–c, have a current ringing frequency of 20 MHz, and the measurement results using the traditional winding inductor, as shown in Figure 15d–f and Figure 16d–f, have a current ringing frequency of 10 MHz. By measuring Figure 15 and Figure 16, the current ringing amplitude of the resonant current can be obtained, as shown in Table 2. Combining the experimental results shown in Figure 15 and Figure 16, and Table 2, it can be seen that using the interleaved winding inductor, compared with the traditional winding inductor, can reduce current ringing.

4.2. Measurement of THD of Resonant Current

According to the measurement results of Figure 8, Figure 9, Figure 10 and Figure 11, the harmonic distortion of the measured resonant current waveform was measured, and the results are shown in

Table 3. Resonant current THD value.

Transformer Type	Load Resistance	Interleaved Winding Inductor Resonant Current THD Value	Traditional Winding Inductor Resonant Current THD Value
4-layer PCB planar transformer	25 Ω	5.65%	6.45%
	30 Ω	5.59%	6.57%
	50 Ω	8.86%	9.77%
24-layer PCB planar transformer	25 Ω	5.91%	7.11%
	30 Ω	4.89%	7.12%
	50 Ω	15.08%	15.97%

. From Table 3, it can be seen that under different conditions of planar transformers and loads, the harmonic distortion of the resonant current using the interleaved winding inductor was smaller than that using the conventional winding inductor. Therefore, using the interleaved winding inductor can reduce harmonic distortion.

4.3. Comparison of Different Inductor Designs

In this paper, FEM simulation models for both the interleaved winding planar inductor and the traditional winding planar inductor were established. Two types of inductors were fabricated and tested in an LLC resonant converter prototype. Theoretical calculations and simulations demonstrated that, with the same length of the outer turn of the winding, the interleaved winding planar inductor exhibits a smaller parasitic capacitance. This was experimentally validated, showing that the interleaved winding planar inductor has reduced current ringing compared to traditional winding planar inductor in the LLC resonant converter prototype. Therefore, under identical winding design parameters, the interleaved winding planar inductor not only shares the same manufacturing cost with the traditional winding planar inductor but also offers a smaller parasitic capacitance, leading to reduced ringing current when applied to LLC resonant converters.

Commonly used in power converters, toroidal inductors reduce electromagnetic interference (EMI) but cannot eliminate it entirely. Toroidal inductors are costly to manufacture and complex to install. Unable to be produced as planar structures, toroidal inductors fail to meet the miniaturization needs of power converters, which makes it difficult to reduce their size for power converters with high power density. Therefore, after a comprehensive comparison of toroidal inductors and traditional winding inductors, considering cost, installation, and the effect on suppressing current ringing, this paper proposes that the interleaved winding inductor is the best design.

5. Conclusions

This paper analyzes the causes of current ringing in LLC resonant converters. A resonant tank impedance model is established. Through the impedance model, it is found that the parasitic capacitance of the resonant inductor causes current ringing, and the method to reduce the current ringing is to reduce the parasitic capacitance of the resonant inductor. In addition, based on the planar conductor parasitic capacitance model, an interleaved winding design method for multilayer planar inductors is proposed, which reduces the parasitic capacitance of the inductor winding by reducing the voltage difference between the upper and lower adjacent layers, without changing the design requirement of the inductor winding width. FEM simulations and experimental validation demonstrated that the interleaved winding inductor exhibits a significantly lower parasitic capacitance compared to the traditional winding inductor. With the same design parameters, the parasitic capacitance of the interleaved winding inductor was only 42% of that of the traditional winding inductor. The LLC resonant converter utilizing the interleaved winding inductor showed a 60% reduction in current ringing amplitude under various loads and, consequently, the total harmonic distortion (THD) was reduced by 1%. Compared with a traditionally wound inductor, interleaved winding does not increase the additional manufacturing cost and complexity under the design requirement of high power density. The use of interleaved winding inductors can reduce the current ringing of LLC resonant converters, as well as the harmonic distortion of the converters. Therefore, the use of interleaved winding inductors is beneficial for the design of LLC resonant converters.