Solid-State Circuit Breaker Topology Design Methodology for Smart DC Distribution Grids with Millisecond-Level Self-Healing Capability

Abstract

To address the challenges of prolonged current isolation times and high dependency on varistors in traditional flexible short-circuit fault isolation schemes for DC systems, this paper proposes a rapid fault isolation circuit design based on an adaptive solid-state circuit breaker (SSCB). By introducing an adaptive current-limiting branch topology, the proposed solution reduces the risk of system oscillations induced by current-limiting inductors during normal operation and minimizes steady-state losses in the breaker. Upon fault occurrence, the current-limiting inductor is automatically activated to effectively suppress the transient current rise rate. An energy dissipation circuit (EDC) featuring a resistor as the primary energy absorber and an auxiliary varistor (MOV) for voltage clamping, alongside a snubber circuit, provides an independent path for inductor energy release after faults. This design significantly alleviates the impact of MOV capacity constraints on the fault isolation process compared to traditional schemes where the MOV is the primary energy sink. The proposed topology employs a symmetrical bridge structure compatible with both pole-to-pole and pole-to-ground fault scenarios. Parameter optimization ensures the IGBT voltage withstand capability and energy dissipation efficiency. Simulation and experimental results demonstrate that this scheme achieves fault isolation within 0.1 ms, reduces the maximum fault current-to-rated current ratio to 5.8, and exhibits significantly shorter isolation times compared to conventional approaches. This provides an effective solution for segment switches and tie switches in millisecond-level self-healing systems for both low-voltage (LVDC, e.g., 750 V/1500 V DC) and medium-voltage (MVDC, e.g., 10–35 kV DC) smart DC distribution grids, particularly in applications demanding ultra-fast fault isolation such as data centers, electric vehicle (EV) fast-charging parks, and shipboard power systems.

1. Introduction

Fault self-healing in intelligent distribution networks is a key technology for smart grids [1]. As a crucial component of smart grids, flexibly interconnected DC distribution networks rely on the rapid operation of section switches and tie switches within the DC network to achieve efficient reconfiguration of load transfer paths and the formation of planned islands [2,3,4]. However, traditional circuit breaker-based section and tie switches are incapable of achieving millisecond-level fault self-healing in intelligent distribution networks. Therefore, there is an urgent need to research novel DC circuit breaker topologies to enable rapid circuit closing and breaking actions [5,6,7].

Achieving fast operation in DC circuit breakers primarily involves addressing the following two challenges:

1. Adaptive connection of current-limiting components: Direct installation of inductor-based current limiters in the main circuit can cause system operating point drift, increasing instability risks [8]. It can also induce voltage oscillations during system transients, amplifying transient voltage peaks [9]. Thus, implementing adaptive connection of current-limiting inductors is critical to minimize system oscillation risks.

2. Rapid isolation of faulted lines: The fault isolation speed of a DC circuit breaker is constrained by the fault detection delay time and the fault current clearing time [10]. The fault detection delay depends on the detection algorithm, while fault current clearing depends on the design of the breaker’s energy dissipation circuit. Consequently, achieving efficient energy dissipation within a breaker to shorten the fault current clearing time is a vital aspect of circuit breaker topology design.

However, traditional DC circuit breakers struggle to achieve both adaptive connection of current limiters and rapid isolation of faulted lines. The difficulties include the following two points:

On the one hand, DC circuit breakers can be classified into three types based on their interruption principles and structural characteristics: mechanical DC circuit breakers (MCBs) [11], solid-state circuit breakers (SSCBs) [12], and hybrid circuit breakers (HCBs) [13,14,15]. MCBs rely on mechanical contacts to interrupt the current, achieving interruption by creating an artificial current zero and being equipped with arc-extinguishing devices [16]. SSCBs utilize solid-state switching elements to achieve arc-less fast tripping [17]. HCBs achieve interruption through a composite structure combining mechanical switches with solid-state switching elements [18]. However, traditional DC circuit breakers directly connecting the current-limiting inductor to the main circuit increase the risk of oscillations. Solid-State Fault Current Limiters (SSFCLs) [19] can achieve fault current limiting without relying on current-limiting inductors. Compared with mechanical circuit breakers and hybrid circuit breakers, solid-state circuit breakers offer the fastest breaking/opening speed, have no physically separating mechanical contacts (eliminating arc formation), and possess an extremely high operating frequency, enabling them to withstand extremely frequent opening and closing operations. This limiting method implements fault current limiting within an extremely short time after a fault occurs by adding solid-state elements to the circuit, thereby reducing the risk of system oscillations. Nevertheless, the inclusion of solid-state elements also results in higher steady-state losses in the circuit breaker [20]. Therefore, achieving adaptive (on-demand) connection of the current limiter—such that it does not increase system oscillation risk under normal conditions but automatically engages upon fault occurrence to perform its current-limiting function—represents a significant challenge in the design of novel DC circuit breaker topologies.

On the other hand, employing inductors for current limiting in DC lines can address the issue of high fault current rise rates [21]. However, since the inductor stores inductive energy during the current-limiting process, it requires coordination with a Metal Oxide Varistor (MOV) for energy dissipation [22]. The effectiveness of this energy dissipation depends on the MOV’s capacity and its own parameter design. Crucially, this approach has limited energy handling capability and cannot perform continuous interruptions; each interruption operation requires a cooling interval of over half an hour. Superconducting Fault Current Limiters (SFCLs) are suitable for large-scale power grids and high-load conditions [23]. Upon fault occurrence, the superconducting material within an SFCL enters a quenching state due to the increased fault current, rapidly generating high resistance to limit the current peak. This significantly increases the fault current clearing speed. However, the superconducting material relies on additional cooling systems, substantially increasing the physical footprint and the cost for practical applications. Positive Temperature Coefficient (PTC) thermistors can address issues of overload protection and fast recovery based on a similar principle [24]. While both SFCLs and PTC devices avoid the need to dissipate stored inductive energy after a fault, their return to the normal-state temperature after fault isolation depends on additional cooling systems.

To meet the requirements for adaptive connection and rapid isolation in DC circuit breakers, this paper proposes a topology design scheme based on a symmetrical full-bridge solid-state circuit breaker (SSCB). Its primary innovations are as follows:

1. To address the issue of oscillations induced by power flow variations during normal system operation in circuit breakers employing inductive current limiting, this paper proposes a circuit breaker topology with adaptive commutation capability. Compared to traditional solid-state circuit breakers (SSCBs), this topology enables the current-limiting inductor to remain disconnected from the system under normal conditions and automatically connect to the system upon fault occurrence. This effectively mitigates the system oscillation risk.

2. To address the issues of energy dissipation delay and limited isolation speed inherent in traditional fault isolation schemes relying on Metal Oxide Varistors (MOVs), this paper proposes an auxiliary energy dissipation scheme based on an energy dissipation circuit (EDC). This scheme enables the release of current-limiting inductor energy through an independent EDC loop after fault tripping. By connecting an MOV in parallel across the IGBT for voltage stabilization, it significantly shortens the faulted line isolation time. Compared to traditional MOV-dependent schemes (which exhibit an isolation delay of 3 ms), the proposed energy dissipation scheme can compress the fault isolation time to less than 0.1 ms, achieving microsecond-level rapid isolation. Concurrently, it reduces the thermal runaway risk of the MOV during the fault isolation process, effectively enhancing both the safety and response speed of circuit breaker tripping.

2. Related Works

2.1. Topology Structure and Operating Principle

This paper proposes a novel solid-state circuit breaker (SSCB) topology. Unlike conventional designs, it eliminates DC inductors from the main current path of the DC line. Instead, all inductors are relocated entirely to branch paths. This design eliminates the negative impacts associated with DC inductors under normal operation—specifically their inherently high steady-state losses. Upon fault occurrence, the inductors are automatically connected into the DC line, achieving adaptive commutation. Furthermore, the topology incorporates an energy dissipation circuit (EDC) consisting of diodes in series with resistors. This EDC is connected in parallel across the DC inductor to dissipate the energy stored within the inductor after tripping. The designed SSCB employs a symmetrical dual-bridge circuit structure. This configuration enables effective interruption of DC faults regardless of whether a fault occurs on the positive pole or the negative pole.

The topological structure of this new SSCB is shown in Figure 1. It consists of two full-bridge modules (each formed by two half-bridge legs) and two adaptive current-limiting branches. Within each H-bridge, every bridge leg contains an Insulated-Gate Bipolar Transistor (IGBT) switch. Each IGBT is paralleled with an MOV to dissipate the IGBT’s energy. In the branches, a DC inductor is connected in parallel with an EDC (energy dissipation circuit) and a DC bias power source. To ensure the snubber circuit functions correctly during both pole–pole (PP) faults and pole–ground (PG) faults, the midpoint of the snubber circuit is grounded. This ensures uniform voltage distribution.

Figure 1. The topology of the symmetrical full-bridge SSCB.

The operation process of this new SSCB can be divided into the normal operation state, the current-limiting state, the fault current-clearing state, and the recovery state.

(1) Normal operation state: Under normal conditions, switches S₁ and S₂ are in the on state. The DC bias power sources, U_b1 and U_b2, are used to provide the bias current at its set value ($I_b$). Assuming the conduction resistance of each bridge arm in the H-bridge is identical, $I_b$ is equally distributed to each bridge arm as (1/2)$I_b$, while the DC line current ($i_{dc}$) is also equally distributed to each bridge arm as (1/2)$i_{dc}$. Therefore, the currents flowing through S₁–S₄ ($i_1$–$i_4$) can be calculated using Formula (1) as follows:

$$\left\{\begin{array}{c}{i}_1={\displaystyle \frac{1}{2}}{I}_b+{\displaystyle \frac{1}{2}}{i}_{dc},i_2={\displaystyle \frac{1}{2}}{I}_b-{\displaystyle \frac{1}{2}}{i}_{dc}\\ i_3={\displaystyle \frac{1}{2}}{I}_b-{\displaystyle \frac{1}{2}}{i}_{dc},i_4={\displaystyle \frac{1}{2}}{I}_b+{\displaystyle \frac{1}{2}}{i}_{dc}\end{array}\right.$$

(1)

As can be seen in the above formula, if $i_{dc}$> 0, then i₁ and i₄ are greater than 0. To ensure that current can flow through the two IGBTs (S₂ and S₃) under normal conditions, enabling conduction in both bridge arms, it is necessary that $i_2$ > 0 and $i_3$ > 0, which implies $i_{dc}$ < $I_b$. Therefore, as shown in Figure 2, in the normal state when 0 < $i_{dc}$ < $I_b$, the branch is bypassed through the appropriate selection of the DC bias current ($I_b$).

Figure 2. Current flow under normal operating conditions.

(2) Current-limiting state: When a fault occurs, the DC line current ($i_{dc}$) begins to increase. According to Formula (1), $i_1$ and $i_4$ rise with the propagation of the fault current, while $i_2$ and $i_3$ decrease after a fault occurs. When $i_{dc}$ reaches $I_b$, $i_2$ and $i_3$ drop to zero. At this point, switches S₂ and S₃ turn off, and idc automatically commutates to flow through S₁, the current-limiting branch, and S₄. The SSCB then initiates the Fault Current Limitation (FCL) phase, as shown in Figure 3. The rate of rise of the fault current is limited by the DC inductor within the current-limiting branch. Therefore, the SSCB enters the current-limiting state.

Figure 3. Current flow in current-limiting stage.

(3) Fault current-clearing state: Once a fault is detected, a trip signal is sent to S₁ and S₄. As the fault current declines, the freewheeling current flowing through the DC inductor and the line inductance generate a back EMF, thereby releasing energy. R₂ and R₄ in the EDC are used to absorb the dissipated energy from L₁ and L₂, while R₁₁ and R₁₄ in the snubber circuit are used to dissipate the energy from the IGBT. The current flow in this state is shown in Figure 4.

Figure 4. Current flow in fault current-clearing stage.

(4) Recovery state: After the fault is cleared, the isolated line should be reconnected to the DC system to restore the DC bias current. At this point, the current-limiting branch is bypassed again.

2.2. Parametric Design

2.2.1. Parameter Design of Current-Limiting Inductor

To achieve effective fault current limiting, the key parameters of the current-limiting inductor must be determined based on the dynamic characteristics of the system. Taking the IGBT module FZ1000R33HE3 IHM-B (rated voltage: 3.3 kV, rated current: 1000 A) as an example, with a system-rated DC current of 50 A and a fault current protection threshold of 200–400 A, the maximum fault current rise rate is set considering the fault detection delay (t_det = 100 µs) and the IGBT’s maximum breaking capacity (400 A):

$${\displaystyle \frac{d{i}_{dc}}{dt}}={\displaystyle \frac{400\mathrm{A}-50\mathrm{A}}{100\mathsf{\mu }\mathrm{s}}}=3.5\mathrm{A}/\mathsf{\mu }\mathrm{s}$$

(2)

Based on the inductor voltage relationship and the rated DC voltage, the theoretical minimum value of the current-limiting inductor can be derived:

$$L_{\min }={\displaystyle \frac{V_{dN}}{\frac{d{i}_{dc}}{dt}}}={\displaystyle \frac{3300\mathrm{V}}{3.5\mathrm{A}/\mathsf{\mu }\mathrm{s}}}\approx 943\mathsf{\mu }\mathrm{H}$$

(3)

To provide a safety margin, the current-limiting inductor is ultimately selected as L = 950 µH, ensuring the fault current remains within the safe interruption range of the IGBT.

2.2.2. Parametric Design of Energy Dissipation Circuits

The energy dissipation circuit (EDC), composed of resistors and diodes combined in series, is designed with parameters that must satisfy the requirement for rapid release of the inductor’s stored energy. After tripping, the inductor current follows an RL zero-input response:

$$i_L(t)=I_{L0}\cdot e^{-{\displaystyle \frac{t}{\tau }}}$$

(4)

$$\tau ={\displaystyle \frac{L}{R_{EDC}}}$$

(5)

I_L0 represents the inductor current at the trip instant, while $R_{EDC}$ represents the energy absorption resistor.

To balance the energy dissipation speed with the IGBT’s voltage withstand requirement, the value of the $R_{EDC}$ must be optimized. Simulation analysis indicates that when $R_{EDC}$ = 4.7 Ω, the peak inductor voltage can be controlled within 60 V and the voltage across the IGBT remains within its safe threshold (<3.3 kV). Consequently, $R_{EDC}$ = 4.7 Ω is selected and paired with the fast-recovery diode DZ435N36K (reverse withstand voltage: 3600 V, peak current: 435 A). This configuration ensures rapid energy dissipation while avoiding the risk of reverse breakdown.

2.2.3. Device Selection and Hipot Analysis

Based on system-rated parameters and fault scenarios, withstand voltage verification is performed and key components are selected. The peak current capability (1000 A) fully accommodates fault currents during trip events.

(1) Bridge Leg IGBT Module

The IGBT withstands the maximum reverse voltage at the instant of turn-off. V_CE = V_dN + V_L = 3.3 kV + 3.325 kV = 6.625 kV. The FZ1000R33HE IHM-B module (rated voltage: 3.3 kV) is adopted. Combined with voltage-balancing resistors and dynamic gate driving, it ensures a voltage withstand margin. Its peak current capability (1000 A) fully accommodates fault currents during trip events.

(2) Snubber Circuit Diode Module

Under normal operating conditions, the snubber diode experiences near-zero voltage stress, but its voltage withstand capability is determined by transient overvoltage during faults. The Infineon DZ435N36K (rated voltage: 3600 V, peak current: 435 A) is selected, as its fast recovery characteristics effectively suppress voltage spikes.

(3) Deadtime Setting for Bridge Switches

To prevent shoot-through during commutation, a deadtime is implemented between complementary switches (e.g., S₁/S₂ and S₃/S₄ in each half-bridge). The deadtime duration (typically 1–2 µs) is configured in the gate drivers based on IGBT turn-on/off delays (t_on/t_off ≈ 0.5 µs/1.2 µs for FZ1000R33HE3) and driver propagation delay. This ensures a switch is fully off before its complement turns on. Experimental validation confirmed no shoot-through occurs during normal/fault transitions.

Through the aforementioned parameter optimization and component selection, the system achieves efficient energy dissipation during fault isolation while ensuring safe operation of all components.

2.2.4. MOV Reliability and Reclosing Constraint

The MOV’s structural vulnerability and thermal limitations necessitate caution regarding automatic reclosing. Each significant energy absorption event causes cumulative, irreversible damage to its grain boundaries. Crucially, MOVs dissipate absorbed heat slowly, requiring cooling times far exceeding typical reclosing intervals (hundreds of milliseconds). Reapplying system voltage to a hot, potentially degraded MOV before sufficient cooling creates a high risk of power frequency follow current, leading to thermal runaway and catastrophic failure. Therefore, to avoid inducing MOV damage during validation, as the primary focus was on demonstrating the ultra-fast initial isolation capability with reduced MOV burden, automatic reclosing tests were deliberately omitted from the experimental scope.

2.2.5. Cost Analysis

Regarding the construction cost, as the unit price of IGBT FZ1000R33HE IHM-B is approximately CNY 5040 and the unit price of MOV HY5WR-5/13.5 is approximately CNY 231, the cost of a traditional SSCB is calculated as follows:

$${\mathrm{Price}}_1=2\times 720+33=1473\mathrm{USD}$$

(6)

Therefore, the total construction cost of using a traditional SSCB in an MTDC system is calculated as follows:

$${\mathrm{Price}}_2=1473\times 36=\mathrm{53,028}\mathrm{USD}$$

(7)

For the designed SSCB, the cost mainly includes one IGBT (FZ1000R33HE IHM-B: USD 720), six diodes (DZ435N36K: USD 207), one reactor (USD 195), and one 10 kV transformer (USD 315). The cost of other components is relatively low. Therefore, the unit price of the designed SSCB is calculated as follows:

$${\mathrm{Price}}_3=720+6\times 207+195+315=2472\mathrm{USD}$$

(8)

Due to the price of a mechanical DCCB being approximately USD 270, the total construction cost calculated for the configuration strategy in this article is as follows:

$${\mathrm{Price}}_4=2472\times 12+270\times 24=\mathrm{36,144}\mathrm{USD}$$

(9)

Therefore, using this configuration strategy can save approximately USD 16,874, and this advantage will become more apparent as the system’s scale expands.

3. Simulation Verification

3.1. Simulation Platform Construction

A four-terminal VSC-MTDC system was established in a SIMULINK real-time simulator, as shown in Figure 5. The main system parameters are listed in Table 1. Solid-state circuit breakers (SSCBs) were installed at the DC line terminals, and the simulation primarily demonstrated pole-to-pole (PP) faults and load variations.

Figure 5. Four-terminal VSC-MTDC system.

Table 1. Simulation system parameters.

	Terminal	T1	T2	T3	T4
	AC voltage (kV)	4	4	4	4
AC power grid	Frequency (Hz)	60	50	50	60
	Active power (kW)	300	100	600	200
	DC voltage (kV)	±6.5	±6.5	±6.5	±6.5
DC lines	DC current (A)	50	50	50	50
	Capacitor (µF)	750	750	750	750

The steady-state DC line current was maintained at 2.6 A. Pole-to-pole (PP) faults were generated by a DC solid-state relay (SSR). According to university laboratory safety requirements, the maximum fault current needed to be limited to less than 25 A. Nevertheless, this range was analogous to typical fault currents in low-voltage DC systems (i.e., 63 A). Furthermore, the primary objective of this study was to characterize the SSCB’s performance; thus, greater emphasis was placed on the fault current waveform profile. Building upon this work, future research will extend it to testing in industrial-scale installations.

While the detailed analysis focused on the fault current waveform profile (magnitude, di/dt, etc.) as a key indicator of SSCB performance during the initial fault interruption phase, it is crucial to acknowledge the fundamental physical significance of the subsequent switching process, particularly concerning the Transient Recovery Voltage (TRV). Following successful current interruption by the SSCB, the TRV is the voltage transient that appears across its opening contacts. This voltage stresses the newly formed gap and is critical for determining whether the interruption is ultimately successful (arc does not re-ignite) or fails.

The magnitude and wave shape of the TRV were governed by the system’s inherent parameters (inductance, capacitance, and resistance) and the magnitude of the interrupted current. Crucially, the physical implications of the TRV scale dramatically with system voltage and current levels. A TRV of 10 V across a contact gap interrupting 10 A presents negligible stress on insulation and poses minimal re-ignition risk. In stark contrast, a TRV reaching 100 kV across contacts interrupting 10 kA imposes extreme dielectric stress, demanding sophisticated contact design (e.g., larger gaps, arc chutes, and vacuum/SF6 insulation) and precise control to manage the intense electric field and prevent destructive re-strikes. Similarly, interrupting 10 kA generates vastly higher electromagnetic forces, contact erosion, and arc energy compared to interrupting 10 A, fundamentally altering the stresses on the switching device.

Therefore, while the present study utilized RTDS and focused on characterizing SSCB behavior under the constrained, low-energy conditions (25 A max fault current and the low system voltage implied by the TRV levels achievable in this setup) pertinent to the laboratory safety scale and analogous low-voltage DC applications, we explicitly recognize that scaling to industrial-level voltages (hundreds of V to kV) and fault currents (kA range) introduces orders-of-magnitude greater challenges. The TRV becomes a dominant factor requiring careful design consideration, and the physical phenomena (electromagnetic forces, arc plasma dynamics, and dielectric recovery) during the interruption and the TRV phase become significantly more intense and complex. Future work targeting industrial applications will necessitate dedicated investigations of SSCB performance under these high-stress TRV and high-current interruption conditions.

3.2. Analysis of Simulation Results

3.2.1. Fault Clearing Simulation Analysis

The SSCB designed in this paper was set to initiate a fault signal at 1.998 s. The current in the DC circuit path is shown in Figure 6. As can be seen in the figure, the current started to drop abruptly after a 0.02 s delay post-fault. This was because the current-limiting branch incorporated a DC bias source. The current-limiting effect was only activated when the fault current exceeded the DC bias current, causing IGBT S3 to interrupt. This action thus altered the current path, interrupting the fault current after it reached its peak.

Figure 6. A fault isolation comparison: (a) the mutual inductor and (b) the novel SSCB.

Furthermore, as shown in Figure 6, the fault current in the mutual-inductor-based current-limiting scheme exhibited a gradual decline due to the inductance restricting abrupt current changes, resulting in an excessively long current-limiting period. In contrast, the fault current in the designed SSCB demonstrated a nearly vertical slope during its descent, significantly reducing the fault isolation time.

3.2.2. Current-Limiting Simulation Analysis

Under conditions without triggering tripping, a functional comparison of the two current-limiting methods was conducted. As shown in Figure 7, both the mutual-inductor-based current-limiting scheme and the designed SSCB current-limiting method could effectively suppress diode current disturbances and active power disturbances in VSC1, as well as reduce the peak current in the faulted line. The figure reveals no significant visual difference between the waveforms produced by the mutual-inductor-based scheme and the designed SSCB method. However, these two distinct current-limiting approaches exhibited significant differences in other functional aspects.

Figure 7. A fault limitation comparison: (a) the mutual inductor and (b) the novel SSCB.

3.2.3. Simulation Analysis of Current-Limiting Inductor Voltages When Using Different Resistors

The voltage variation across the current-limiting inductor under different resistances is shown in Figure 8a. When a fault pulse occurred at t = 1.998 s, the voltage across the inductor instantly surged. This phenomenon occurred because the inductor current could not change abruptly while the inductor voltage could experience instantaneous changes. Within a short duration, the inductor voltage rapidly climbed to its peak. During the period from 1.998 s to 2 s, the current-limiting voltage initially rose to its peak value and then gradually declined, maintaining an overall inductor voltage below 60 V. At t = 2 s, when the IGBT tripped, the current-limiting voltage dropped rapidly. This enabled immediate isolation of the DC line, even while the current-limiting inductor continued dissipating energy for a brief period.

Figure 8. Variation in voltage in (a) current-limiting inductor and (b) IGBT.

As indicated in the figure, when the resistance in the energy dissipation circuit (connected in parallel with the current-limiting inductor) was altered, the voltage across the current-limiting inductor changed accordingly. At t = 2 s, when the IGBT began to trip, the current was diverted from the current-limiting path to the energy dissipation circuit. Since inductor current cannot change instantaneously, the voltage across it increases with higher resistance values. The duration of this voltage is governed by the time constant (τ), where τ = L/R. For a fixed inductance, more resistance results in a shorter voltage duration. Therefore, by comprehensively considering the subsequent voltage across the IGBT, an appropriate resistance value was selected to enable rapid dissipation of the energy stored in the current-limiting inductor.

3.2.4. Simulation Analysis of IGBT Voltage Under Different Resistances

As shown in Figure 8b, the voltage variations across the IGBT under different resistances after fault occurrence demonstrated the following behavior: At the initial fault inception (t = 1.998 s), the IGBT maintained its conducting state due to its inherent high input impedance, while the fault current remained below the DC bias current. At t = 2 s, when the fault current exceeded the DC bias current, the freewheeling current through the current-limiting inductor and line inductance generated a back electromotive force (EMF) during the subsequent fault current decline. This back EMF forced the IGBT to turn off, thereby interrupting the fault current.

As observed in the figure, the voltage across the IGBT differed at resistance values of 10 Ω, 5 Ω, and 1 Ω. For IGBT voltage, lower values are preferable since excessive voltage may cause breakdown, preventing normal operation after fault recovery. Considering the voltage behavior across the current-limiting inductor under different resistances (as previously analyzed), we must ensure both rapid dissipation of energy from the current-limiting voltage and maintenance of the IGBT voltage within a safe threshold. This study adopted 5 Ω for the resistor in the energy dissipation circuit.

3.2.5. Fault Ride-Through Simulation Analysis

Following the trip event at t = 2 s, the system response of healthy components to the fault occurrence is illustrated in Figure 9. Here, I_dc2 and I_dc3 represent the DC currents of VSC2 and VSC3, respectively, while V_dc2 and V_dc3 denote the DC voltages of VSC2 and VSC3, respectively.

Figure 9. A fault ride-through comparison: (a) the mutual inductor and (b) the novel SSCB.

The DC current and voltage limits of the voltage regulator were set to 4 × I_dN = 200 A and M × U_dN = 11.05 kV (where M is the modulation index of the voltage regulator, taken as 0.85 in this study). As shown in Figure 9, the mutual-inductance current-limiting method could restrict the DC current of the VSC, but the VSC’s DC voltage decayed below 11.05 kV. In contrast, with the designed SSCB, after the trip event occurred, both the DC current and voltage of the VSC remained essentially stable. Therefore, by adopting the proposed SSCB scheme, the healthy portion of the flexible DC system successfully rode through the DC fault.

4. Experimental Results

4.1. Experimental Platform Construction

The experimental DC system was configured as shown in Figure 10, with the DC voltage maintained at 130 V, the DC bias current at 3 A, and the steady-state DC line current at 2.6 A. Pole-to-pole (PP) faults were generated using a DC solid-state relay (SSR). Per university laboratory safety requirements, the maximum fault current needed to be limited to below 25 A, although this value is similar to typical fault currents (63 A) in low-voltage DC systems. Due to the laboratory’s lower voltage level, this study did not select the FZ1000R33HE3 IHM-B and Infineon DZ435N36K modules but rather employed the low-voltage-rated IHW20N120R3 and RHRG30120 modules.

Figure 10. Experimental test system.

The main parameters of the system are listed in Table 2. In the 130 V DC experimental system, a pole-to-pole (PP) fault was initiated at t = 0.025 s, and the SSCB tripped at t = 5.025 s.

Table 2. The main parameters of the experimental system.

Component Type	Parameter	Component Type	Parameter
AC power	100 Vrms, 50 Hz	Resistive loads	46 Ω, 4 KW
DC voltage	130 V	SSR	DD220D100
DC current	2.6 A	IGBT	IHW20N120R3
DC capacitors	2700 µF	Diode	RHRG30120
R1, R3	2 Ω	R6, R7	2 Ω
R2, R4	6 Ω	L1, L2	10 mH
R5	6 Ω	L3, L4	6 mH

4.2. Comparison with Traditional SSCB

Figure 11 and Figure 12 compares the fault current response of a traditional SSCB with or without a current-limiting inductor in a DC line with the designed SSCB. Due to the fact that the designed SSCB can only produce a current-limiting effect when the fault current exceeds the DC bias current (3 A in this study), the fault current is interrupted after reaching its peak, preserving the inherent waveform characteristics of the fault current response.

Figure 11. Fault current limiting.

Figure 12. Fault current clearing.

Compared with traditional SSCBs without current-limiting inductors, the designed SSCB reduces the ratio of the maximum fault current to the rated current from 8.4 to 5.8. In addition, due to the presence of an EDC, the designed SSCB can instantly isolate DC lines (≤0.1 ms). In contrast, traditional SSCBs with or without current-limiting inductors require 0.3~0.5 milliseconds for MOVs to dissipate energy after tripping.

5. Conclusions

This paper proposes a novel SSCB topology with adaptive fault current-limiting capability specifically designed for enhancing the protection and self-healing capabilities in both low-voltage DC (LVDC, e.g., 380 V, 750 V, and 1500 V DC) and medium-voltage DC (MVDC, e.g., 10 kV, 20 kV, and 35 kV DC) distribution networks. Its ultra-fast isolation performance makes it particularly suitable for critical infrastructure requiring high power availability and minimal disruption, including the following:

1. Data center power distribution: To prevent cascading failures and maintain uninterrupted operation of sensitive IT loads.

2. Electric vehicle (EV) fast-charging stations: To ensure safety and enable rapid recovery after faults in high-power charging infrastructure.

3. Shipboard and aerospace DC microgrids: Where space, weight, and fault resilience are paramount concerns.

4. Industrial DC microgrids with sensitive processes: To minimize downtime and protect expensive equipment.

5. Renewable energy integration points (e.g., PV farms and battery storage interconnections): For reliable protection of converters and DC collection systems.

The novel SSCB topology incorporates an energy dissipation circuit (EDC) with auxiliary MOV-assisted energy dissipation and a snubber circuit. The primary innovation of this work lies in proposing a topology featuring adaptive switching functionality, enabling adaptive connection of the inductor to the main DC line. Furthermore, an auxiliary energy dissipation scheme based on an energy dissipation circuit (EDC) is introduced. In this EDC, a resistor serves as the primary element for dissipating the inductor’s stored energy, while an auxiliary MOV provides voltage clamping support. This design significantly accelerates fault isolation and reduces the energy burden, hence the capacity requirement placed on the MOV compared to traditional schemes where the MOV is solely responsible for energy absorption. Consequently, the proposed scheme achieves rapid isolation of the fault line with substantially alleviated constraints imposed by MOV capacity limitations. Compared to a traditional SSCB solution with a current limiter installed directly in the DC line, simulation and experimental results demonstrate that the proposed SSCB scheme successfully achieves adaptive commutation and realizes rapid isolation of the fault line within 0.1 ms.