Second-Order Ripple Current Suppression Based on Virtual Impedance in the Application of Dynamic Voltage Restorer

Abstract

In existing two-stage single-phase dynamic voltage restorer (DVR) voltage sag mitigation devices, the output-side power contains a pulsating component at twice the fundamental frequency (2f₀), leading to the presence of second-order ripple currents (SRCs) on the DC input side. This, to some extent, affects the reliability of the system and has a significant impact on the lifespan of energy storage devices. In this study, the dual-loop control method of the buck/boost converter is combined with the virtual impedance auxiliary control strategy to suppress SRCs. Compared to existing solutions, this method offers the advantages of being fast, stable, and reliable, while the virtual impedance auxiliary control strategy is flexible and easy to implement. The feasibility and stability of this strategy were verified using a 3 kW DVR prototype. When applying the two virtual impedance methods, the second harmonic content was reduced from 39.64% to 1.74% and 1.78%, respectively. The proposed control strategy demonstrates significant effectiveness in suppressing second harmonic currents.

1. Introduction

With the gradual development of industrial power distribution systems, power quality issues have increasingly garnered attention [1]. Among various power quality problems, such as voltage flicker, sag, and harmonics, voltage sags occur most frequently and are one of the significant causes of reduced stability in electrical equipment [2,3,4]. Voltage sags can lead to the abnormal operation of numerous sensitive devices, resulting in incalculable losses [5]. With its benefits of cost-effectiveness, high efficiency, and rapid response, the dynamic voltage restorer (DVR) stands out as a compelling solution for mitigating voltage sag issues [6,7].

For medium and low power levels, as well as for ease of implementation, a single-phase two-stage scheme is adopted typically. Figure 1 illustrates the system structure of DVR, which consists of energy storage (ES), a front-stage DC-DC converter for stepping up the voltage, a rear-stage DC-AC inverter, and a large-capacity capacitor $C_{bus}$ to maintain the input voltage of the rear-stage DC-AC inverter. Finally, it is connected to the equipment or sensitive load. During DC-AC conversion, second-order pulsations in AC-side output power are also observed in the DC-side input voltage and current. Typically, the input-side voltage is controlled at a constant value, so the second-order oscillations primarily appear in the input current. Since the energy source usually consists of battery components such as lithium batteries or fuel cells, these second-order ripple currents (SRCs) reflected on the input side can cause various harmful effects. In reference [8], SRCs could induce approximately 22% additional thermal losses, leading to increased temperature in battery packs. Temperature significantly impacts both battery capacity and lifespan. References [9,10] further indicate that a 30 °C temperature rise can reduce lithium-ion battery lifespan by up to 60%. Moreover, high temperatures may trigger safety concerns in lithium-ion batteries, compromising the reliability of both the energy storage system and the DVR device. Therefore, it is essential to effectively suppress SRCs in DVR devices.

In the literature, there are both passive and active methods to suppress SRCs. Passive methods include adding capacitors and inductors to eliminate the SRC components. However, the large size of these components leads to oversized designs and high system costs. A few power decoupling thoughts are proposed for eliminating SRCs in [11,12]. Ordinary electrolytic capacitors are substituted with longer-lasting film capacitors, improving the system’s durability [13]. Additionally, the most direct way to suppress the SRCs is to increase the capacitance of the intermediate DC bus. However, high-capacity electrolytic capacitors have a shorter lifespan, which reduces the service life of devices [14,15].

The second passive method involves applying auxiliary control methods in the front-stage DC-DC converter to suppress the SRCs flowing to the input side. Earlier ripple reduction methods primarily focused on introducing an inductor current feedback loop to create dual-loop control [16]. But this approach reduces the cutoff frequency of the voltage loop, resulting in a significant overshoot on the bus voltage when the load is suddenly changed. To suppress SRCs while maintaining the system’s dynamic performance, the authors of [17,18] introduced notch filters into the voltage feedback path, while the authors of [19] incorporated bandpass filters into the current feedback path. However, both methods introduce significant negative phase shifts, which affect system stability. In [20,21], the virtual impedance method was applied to regulate the input or output impedance at specific frequencies to suppress SRCs. This approach does not require additional components and is easy to implement. In [22,23], the method of paralleling virtual impedance across the bus capacitor was proposed to decrease bus voltage overshoots during variations in the load. In [24], a control scheme with the virtual fractional-order inductance is proposed. In [25], the authors proposed a deadbeat control method to optimize the traditional PI controller. The primary control methods used in the above studies are based on single-output-side bus voltage feedback control. Compared to dual-loop control, this single voltage feedback control exhibits poorer dynamic performance and lower system robustness. In [26], the authors combined droop control, dual-loop control of bus voltage and inductor current, and a notch filter to suppress SRCs. In [27], the authors proposed a simplified model for the front-stage buck/boost converter and employed dual-loop control of bus voltage and inductor current, combined with a digital notch filter to suppress SRCs. This approach reduces control complexity, but the digital notch filter introduces phase delay and is only effective at specific frequencies. Compared to the droop control strategy and digital notch filter proposed in [26,27], the virtual impedance method is simpler to implement, more flexible, and does not require integration with other methods. At the same time, few studies have explicitly proposed combining dual-loop control with the virtual impedance method to suppress SRCs.

In this study, a method for suppressing DC-side SRCs in DVR devices is proposed. Firstly, based on the dual feedback loops (voltage and current) of the front-stage buck/boost converter, the virtual series impedance (VSI) and the virtual parallel impedance (VPI) are introduced to step up the equivalent impedance at 2f₀, which effectively suppresses SRCs. The proposed control method takes advantage of the fast, stable, and reliable characteristics of dual closed-loop control, while the virtual impedance-assisted control strategy is flexible and easy to implement. Next, the propagation mechanism of SRCs and the suppression method based on virtual impedance are described. Then, the selection of virtual impedance and the design of key parameters are introduced. Finally, a 3 kW single-phase DVR experimental prototype is built, and the results are discussed.

2. SRC Generation Mechanisms and Suppression Methods Based on Virtual Impedances

2.1. Generation and Propagation Mechanism of the SRCs

Figure 2a shows the simplified topology of the dynamic voltage restorer (DVR) mitigation device. The DC bus capacitor $C_{bus}$ connects the front-stage buck/boost converter with the rear-stage DC-AC inverter. The input side ($U_s$) is typically connected to the ES or batteries, while the output side ($u_o$) interfaces with sensitive loads through a transformer. To streamline the design and analysis process, the transformer is assumed to be ideal, and the configuration in Figure 2a can be further simplified to Figure 2b.

Under ideal conditions, $u_o$ is the output voltage of the DVR, and it is a sinusoidal wave. Its expression is:

$$u_o=U_o\sin ({\omega }_{0}t+\phi )=U_o\sin (2\pi f_{0}t+\phi ),$$

(1)

where $U_o$ is the amplitude of $u_o$. $f_0$ is the frequency of $u_o$. The output current $i_o$ is represented as

$$i_o=I_o\sin (2\pi f_{0}t+\phi ),$$

(2)

where $I_o$ is the amplitude of $i_o$. The instantaneous output power $P_o$ can be expressed as

$$\begin{array}{ll}{P}_o& =u_o{i}_o\\ & =\underset{DC}{\underbrace{{\displaystyle \frac{1}{2}}{U}_o{I}_o\cos \phi }}-\underset{AC}{\underbrace{{\displaystyle \frac{1}{2}}{U}_o{I}_o\cos (2\pi ·2f_{0}t+\phi )}}\end{array},$$

(3)

From Equation (3), it can be concluded that $P_o$ contains not only a DC part but also an AC part with a frequency of $2f_0$.

Under normal operating conditions, the DC bus voltage ripple is typically minimal and can, thus, be approximated as a constant. Furthermore, the input current $i_{dc}$ can be derived as:

$$\begin{array}{ll}{i}_{dc}& ={\displaystyle \frac{P_o}{u_{dc}}}\\ & ={\displaystyle \frac{U_o{I}_o}{2u_{dc}}}\cos \phi -{\displaystyle \frac{U_o{I}_o}{2u_{dc}}}\cos (2{\omega }_{0}t+\phi )\\ & =I_{dc}-i_{SRCs}\end{array},$$

(4)

From Equation (4), it can be observed that $i_{dc}$ contains not only a DC part $I_{dc}$ but also an AC part $i_{SRCs}$ with a frequency of $2f_0$. Consequently, the AC part $i_{SRCs}$ propagates to the DC bus, introducing a current ripple at $2f_0$ in the capacitor $C_{bus}$. Under constant input voltage conditions, the SRCs necessarily manifest within the input current $i_L$.

2.2. Suppression Method of SRCs Based on Virtual Impedance

Figure 3a gives the control scheme employing dual feedback loops (voltage and current) for the front-stage converter. $G_v\left(s\right)$ and $G_i\left(s\right)$ are PI controllers to regulate DC bus voltage $u_{dc}$ and inductor current $i_L$, respectively. $d$ is the duty cycle. $H_v(s)$ and $H_i(s)$ represent the sampling functions of $u_{dc}$ and $i_L$. The control structure after equivalent transformation is shown in Figure 3b.

Figure 4a presents the converter’s small-signal model established via state–space averaging methodology. The dominant approach of suppressing the SRCs is to increase the impedance magnitude of $Z_{bk/bst}(s)$ at $2f_0$ or to reduce the magnitude of $1/s{C}_{bus}$, the latter of which involves increasing the bus capacitor’s capacity. When the magnitude of $Z_{bk/bst}(s)$ is greater than that of $1/s{C}_{bus}$ at $2f_0$, the SRCs will flow into $C_{bus}$ rather than the input side. Therefore, the proposed methods introduce the virtual series impedance (VSI) $Z_s(s)$ in the converter’s inductive network (Figure 4b) to increase the magnitude of $Z_{bk/bst}(s)$ at $2f_0$. Concurrently, to reduce the impedance of $1/s{C}_{bus}$ at $2f_0$ and to address the fluctuation in the DC bus voltage during variations in the load, it is necessary to minimize the buck/boost converter’s closed-loop output impedance. This is achieved through the virtual parallel impedance (VPI) $Z_p(s)$ implementation detailed in Figure 4c. $Z_p(s)$ should have a low impedance at non-$2f_0$ and an open-circuit characteristic at $2f_0$. The required $Z_s(s)$ and $Z_p(s)$ are shown in Figure 5.

Figure 6a,b illustrate the virtual impedance control structure for the front-stage buck/boost converter, derived from Figure 3 and Figure 4b. By relocating the inductor current and bus voltage feedback nodes to the output terminal of the voltage regulator $G_v(s)$ and optimizing their transfer functions, the equivalent control diagrams are generated, as shown in Figure 6c,d. These configurations reveal that VSI and VPI are implemented via dedicated feedback loops for current and voltage regulation, respectively.

3. Virtual Impedance Selection and Parameter Design

In Figure 5, according to the amplitude–frequency characteristic requirements,$Z_s(s)=r_s{G}_{BPF}(s)$ is the expression of the VSI proposed in this study, where $r_s$ is a virtual resistor and $G_{BPF}(s)$ is a bandpass filter, and its expression is:

$$G_{BPF}(s)={\displaystyle \frac{s/(Q_{BPF}·{\omega }_{BPF})}{{\left(s/{\omega }_{BPF}\right)}^2+s/(Q_{BPF}·{\omega }_{BPF})+1}},$$

(5)

where $Q_{BPF}$ is the quality factor. ${\omega }_{BPF}=2\pi ·2f_0$ and $2f_0$ are the center frequency.

Figure 7 shows the Bode plot of $r_s{G}_{BPF}(s)$, and it can be seen that at $2f_0$, $r_s{G}_{BPF}(s)$ behaves as a high-magnitude resistor, while at other frequencies, the magnitude is relatively small. Due to the non-ideal reasons of an actual bandpass filter, when $f<2f_0$, it exhibits an inductive nature; when $f>2f_0$, it exhibits a capacitive nature.

In Figure 4c, let ${\widehat{u}}_s=0$ and $\widehat{d}=0$; the expression of $Z_L(s)$ after introducing $Z_s(s)=r_s{G}_{BPF}(s)$ can be obtained:

$$Z_L(s)={\displaystyle \frac{1}{{(1-d)}^2}}(r_s{G}_{BPF}(s)+sL),$$

(6)

When the virtual impedance is not introduced, the impedance of the inductor branch in the initial state is $Z_{L-initial}(s)$, and its expression is:

$$Z_{L-initial}(s)={\displaystyle \frac{sL}{{(1-d)}^2}},$$

(7)

Based on Equations (6) and (7), the Bode plots of $Z_L(s)$ and $Z_{L-initial}(s)$ can be drawn, as shown in Figure 8. It can be observed that after introducing $r_s{G}_{BPF}(s)$ into the inductor branch, the impedance magnitude of $Z_L(s)$ at $2f_0$ significantly increases, surpassing the capacitive reactance of $C_{bus}$. This effectively inhibits the propagation of second harmonic components in $i_{dc}$ of the rear-stage DC-AC inverter back to the front-stage buck/boost converter. As mentioned earlier, when $f>2f_0$, $r_s{G}_{BPF}(s)$ exhibits capacitive behavior, it causes a series resonance with $L$ at frequencies higher than $2f_0$, resulting in a downward resonance peak on the magnitude–frequency characteristic curve of $Z_L(s)$.

To decrease the impedance of $1/s{C}_{bus}$ at $2f_0$ and to minimize the fluctuation in the DC bus voltage upon variations in the load, the output impedance $Z_{o-bk/bst}$ of the converter should be as small as possible. It can be expressed as:

$$Z_{o-bk/bst}={\displaystyle \frac{Z_{o-bk/bst-open}(s)}{1+T_{v-bk/bst}(s)}},$$

(8)

where $T_{v-bk/bst}(s)$ represents the voltage regulation loop gain in the control strategy of the front-stage buck/boost converter. Thus, reducing $Z_{o-bk/bst}$ can be achieved by decreasing $Z_{o-bk/bst}$.

In Figure 4c, let ${\widehat{u}}_s=0$ and $\widehat{d}=0$; the expression of $Z_{o-bk/bst-open}(s)$ after introducing them can be obtained:

$$Z_{o-bk/bst-open}(s)=Z_L(s)//Z_p(s)//Z_C(s),$$

(9)

For any inductive-resistive parallel network, its parallel impedance can be represented in the form of an inductor’s reactance in series with a low-pass filter. Hence, Equation (9) can be simplified as:

$$Z_{o-bk/bst-open}(s)=(Z_L(s)·G_{LPF}(s))//Z_C(s),$$

(10)

To minimize the magnitude of $Z_{o-bk/bst-open}\left(s\right)$ as much as possible, the cutoff frequency of $G_{LPF}(s)$ must be low and far from $2f_0$. At the same time, to preserve the buck/boost converter’s output impedance at $2f_0$, $G_N(s)$, with a center frequency of $2f_0$, must be introduced into $G_{LPF}(s)$. Therefore, the expression of $G_{LPF}(s)$ is:

$$G_{LPF}(s)={\displaystyle \frac{{\omega }_{LPF}}{{\omega }_{LPF}+s·G_N(s)}},$$

(11)

where ${\omega }_{LPF}$ is the cutoff frequency of $G_{LPF}(s)$, and it satisfies:

$${\omega }_{LPF}\ll 2\pi ·2f_0,$$

(12)

The expression of $G_N(s)$ is:

$$G_N(s)={\displaystyle \frac{{(s/{\omega }_N)}^2+1}{{(s/{\omega }_N)}^2+s/(Q_N·{\omega }_N)+1}},$$

(13)

where $Q_N$ is the quality factor, and ${\omega }_N=2\pi ·2f_0$.

By substituting Equation (6) into (9)–(11), the following can be obtained:

$$Z_p(s)={\displaystyle \frac{sL+r_s{G}_{BPF}(s)}{{(1-d)}^2}}·{\displaystyle \frac{{\omega }_{LPF}}{s{G}_N(s)}},$$

(14)

After introducing $Z_s(s)=r_s{G}_{BPF}(s)$, at $2f_0$, we have:

$$\begin{array}{ll}\left|Z_L(j2\pi ·2f_0)\right|& =\left|{\displaystyle \frac{(j2\pi ·2f_0·L+r_s)}{{(1-d)}^2}}\right|\\ & \gg \left|Z_C(j2\pi ·2f_0)\right|={\displaystyle \frac{1}{2\pi ·2f_0·C_{bus}}}\end{array},$$

(15)

The inductive reactance of $L$ at $2f_0$ is much smaller than $r_s$; so, from Equation (15), we can obtain:

$$\left|{\displaystyle \frac{(j2\pi ·2f_0·L+r_s)}{{(1-d)}^2}}\right|\approx \left|{\displaystyle \frac{r_s}{{(1-d)}^2}}\right|\gg {\displaystyle \frac{1}{2\pi ·2f_0·C_{bus}}},$$

(16)

Further, it yields:

$${\displaystyle \frac{{(1-d)}^2}{r_s{C}_{bus}}}\ll 2\pi ·2f_0,$$

(17)

According to Equations (12) and (17), ${\omega }_{LPF}$ can be taken as ${(1-d)}^2/r_s{C}_{bus}$. Substituting this into Equation (13), we have:

$$Z_p(s)={\displaystyle \frac{sL+r_s{G}_{BPF}(s)}{s·r_s{C}_{bus}·G_N(s)}},$$

(18)

Based on Thevenin’s theory, the front-stage buck/boost converter can be modeled as a two-port network and equivalently represented by a voltage source in series with an impedance. Furthermore, when higher-order harmonic components are neglected, load and the rear-stage single-phase DC/AC inverter can be equivalently substituted with a purely resistive load. The simplified equivalent representation is shown in Figure 9.

To obtain $Z_{eq}(s)$, $U_s$ and $V_{ref}$ in Figure 6c,d are set to zero. The control structure of the front-stage converter with $i_{dc}$ as the input variable is shown in Figure 10. The equivalent impedance $1/Z_{eq}$ of the converter is represented in the red dashed box. When only VSI is introduced, the equivalent admittance is $1/Z_{eq1}(s)$, and when VSI and VPI are introduced, the equivalent admittance is $1/Z_{eq2}(s)$. The expressions for both are:

$${\displaystyle \frac{1}{Z_{eq1}}}={\displaystyle \frac{(1-d)G_v(s)H_v(s)G_i(s)K_{PWM}{U}_{dc}}{sL+Z_s(s)+G_i(s)H_i(s)K_{PWM}{U}_{dc}}},$$

(19)

$${\displaystyle \frac{1}{Z_{eq2}}}={\displaystyle \frac{(1-d)G_v(s)G_i(s)K_{PWM}{U}_{dc}}{sL+Z_s(s)+G_i(s)H_i(s)K_{PWM}{U}_{dc}}}+{\displaystyle \frac{1}{Z_p(s)}},$$

(20)

Therefore, the equivalent output impedance $Z_{dc}$ of the bus capacitor and front-stage buck/boost converter is given as:

$$Z_{dc}(s)=Z_{eq}(s)//{\displaystyle \frac{1}{s{C}_{bus}}},$$

(21)

In order to balance the system’s dynamic performance, the magnitude of $Z_{eq}(s)$ should be large at $2f_0$, while it should be as small as possible at non-$2f_0$. $Z_{dc}$ will be lower as $Z_{eq}$ decreases, thereby reducing the fluctuation in the DC bus voltage $u_{dc}$.

$Z_{dc}(s)$ can be adjusted by modifying $G_v(s)$. $G_v(s)$ is a PI controller, and its expression is:

$$G_v(s)=k_{pv}+{\displaystyle \frac{k_{iv}}{s}},$$

(22)

It is reasonable to change $Z_{eq}(s)$ by adjusting $k_{pv}$ while keeping $k_{iv}$ fixed. This is because $k_{pv}$ has a more significant contribution to the magnitude of $Z_{eq}(s)$ compared to $k_{iv}$. After introducing VSI, the open-loop transfer function $T(s)$ can be expressed as:

$$\begin{array}{ll}T(s)& ={\displaystyle \frac{1}{Z_{eq1}(s)}}·{\displaystyle \frac{1}{s{C}_{bus}}}\\ & ={\displaystyle \frac{(1-d)G_v(s)H_v(s)G_i(s)K_{PWM}{U}_{dc}}{sL+Z_s(s)+G_i(s)H_i(s)K_{PWM}{U}_{dc}}}·{\displaystyle \frac{1}{s{C}_{bus}}}\end{array}$$

(23)

In Figure 11, the bandwidth and cutoff frequency of $T(s)$ exhibit a positive correlation with $k_{pv}$. Additionally, a Nyquist diagram of $T(s)$ is shown in Figure 12, and it can be observed that the phase margin (PM) decreases as $k_{pv}$ increases. When $k_{pv}$ is 0.5, the PM is 52.4 deg, while when $k_{pv}$ is 5, the PM is 20.8 deg. To meet general engineering requirements while considering bandwidth, $k_{pv}$ can be set to 1, at which point $PM=45.6\mathrm{deg}$.

When VSI and VPI are introduced, the equivalent impedance of the converter $Z_{eq}$ is shown in Figure 13, and it is illustrated that while the equivalent impedance $Z_{eq}$ at $2f_0$ increases, the impedance at non-$2f_0$ is reduced. This effectively mitigates the SRCs while also reducing the fluctuation in the DC bus voltage upon variations in the load.

4. Results Analysis

4.1. Simulation Results

A simulation model of the DVR voltage sag mitigation system is built in MATLAB R2024a based on the parameters in

Table 1. Main parameters of simulation and prototype.

	Parameters	Specifications
Buck/Boost Converter	Ubat/V	200
	fs/kHz	10
	L/mH	0.5
	Cbus/mF	1.36
Single-phase Inverter	Uac/V	311
	f0/Hz	50
	Lf/mH	4
	Cf/mF	0.13
	Switching Frequency/kHz	10
Virtual impedance	rs	200
	QBPF	2
	QN	2
PI controller	kpv	1
	kiv	10
	kpi	5
	kii	20

. The simulation results are shown in Figure 14, Figure 15 and Figure 16.

Figure 14 presents the main waveforms under conventional dual feedback loop (voltage and current) control in steady state. $u_o$ and $i_o$ are the output voltage and current of the system, $u_{dc}$ is the bus capacitor voltage, and $i_L$ is the input-side inductor current. Both $u_o$ and $i_o$ are sinusoidal waveforms at a frequency of 50 Hz, but the frequency of $i_L$ is clearly twice that of $u_o$ and $i_o$. This indicates that there is a 100 Hz harmonic current component present in $i_L$.

Figure 15 and Figure 16 show the key waveforms after introducing the virtual impedance methods proposed in this study. It is clearly seen that the SRCs in $i_L$ are greatly reduced and have become a smooth DC waveform.

Table 2. FFT results of $i_L$ with different methods.

Methods	Without Virtual Impedance	Reference [27]	With VSI	With VSI and VPI
Average of $i_L$/A	15.69	15.43	15.68	15.27
Percentage of second-order ripple current	31.72%	2.894%	1.04%	1.07%
Percentage of fourth-order ripple current	0.22%	\	0.13%	1.16%

provides the results of the FFT analysis of the input-side inductor current $i_L$ for the three control strategies. When only VSI is introduced, the percentage of SRCs relative to the average value decreases from 31.72% to 1.04%. When VSI and VPI are introduced, the percentage of SRCs relative to the average value is 1.07%. When using the method proposed in reference [24], the percentage of SRCs relative to the average value is 2.894%. These results demonstrate that most of the SRCs have been effectively suppressed. Furthermore, compared to the suppression method in [24], the proposed methods demonstrate better performance in suppressing the SRCs.

However, compared to the conventional dual feedback loop (voltage and current) control strategy and the proposed control strategy with VSI, the proposed control strategy with VSI and VPI increases the fourth harmonic content. The percentage of the fourth harmonic relative to the average value increases from 0.22% and 0.19% to 1.16%. This phenomenon is related to the equivalent impedance $Z_{eq}(s)$ of the front-stage buck/boost converter after the introduction of the parallel impedance. Figure 13 shows $Z_{eq}(s)$ after introducing both types of virtual impedance. In the case where VSI and VPI are introduced, a downward resonance peak is observed at $4f_0$ in the amplitude–frequency characteristic curve. It is preliminarily speculated that this peak at $4f_0$ leads to an increase in the fourth harmonic content in the input current $i_L$.

4.2. Experimental Verification

A 3 kW dynamic voltage restorer experimental prototype was designed and fabricated in the laboratory based on the main parameters in Table 1. The DSP TMS320F82335 is used as the main controller.

The load is purely resistive. Figure 17 and Figure 18 show the key voltage and current waveforms of the DVR system under full load conditions. Both $u_o$ and $i_o$ are sinusoidal waveforms at a power frequency of 50 Hz. The voltage and current waveforms before compensation are shown in Figure 17. Before compensation, the frequency of $i_L$ is clearly twice that of $u_o$ and $i_o$, indicating the presence of significant second-order harmonic components in it. The key waveforms under the proposed methods in this study are shown in Figure 18, where $i_L$ becomes a smooth DC waveform, and the SRCs are effectively suppressed. The peak ripple of $i_L$ decreases from 5.9 A to 1.2 A and from 5.9 A to 1.1 A, while the ripple factor of $i_L$ decreases from 37.6% to 7.66% and 7.2%, respectively. The experimental results obtained well validate the rationality and correctness of Equations (5)–(18).

The input current $i_L$ data obtained from the oscilloscope are imported into MATLAB R2024a’s FFT toolbox for harmonic content analysis. The results are shown in

Table 3. FFT analysis results of $i_L$ with different methods.

Methods	Without Virtual Impedance	Reference [27]	With VSI	With VSI and VPI
Average of $i_L$/A	15.32	15.31	15.21	15.14
Percentage of second-order ripple current	39.64%	2.11%	1.74%	1.78%
Percentage of fourth-order ripple current	0.54%	\	0.64%	1.62%

. The DC components of the three methods are similar to the average values of $i_L$ read from the oscilloscope. When using the method proposed in [24], the percentage of SRCs relative to the average value is 2.11%. After introducing virtual impedance, the secondary ripple content in $i_L$ is significantly reduced, with the percentage of SRCs decreasing from 39.64% to 1.74% and 1.78% and the secondary harmonic content being less than 2%. There are still minor fluctuations in the waveform, which are caused by parasitic inductance, parasitic capacitance, and noise in the circuits.

However, when VSI and VPI are introduced simultaneously, the fourth harmonic content increases, which aligns with the conclusions derived from the simulation. The percentage of the fourth harmonic relative to the average value increases from 0.54% and 0.64% to 1.62%. This phenomenon occurs due to a downward peak in the frequency response of the front-stage buck/boost converter’s equivalent impedance at $4f_0$ when VSI and VPI are applied, resulting in resonance at $4f_0$ in the input current.

5. Conclusions

In response to the double-frequency ripple phenomenon observed in existing two-stage single-phase DVR voltage sag mitigation devices, this study introduces the VSI and VPI methods to suppress SRCs, based on the dual feedback loop (voltage and current) control strategy of the front-stage buck/boost converter. The virtual impedances can be realized in the current and voltage sampling loops through equivalent transformation. Compared to existing schemes, the proposed methods offer the advantages of being fast, stable, and reliable, while the virtual impedance auxiliary control strategy is flexible and simple to implement. The feasibility and stability of this strategy were verified using a 3 kW DVR prototype. When applying the two virtual impedance methods, the second harmonic content was reduced from 39.64% to 1.74% and 1.78%, respectively. However, after introducing VSI and VPI, the fourth harmonic content in the input current $i_L$ increased. This may be due to a downward resonance peak in the equivalent impedance of the buck/boost converter at $4f_0$ caused by the introduction of VSI and VPI.

The current work still has certain limitations, which will be key focuses for future research:

(1)

The fundamental mechanism behind the increased fourth harmonic content in the input current $i_L$ after introducing VSI and VPI requires further investigation. This study only proposed a possible explanation, which remains unverified.

(2)

In real-world applications, DVRs typically encounter complex conditions, such as grid harmonics, nonlinear loads, and load surges, which may limit the effectiveness of virtual impedance. It is necessary to adjust the virtual impedance parameters according to the impedance characteristics of different actual circuits.

(3)

Practical applications involve numerous uncertainties and variable conditions. Ensuring and improving the reliability and operational efficiency of DVRs under real-world operating scenarios are highly worthy of research. In subsequent studies, the risk aversion and distributed optimization methods from reference [28] can serve as important guidance.

(4)

In the practical application and promotion of DVRs, the cost, lifespan, and reliability of energy storage devices are major concerns for end-users. Reducing investment costs and extending service life to expand DVR adoption will be key research priorities. The shared energy storage service and optimal configuration methods proposed in reference [29] can effectively address these needs and provide critical guidance for our future work.