Grid-Connected Renewable Energy Sources: A New Approach for Phase-Locked Loop with DC-Offset Removal

Abstract

Renewable Energy Sources (RES) are widely used worldwide due to their positive effect on the environment, being sustainable, low cost, and controllable. The power generated from RESs must be configured to interface and perfectly synchronize with the grid by using Power Electronics Converters (PEC). A Phase-Locked Loop (PLL) is one of the most popular synchronization techniques used due to its speed and robustness. A growing issue that results in oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude is the DC-offset in the input of the PLL. This study was developed to eliminate the DC-offset in the single-phase grid synchronization using Delay Signal Cancellation (DSC) and a fixed-length Transfer Delay (TD)-based PLL. Then, the small-signal model, stability analysis, and selection of controller gains were discussed. The proposed PLL was simulated using MATLAB/Simulink. Moreover, to evaluate the proposed method, several scenarios were developed in order to compare it with other powerful PLLs in terms of performance indicators such as settling time, frequency, and phase error. As a result, the proposed PLL has the fastest dynamic response, completely rejects the DC-offset effect, and fully synchronizes with the electrical grid.

1. Introduction

Renewable Energy Sources (RES) such as wind energy, solar energy, and hydro energy are widely used due to their positive effects on the environment, being sustainable, low cost, and controllable [1]. According to the International Energy Agency (IEA), the world generated about 20% of its total energy in 2010 from RESs, and the total generation in 2020 from RESs is 28% [2]. This is a positive indicator that the world is moving steadily to make the most of sustainable resources.

The power generated from RESs must be shaped in order to be interfaced with the grid by employing Power Electronics Converters (PEC) [3]. In grid-connected RES systems, the most popular synchronization technique is based on Phase-Locked Loops, (PLL) which synchronize the output power from the PEC with the electrical grid [4,5,6,7,8].

The Synchronous Reference Frame (SRF) PLL is one of the most popular PLLs. SRF-PLLs have three main parts. The first is the Phase Detector (PD), which generates a phase error signal, i.e., a signal that contains the error between actual and estimated phases.

The second and third parts of SRF-PLLs are the Loop Filter (LF) and the Voltage-Controlled Oscillator (VCO) [8]. The LF is a Proportional Integrator (PI) controller that is mainly responsible for suppressing disturbances inside the PLL control loop. The output from the LF moves through VCO to estimate the grid phase under any conditions.

To properly match the grid synchronization, problems caused by the presence of DC-offset in the PLL’s input must be overcome. The existence of oscillations in the estimated fundamental frequency, phase, and amplitude is only one of many difficulties. However, the stability of the closed-loop system can be compromised. The DC-offset in grid-connected PECs can be caused by a variety of factors, including the usage of A/D conversions, digital controllers, the use of control algorithms in microcontrollers, sensor offsets, geomagnetic events, and grid failures [4,9,10,11,12,13,14].

In general, single-phase PLLs are more difficult to construct than three-phase PLLs because of the way to generate orthogonal signals are generated in the PD part of the PLL. Many techniques have been proposed in order to generate the orthogonal signal in the single-phase PLL [15,16,17,18,19,20].

In ref. [16], the authors conducted a comprehensive comparison of seven orthogonal signal generator structures, considering five assessment criteria. Their analysis revealed that Transfer Delay (TD) and all-pass filters are the simplest approaches to generating an orthogonal signal. However, the Hilbert Transform (HT) and Complex Coefficient Filter (CCF) are more complicated due to the additional compensation structure required. Inverse park transformation, Second-Order Generalized Integrator (SOGI), and CCF exhibit inherent filtering characteristics and offer better steady-state accuracy. In contrast, TD requires lower filter design criteria.

To solve the DC-offset effect in the PLL’s input, the authors in [9] proposed a novel PLL architecture that comprises three key components: a filter-based Fundamental Positive Sequence Component Separator (FPSCS), an SRF-PLL, and a Secondary Control Path (SCP). The FPSCS module employs a Sliding Goertzel Discrete Fourier Transform (SGDFT) filter and the symmetrical component method to accurately isolate the FPSC, even in the presence of distortion. Additionally, the FPSCS part can remove the effect of the DC-offset in the PLL inputs.

The authors in [4] employed a DC-immune operator as a straightforward and efficient method to eliminate the influence of DC-offset on a three-phase PLL input. Additionally, they incorporated a phase error compensator to eliminate the phase shift effect in the PLL’s output.

In ref. [13], the authors introduced an innovative method known as Enhanced Delayed Signal Cancellation (EDSC) for integrating distributed RESs into the power grid, which can be seamlessly integrated into a conventional Cascaded Delayed Signal Cancellation (CDSC) PLL, enabling it to function as a reliable grid synchronization tool for grid-connected converters and to remove the effect of the DC-offset. The approach demonstrates the capability of estimating both positive and negative sequences of the fundamental frequency, ensuring a fast settling time and significantly enhancing the synchronization process. However, it is essential to note that this method does not incorporate any representation of the small-signal model.

Another investigation presented various techniques for rejecting DC-offset in three-phase grid synchronizations [12]. These approaches encompass PLLs that utilize Delayed Signal Cancellation (DSC) operators within dq and αβ reference frames.

In ref. [21], the authors proposed applying the Modified Delayed Signal Cancelation (MDSC) operator in the dq reference frame to reject the DC-offset effect, regardless of the delay factor selection.

For single-phase grid synchronization, Golestan et al. (2019) proposed PLLs based on adaptive and non-adoptive CDSC [22]. Each DSC operator can reject disturbances in a particular way. A delay length equal to one-half of the fundamental grid period was employed for DC-offset reduction. Moreover, the Orthogonal Signal Generation (OSG) required for $dq$ transformation was created by delaying the initial single-phase signal by 90°, and the orthogonal signal is produced.

In [23], a closed-loop control two-phase generator was integrated into the SRF-PLL to eliminate DC-offset. The method involves computing the difference between the input and the extracted α-axis component, then passing it through an integrator. Finally, the output representing the input DC component was subtracted from the input signal.

In ref. [24], a frequency-fixed Cascaded Generalized Integrator (CGI) PLL was proposed to eliminate the DC-offset in the PLL’s input. The α-axis output of the first SOGI block serves as input for the second SOGI block. The αβ-axis outputs of the second SOGI block were fed to the embedded SRF-PLL. However, the dynamic response and harmonic attenuation capability of the SRF-PLL were influenced by its bandwidth.

The literature on PLL analysis in single-phase grid-connected systems has explored various techniques to enhance the accuracy and stability of the system. One such technique, presented in [11], involves using a Third-Order Generalized Integrator (TOGI) to construct an alpha and beta static coordinate system. This method depends on a virtual orthogonal voltage vector approach that eliminates DC-offset in a voltage signal or zero offset in the sampling process while maintaining consistent signal amplitude. The authors also introduced an adaptive frequency estimation unit to tackle changes in the power grid voltage frequency, thereby ensuring PLL accuracy.

In ref. [10], an improved single-phase Fixed-Frequency PLL (FFPLL) based on the SOGI filter was proposed. This method utilizes the fixed-frequency SOGI filter to effectively eliminate the impact of DC-offset in various ways.

In ref. [14], the authors introduced a novel structure called the Novel Second-Order Generalized Integrator (NSOGI) and a modified version of the NSOGI that includes DC-offset rejection capability.

This study suggests a τ delay time to create a straightforward technique for DC-offset rejection that is not constrained to any particular time delay; this will provide the proposed PLL more flexibility than the PLLs discussed above. The mathematical representation, the small-signal model, and the design of the PI controller’s gains were developed in this work. To evaluate the effectiveness of the proposed PLL, a comparison with existing PLLs was carried out through several scenarios taking into account some indicators such as phase error, estimated frequency, and settling time.

The rest of this paper is organized as follows: Section 2 outlines the methodology. Section 3 presents the fundamental concept, the mathematical representation, the analysis of the small-signal model, the design of the controller gains, and a comparison of the real-time and small-signal models for the proposed PLL. In Section 4, a comparison is made between the proposed PLL and other powerful PLLs using MATLAB/Simulink. Finally, Section 5 concludes with the conclusions.

2. Methodology

A simple and effective method for grid synchronization is proposed. In addition, the proposed method is capable of completely rejecting the DC-offset. Several steps were taken to achieve the objectives of the study:

• Description of the suggested method’s block diagram and real-time mathematical model analysis;
• Mathematically determining the structure of the proposed method’s small-signal model;
• Designing and building a small-signal model’s closed-loop transfer function;
• Utilizing a closed-loop transfer function to calculate the PI controller’s gain;
• Checking the accuracy of the small-signal model;
• Compare the proposed method with other robust methods to evaluate the proposed PLL through several scenarios.

The methodology consists of six main points. Each of these points is discussed in-depth to provide a comprehensive understanding of the research process, with a clear explanation of the steps taken to carry out this study and to ensure that the methodology is transparent.

3. Development

3.1. Proposed PLL

The proposed PLL was created based on TD and DSC operators. Figure 1 presents the real-time block diagram for the proposed PLL. To analyze the system mathematically, the analysis starts with the input signals. Assume that the grid voltage can be represented as:

$$v_a=v_{\alpha }=Vsin\left(\theta \right)+v_a^{dc}$$

(1)

where $v_{\alpha }$ is the alpha signal in the $\alpha \beta$-reference frame, $\theta ={\omega }_{g}t+\phi$ is the grid-phase, $V$ is the grid-amplitude, ${\omega }_g$ is the grid-frequency, φ is the initial phase angle, and $v_a^{dc}$ is the DC component in the input voltage $v_a$.

According to Figure 1, the orthogonal signal ($v_{\beta }$) can be written as:

$$v_{\beta }=Vsin\left(\theta -\frac{{\omega }_{g}T}{4}\right)+v_a^{dc}=-Vcos\left(\theta -\frac{\Delta {\omega }_{g}T}{4}\right)+v_a^{dc}$$

(2)

where T is the time period, ${\omega }_g={\omega }_n+\Delta {\omega }_g$, and ${\omega }_n$ is the nominal grid frequency. The components of the $\alpha \beta$ voltages in Equations (1) and (2) that are delayed can be represented as follows:

$$\left[\begin{array}{c}\Delta v_{\alpha }\\ \Delta v_{\beta }\end{array}\right]=V\left[\begin{array}{c}sin\left(\theta \right)-sin\left(\theta -{\omega }_g\tau \right)\\ -cos\left(\theta -\frac{\Delta {\omega }_{g}T}{4}\right)+cos\left(\theta -\frac{\Delta {\omega }_{g}T}{4}-{\omega }_g\tau \right)\end{array}\right]+\left[\begin{array}{c}{v}_a^{dc}\\ v_a^{dc}\end{array}\right]$$

(3)

where the time delay is expressed in seconds by the symbol τ. The $\alpha \beta$ signals are deducted from the delayed version of the signals in the following manner to eliminate the DC-offset:

$$\left[\begin{array}{c}\mathsf{\Delta }{v}_{\alpha }\\ \mathsf{\Delta }{v}_{\beta }\end{array}\right]=\left[\begin{array}{c}{v}_{\alpha }\left(t\right)-v_{\alpha }\left(t-\tau \right)\\ v_{\beta }\left(t\right)-v_{\beta }\left(t-\tau \right)\end{array}\right]$$

(4)

According to Figure 1, by employing ${\theta }_0=-\frac{{\omega }_g\tau }{2}$, the adopted phase correction ${\theta }_0$ is the actual phase delay caused by utilizing the time delay to cancel the DC-offset in the PLL, and the orthogonal signal $\acute{\Delta v_{\beta }}$ is developed to solve the oscillation problem under off-nominal frequency:

$$\acute{\Delta v_{\beta }}=\frac{V\left[-cos\left(\theta -\frac{\Delta {\omega }_{g}T}{4}\right)+cos\left(\theta -\frac{\Delta {\omega }_{g}T}{4}-{\omega }_g\tau \right)\right]-\widehat{V}\left[sin\left(\widehat{\theta }-{\widehat{\omega }}_g\tau \right)+sin\left(\widehat{\theta }\right)\right]sin\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}{cos\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}$$

(5)

Figure 1 shows the proposed PLL. This approach is called a single-phase, non-adaptive DC-immune PLL (non-adaptive DCI PLL). $v_q$ can be written as:

$$v_q=-sin\left(\theta -\frac{{\omega }_g\tau }{2}\right)\Delta v_{\alpha }+cos\left(\theta -\frac{{\omega }_g\tau }{2}\right)\acute{\Delta v_{\beta }}$$

(6)

where $\widehat{⬚}$ is the estimated signal. At synchronization $V\approx \widehat{V}$ and $\Delta {\omega }_g\approx \Delta {\widehat{\omega }}_g$ yield $v_q=0$. This indicates that $v_q$ is controlled and the error signal is equal to zero. For that, it is necessary to discuss closed-loop stability and create a voltage controller that will regulate the q-axis voltage $v_q$ to zero. The PLL small-signal model is typically used to evolve the PI controller as the voltage controller.

3.2. Small-Signal Model

This section focuses on deriving a small-signal model for the proposed single-phase, non-adaptive DCI PLL. The estimated voltage $v_q$ can be represented as:

$$v_q=-sin\left(\widehat{\theta }-\frac{{\widehat{\omega }}_g\tau }{2}\right)\Delta v_{\alpha }+cos\left(\widehat{\theta }-\frac{{\widehat{\omega }}_g\tau }{2}\right)\acute{\Delta v_{\beta }}$$

(7)

$$v_q=\left\{\begin{array}{c}-Vsin\left(\widehat{\theta }-\frac{{\widehat{\omega }}_g\tau }{2}\right)\left[sin\left(\theta \right)-sin\left(\theta -{\omega }_g\tau \right)\right]\\ +cos\left(\widehat{\theta }-\frac{{\widehat{\omega }}_g\tau }{2}\right)\left[\frac{V\left[-cos\left(\theta -\frac{\Delta {\omega }_{g}T}{4}\right)+cos\left(\theta -\frac{\Delta {\omega }_{g}T}{4}-{\omega }_g\tau \right)\right]-\widehat{V}\left[sin\left(\widehat{\theta }-{\widehat{\omega }}_g\tau \right)+sin\left(\widehat{\theta }\right)\right]sin\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}{cos\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}\right]\end{array}\right\}$$

(8)

$$\frac{v_q}{V}=\frac{1}{2}\left\{\begin{array}{c}\left\{\begin{array}{c}\left[\mathit{c}\mathit{o}\mathit{s}\left(\mathit{\theta }+\widehat{\mathit{\theta }}-\frac{{\widehat{\mathit{\omega }}}_{\mathit{g}}\mathit{\tau }}{\mathbf{2}}\right)-cos\left(\theta -\widehat{\theta }+\frac{{\widehat{\omega }}_g\tau }{2}\right)\right]+\\ \frac{\left[-cos\left(\mathit{\theta }+\widehat{\mathit{\theta }}-\frac{{\widehat{\mathit{\omega }}}_{\mathit{g}}\mathit{\tau }}{\mathbf{2}}-\frac{\Delta {\mathit{\omega }}_{\mathit{g}}\mathit{T}}{\mathbf{4}}\right)-cos\left(\theta -\widehat{\theta }+\frac{{\widehat{\omega }}_g\tau }{2}-\frac{\Delta {\omega }_{g}T}{4}\right)\right]}{cos\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}+\\ tan\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)\left[\mathit{s}\mathit{i}\mathit{n}\left(\mathbf{2}\widehat{\mathit{\theta }}-\frac{{\widehat{\mathit{\omega }}}_{\mathit{g}}\mathit{\tau }}{\mathbf{2}}\right)+sin\left(\frac{{\widehat{\omega }}_g\tau }{2}\right)\right]\end{array}\right\}\\ +\left\{\begin{array}{c}\left[cos\left(\theta -\widehat{\theta }-{\omega }_g\tau +\frac{{\widehat{\omega }}_g\tau }{2}\right)-\mathit{c}\mathit{o}\mathit{s}\left(\mathit{\theta }+\widehat{\mathit{\theta }}-{\mathit{\omega }}_{\mathit{g}}\mathit{\tau }-\frac{{\widehat{\mathit{\omega }}}_{\mathit{g}}\mathit{\tau }}{\mathbf{2}}\right)\right]+\\ \frac{\left[cos\left(\mathit{\theta }+\widehat{\mathit{\theta }}-{\mathit{\omega }}_{\mathit{g}}\mathit{\tau }-\frac{{\widehat{\mathit{\omega }}}_{\mathit{g}}\mathit{\tau }}{\mathbf{2}}-\frac{\Delta {\mathit{\omega }}_{\mathit{g}}\mathit{T}}{\mathbf{4}}\right)+cos\left(\theta -\widehat{\theta }-{\omega }_g\tau +\frac{{\widehat{\omega }}_g\tau }{2}-\frac{\Delta {\omega }_{g}T}{4}\right)\right]}{cos\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}+\\ tan\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)\left[\mathit{s}\mathit{i}\mathit{n}\left(\mathbf{2}\widehat{\mathit{\theta }}-\frac{\mathbf{3}{\widehat{\mathit{\omega }}}_{\mathit{g}}\mathit{\tau }}{\mathbf{2}}\right)+sin\left(\frac{{\widehat{\omega }}_g\tau }{2}-{\widehat{\omega }}_g\tau \right)\right]\end{array}\right\}\end{array}\right\}$$

(9)

In Equation (9), the double frequency terms written in the bold line will cancel one another out near the synchronization condition.

$$v_q=\frac{1}{2}\left\{\begin{array}{c}cos\left(\theta -\widehat{\theta }-{\omega }_g\tau +\frac{{\widehat{\omega }}_g\tau }{2}\right)-cos\left(\theta -\widehat{\theta }+\frac{{\widehat{\omega }}_g\tau }{2}\right)\\ +\frac{cos\left(\theta -\widehat{\theta }-{\omega }_g\tau +\frac{{\widehat{\omega }}_g\tau }{2}-\frac{\Delta {\omega }_{g}T}{4}\right)-cos\left(\theta -\widehat{\theta }+\frac{{\widehat{\omega }}_g\tau }{2}-\frac{\Delta {\omega }_{g}T}{4}\right)}{cos\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}\\ +tan\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)sin\left(\frac{{\widehat{\omega }}_g\tau }{2}\right)+tan\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)sin\left(\frac{{\widehat{\omega }}_g\tau }{2}\right)\end{array}\right\}$$

(10)

By using trigonometric identities to Equation (10), $v_q$ can be written as:

$$v_q=\left\{\begin{array}{c}sin\left(\frac{{\omega }_g\tau }{2}\right)\left[sin\left(\theta -\widehat{\theta }-\frac{\tau }{2}\left({\omega }_g-{\widehat{\omega }}_g\right)\right)+\frac{sin\left(\theta -\widehat{\theta }-\frac{\tau }{2}\left({\omega }_g-{\widehat{\omega }}_g\right)-\frac{\Delta {\omega }_{g}T}{4}\right)}{cos\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)}\right]\\ +tan\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)sin\left(\frac{{\widehat{\omega }}_g\tau }{2}\right)\end{array}\right\}$$

(11)

It is necessary to know that $\theta ={\theta }_n+\Delta \theta$, $\widehat{\theta }={\theta }_n+\Delta \widehat{\theta }$, and ${\widehat{\omega }}_g={\omega }_n+\Delta {\widehat{\omega }}_g$. To evaluate the small-signal model, the following approximation is applicable:

$$sin\left(\Delta \theta -\Delta \widehat{\theta }-\frac{\tau }{2}\left(\Delta {\omega }_g-\Delta {\widehat{\omega }}_g\right)-\frac{\Delta {\omega }_{g}T}{4}\right)=\Delta \theta -\Delta \widehat{\theta }-\frac{\tau }{2}\left(\Delta {\omega }_g-\Delta {\widehat{\omega }}_g\right)-\frac{\Delta {\omega }_{g}T}{4}$$

(12)

$$sin\left(\Delta \theta -\Delta \widehat{\theta }-\frac{\tau }{2}\left(\Delta {\omega }_g-\Delta {\widehat{\omega }}_g\right)\right)=\Delta \theta -\Delta \widehat{\theta }-\frac{\tau }{2}\left(\Delta {\omega }_g-\Delta {\widehat{\omega }}_g\right)$$

(13)

$$tan\left(\frac{\Delta {\widehat{\omega }}_{g}T}{4}\right)=\frac{\Delta {\widehat{\omega }}_{g}T}{4}$$

(14)

In addition, $sin\left(\frac{{\omega }_g\tau }{2}\right)$ and $sin\left(\frac{{\widehat{\omega }}_g\tau }{2}\right)$ can simplified in the small-signal analysis as follows:

$$sin\left(\frac{{\omega }_g\tau }{2}\right)=sin\left(\frac{{\omega }_n\tau }{2}+\frac{\Delta {\omega }_g\tau }{2}\right)=sin\left(\frac{{\omega }_n\tau }{2}\right)cos\left(\frac{\Delta {\omega }_g\tau }{2}\right)+cos\left(\frac{{\omega }_n\tau }{2}\right)sin\left(\frac{\Delta {\omega }_g\tau }{2}\right)$$

(15)

$$sin\left(\frac{{\widehat{\omega }}_g\tau }{2}\right)=sin\left(\frac{{\omega }_n\tau }{2}+\frac{\Delta {\widehat{\omega }}_g\tau }{2}\right)=sin\left(\frac{{\omega }_n\tau }{2}\right)cos\left(\frac{\Delta {\widehat{\omega }}_g\tau }{2}\right)+cos\left(\frac{{\omega }_n\tau }{2}\right)sin\left(\frac{\Delta {\widehat{\omega }}_g\tau }{2}\right)$$

(16)

$$cos\left(\frac{\Delta {\omega }_g\tau }{2}\right)\approx 1, \mathrm{and} sin\left(\frac{\Delta {\omega }_g\tau }{2}\right)\approx \frac{\Delta {\omega }_g\tau }{2}$$

(17)

Applying the above approximations to Equation (11) yields:

$$v_q\left(t\right)\approx 2Vsin\left(\frac{{\omega }_n\tau }{2}\right)\left[\frac{\Delta \theta +\Delta \theta -\left(\tau +\frac{T}{4}\right)\Delta {\omega }_g}{2}-\Delta \widehat{\theta }+\left(\frac{\tau }{2}+\frac{T}{8}\right)\Delta {\widehat{\omega }}_g\right]$$

(18)

Taking the Laplace transform to Equation (18) yields:

$$v_q\left(s\right)\approx k_l\left[\frac{1+e^{-\left(\tau +\frac{T}{4}\right)s}}{2}\Delta \theta \left(s\right)-\Delta \widehat{\theta }\left(s\right)+\left(\frac{4\tau +T}{8}\right)\Delta {\widehat{\omega }}_g\left(s\right)\right]$$

(19)

where $k_l=2Vsin\left(\frac{{\omega }_n\tau }{2}\right)>0$.

According to Equation (19) and Figure 1, the small-signal model for the proposed non-adaptive DCI PLL is shown in Figure 2.

According to Figure 2, the closed-loop transfer function can be represented as:

$${\mathit{G}}_{\mathit{c}\mathit{l}}\left(\mathit{s}\right)=\frac{\Delta \widehat{\mathit{\theta }}}{\Delta \mathit{\theta }}=\frac{\mathbf{1}+{\mathit{e}}^{-\left(\mathit{\tau }+\frac{\mathit{T}}{\mathbf{4}}\right)\mathit{s}}}{\mathbf{2}}\frac{{\mathit{k}}_{\mathit{l}}{\mathit{k}}_{\mathit{p}}\mathit{s}+{\mathit{k}}_{\mathit{l}}{\mathit{k}}_{\mathit{i}}}{{\mathit{s}}^{\mathbf{2}}+{\mathit{k}}_{\mathit{l}}\left({\mathit{k}}_{\mathit{p}}-{\mathit{k}}_{\mathit{i}}\frac{\mathbf{4}\mathit{\tau }+\mathit{T}}{\mathbf{8}}\right)\mathit{s}+{\mathit{k}}_{\mathit{l}}{\mathit{k}}_{\mathit{i}}}$$

(20)

When utilizing estimated signals in a system, it can cause perturbations. Therefore, it is essential to discuss the closed-loop stability and design a voltage controller to regulate the q-axis voltage to zero. Typically, the PI controller is employed as the voltage controller, which is designed based on the small-signal model of the PLL.

3.3. PI Gains Design

In this section, the PI controller gains were calculated using the second-order Characteristic Equation (CE) in Equation (20), in which the small-signal model closed-loop transfer function

$$s^2+\underset{2{\mathsf{\zeta }\mathsf{ώ}}_n}{\underbrace{k_l\left(k_p-k_i\left(\frac{4\tau -T}{8}\right)\right)}}s+\underset{{{\mathsf{ώ}}_n}^2}{\underbrace{k_l{k}_i}}$$

where ${\mathsf{ώ}}_n$ is the natural frequency and $\mathsf{\zeta }$ is the damping factor, can be used to construct the controller gains.

For the recommended Phase Margin (PM) range of 30° < PM < 60°, the value of b is chosen as $1+\surd 2$. This decision takes into account a damping factor $\mathsf{\zeta }$ of 0.707 and a desired PM of 45°. In addition, ${\mathsf{ώ}}_n$ is selected as 40π rad/s, τ = 0.002 s, and V = 1 pu, which yields $k_l$ = 0.618. Thus, the controller gains are ($k_p=377$ and $k_i=\mathrm{25,551}$).

The results in Figure 3 show that when a phase jump of 30 degrees is applied to the grid voltage at 0.02 s, the small-signal model and real-time model responses are quite similar, which validates the small-signal model.

The proposed single-phase, non-adaptive DCI PLL has the ability to eliminate the impact of DC-offset at any given delay time. To validate its effectiveness across various delay times, a DC-offset of 0.1 pu was intentionally introduced to the grid voltage at 0.02 s. Additionally, a phase jump of 30 degrees was applied to the grid voltage at 0.12 s, as shown in Figure 4a. In Figure 4a, the estimated voltage shown is for τ = 0.005 s.

The estimated phase error and frequency for the proposed single-phase, non-adaptive DCI PLL were evaluated under different delay times while considering the presence of a 0.1 pu DC-offset at 0.02 s and a phase jump of 30 degrees at 0.12 s in the grid voltage. The following time delays were chosen: τ₁ = 0.005, τ₂ = 0.002, τ₃ = 0.001, and τ₄ = 0.0002. The controller gains were calculated for the selected time delay as follows: for τ₁, ($k_p=181.5$ and $k_i=\mathrm{11,166}$); for τ₂, ($k_p=377$ and $k_i=\mathrm{25,551}$); for τ₃, ($k_p=719.4$ and $k_i=\mathrm{50,473}$); and finally, for τ₄, ($k_p=3482.5$ and $k_i=\mathrm{251,370}$). The simulation results are shown in Figure 4b,c.

The results show that the proposed PLL effectively eliminates the DC-offset within a short duration and allows for the utilization of any time delay without being limited to a specific value, as shown in Figure 4. Additionally, the results indicate that the delay time has a significant impact on the system’s behavior, as shown in Figure 4b,c. The fastest response was observed when a delay time was equal to 0.0002 s. In this scenario, the effect of the DC offset on the estimated phase error and frequency was found to be very small.

4. Results and Discussions

In this part, deferent scenarios were applied by using the MATLAB/Simulink tool to evaluate the performance of the proposed single-phase, non-adaptive DCI PLL with the non-adaptive (see Figure 5) and the adaptive (see Figure 6) single-phase DSC-PLLs [24]. In MATLAB/Simulink, the blocks “Three-Phase Programmable Voltage Source, Three-Phase V-I Measurement, and Three-Phase Series RLC Load” were used to generate the grid signal and introduce a disturbance in the grid voltage.

To achieve fair comparisons, the PI controller gains for the adaptive and the non-adaptive single-phase DSC-PLLs were designed based on their respective small-signal models using the same ζ and ${\mathsf{ώ}}_n$ as in the proposed single-phase, non-adaptive DCI PLL. Based on its small-signal model, the single-phase, non-adaptive DSC-PLL PI controller gains are calculated as $k_p=217.193$, $k_i=\mathrm{15,791.37}$, whereas the single-phase adaptive DSC-PLL gains are calculated as $k_p=296.15$, $k_i=\mathrm{15,791.37}$.

The following cases are considered for the comparison:

Case 1.

A phase jump of 30 degrees is applied at 0.02 s (see Figure 7a).

In this case, with a phase jump of 30 degrees added to the grid voltage, the proposed PLL locked the grid signal in 47 milliseconds (ms) (Figure 7b), while the single-phase, non-adaptive and the single-phase adaptive DSC PLLs required 52.9 ms and 54.9 ms, respectively. The proposed PLL has the fastest synchronization time.

Case 2.

A jump in the grid frequency is applied from 50 to 55 Hz at 0.02 s (see Figure 8a).

In the second case (Figure 8), the results show that the proposed non-adaptive DCI PLL has the shortest synchronization time when applying a 5 Hz jump in the frequency the phase error becomes zero in 39.10 ms (Figure 8b) while the non-adaptive DCS PLL was 64.70 ms and the single-phase adaptive DCS PLL was 70.00 ms. Moreover, the proposed PLL shows the minimum estimated peak frequency where the peak value of the estimated frequency is 55.16 hertz (Hz) (Figure 8c) while the single-phase, non-adaptive and the single-phase adaptive DSC PLL required 55.20 Hz and 55.24 Hz, respectively.

Case 3.

A DC-offset is applied at 0.02 s to the grid voltage with a value of 0.1 pu (see Figure 9a).

In this case, with a 0.1 pu DC-offset added to the grid voltage, the proposed single-phase, non-adaptive DCI PLL showed the shortest synchronization time, locking the grid signal in 18.90 ms (Figure 9b), compared to 52.80 ms for the non-adaptive DSC PLL and 49.4 ms for the adaptive DSC PLL. The estimated peak frequency for the proposed single-phase PLL was 50.06 Hz (Figure 9c), while the non-adaptive and the adaptive DSC PLL required 49.60 Hz and 49.67 Hz, respectively, so the proposed DCI PLL has the best behavior in this case.

Case 4.

A phase jump of 30 degree and a DC-offset of 0.15 Pu are applied to the grid voltage at 0.02 (see Figure 10a).

In the fourth case, with a 0.15 pu DC-offset and a phase jump of 30 degrees applied simultaneously to the grid voltage, the proposed single-phase, non-adaptive DCI PLL once again showed the fastest synchronization time, locking the grid signal in 45.60 ms (Figure 10b). Meanwhile, the non-adaptive DSC PLL and the adaptive DSC PLL required 53.00 ms and 56.40 ms, respectively.

Case 5.

A jump in the amplitude of the grid voltage from 1 to 1.2 Pu at 0.02 s with a DC-offset applied at the same time as in case 3 (see Figure 11a).

In this case, the results in Figure 11 show that the proposed single-phase, non-adaptive DCI PLL has the shortest synchronization time when a jump in the amplitude of the grid voltage and a DC-offset with value 0.1 pu were applied at 0.02 s. The proposed single-phase, non-adaptive DCI PLL’s phase error becomes zero in 39.20 ms (Figure 11b), while the non-adaptive DSC PLL was 42.10 ms and the single-phase adaptive DSC PLL was 42.90 ms.

Case 6.

A jump in the amplitude of the grid voltage from 1 to 1.1 Pu and a DC-offset with a value 0.2 Pu applied at 0.02 s (see Figure 12a).

Finally, in the last case, with a 0.2 pu DC-offset and a jump in amplitude from 1 to 1.1 pu applied simultaneously to the grid voltage, the proposed single-phase, non-adaptive DCI PLL showed the shortest synchronization time of 38.10 ms (Figure 12b), while the non-adaptive DSC PLL required 59.20 ms and the adaptive DSC PLL required 55.90 ms. The estimated peak frequency for the proposed PLL was 49.82 Hz (Figure 12c), while the non-adaptive and adaptive DSC PLL required 49.26 Hz and 49.41 Hz, respectively, so the proposed PLL has the best behavior in this case.

The statistical results obtained from the numerical simulations conducted under different scenarios, including phase jumps, frequency variations, amplitude changes, and DC-offsets, clearly demonstrate that the proposed PLL exhibits the fastest transient response, shortest synchronization time, and better dynamic performance compared to other PLLs across nearly all performance indices.

Table 1. The synchronization time and the peak estimated frequency for cases one to six.

Case Study		Proposed PLL	Non-Adaptive DSC-PLL	Adaptive DSC-PLL
Case	Peak estimated frequency (Hz)	54.73	53.53	53.54
1	Synchronization time (ms)	47	52.9	54.9
Case	Peak estimated frequency (Hz)	55.16	55.20	55.24
2	Synchronization time (ms)	39.1	64.7	70
Case	Peak estimated frequency (Hz)	50.06	49.60	49.67
3	Synchronization time (ms)	18.9	52.8	49.4
Case	Peak estimated frequency (Hz)	54.69	53.53	53.50
4	Synchronization time (ms)	45.6	53	56.4
Case	Peak estimated frequency (Hz)	49.66	50.41	50.37
5	Synchronization time (ms)	39.2	42.1	42.9
Case	Peak estimated frequency (Hz)	49.82	49.26	49.41
6	Synchronization time (ms)	38.1	59.2	55.9

summarizes the performance comparisons of the proposed single-phase, non-adaptive DCI PLL with the single-phase, non-adaptive DSC PLL and the single-phase adaptive DSC PLL in terms of phase settling time and the peak estimated frequency.

According to the results in Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 and Table 1, even though the single-phase, non-adaptive DSC PLL and the single-phase adaptive DSC PLL have a good response, the proposed PLL has the fastest dynamic response with the minimum settling time. Moreover, the proposed single-phase, non-adaptive DCI PLL can eliminate the DC-offset in a very short time (see the third case in Table 1) and utilizing any time delay; that is, it is not restricted to a specific time delay.

5. Conclusions

In this study, a straightforward and effective approach is presented for mitigating the impact of DC-offset during the grid synchronization process. The proposed method involves using a simple single-phase PLL based on the TD technique to generate orthogonal signals and a DSC operator to eliminate the DC-offset effect. This PLL is capable of removing DC-offsets using any time delay, without restrictions. The proposed method contains a phase error compensator operator to solve the phase shift problem caused by the delayed version of the input signals. The research includes a detailed discussion on the mathematical model, small-signal model, closed-loop stability, and design of PI controller gains. The small-signal model was validated by comparing it with a real-time model. The gains of the PI controller were determined by analyzing the real-time and small-signal models. This involved deriving a second-order characteristic equation to represent the system accurately. To evaluate the effectiveness of the proposed technique, various scenarios were simulated using the MATLAB/Simulink tool and compared with other single-phase PLLs in terms of the performance indicators, such as settling time, frequency, and phase error. The scenarios involved introducing different disturbances to the input voltage that include adding phase jumps, introducing DC offsets, changing the grid frequency, and changing the voltage amplitude. The results demonstrate the phase error and estimated frequency for all simulated techniques. In addition, the results show the impact of introducing disturbances in the grid voltage and how the proposed PLL effectively locks onto the signal. Moreover, the results show that the proposed PLL has the fastest dynamic response and shortest settling time, making it a reliable option for grid synchronization. The proposed PLL is expected to be very fruitful from an industrial point of view due to its simplicity and efficiency.