6.1. Simulation Results of DAB as Interlink Converter
MATLAB/Simulink is used to simulate the DAB in
Figure 5 with the case-study parameter and control loop presented in
Section 4. The first is an open loop test to verify the SPS modulation waveforms of the DAB described in
Figure 6.
Figure 14 shows the gating signals of the LV and HV sides of DAB, the AC voltage at the LV and HV sides of the transformer, and the transformer leakage inductor current at
d = −0.25. The results show that the phase-shift PWM block in
Figure 13 works as expected to perform the required modulation for the DAB.
The second test is to verify the performance of the control loop of the current injected into the LV bus. Again, the voltages of the LV and HV sides are set at 48 V and 380 V, respectively. The reference current is initially at −1.5 A, then changed in a step to 1.5 A. As shown in
Figure 15, the injected current
Iinj follows the reference signal very well, reaching the steady state at 0.007 s with zero error. The negative injected current
Iinj sign means that the power flow is from the LV to the HV side, achieved with a negative phase shift. Conversely, a positive injected current
Iinj means the power flow from the HV side to the LV side, requiring a positive phase shift.
The last test investigates the impact of load variations in both DC buses and the power flow controlled by the interlink converter, according to the proposed droop control scheme, on the LV and HV buses’ voltages. Three cases are considered: first with 370 V < VHV < 390 V, then with VHV < 370 V, and finally with VHV > 390 V. As discussed before, the interlink converter is droop-controlled based on the magnitude of the voltage at the LV bus, but for low and high at the HV bus, it should be reprogrammed to prevent worsening the problem of excess surplus or shortage of power in that bus.
Threshold voltages and droop resistances modeled the LV DC bus and HV DC bus. For the LV DC bus, VNL_LV = 49.25 V and RdLV = 0.289 Ω, while for the HV DC bus, VNL_HV = 390 V and RdHV = 0.289 Ω. In this case, the LV DC bus voltage can be calculated by (11) through the droop Equation (1) with an equivalent threshold voltage of VNL_eq = 48.625 V, obtained considering the threshold voltages of the LV DC bus and interlink converter, and a droop constant Rdeq = 0.1445 Ω, the parallel combination of RdLV and Rdint. For a given current injected by the DAB into the LV side, the current drawn from the HV side will be much smaller due to the transformer’s turn ratio. The HV DC bus voltage can be calculated by (11) through the droop Equation (1) with a threshold of VNL_HV and a droop constant of RdHV.
The simulation results are shown in
Figure 16. Initially, both DC buses are connected to 80 Ω loads, presenting voltages
VLV = 48.54 V and
VHV = 388.6 V. The value of the current injected into the LV bus (
Iinj) is −1.87 A, determined by the V-I droop characteristic of the interlink converter. With
VLV = 48.54 V higher than
VNL_int = 48 V, power is shown to be drawn from the LV bus and sent to the HV bus. At
t = 0.02 s, an additional 40 Ω is connected to the LV side, resulting in a decrease in the voltage at that bus,
VLV = 48.36 V, and in the current, the interlink converter draws power from the LV bus,
Iinj = −1.26 A. The change, a reduction, in
VHV is minimal due to the small value of the LV side current reflected to the HV side current, and transformer turns ratio. At
t = 0.04 s, an additional 40 Ω is connected to the HV side and, since the reference value for the current of the interlink is a function of the LV DC bus only, the injected current does not change; the HV DC bus voltage becomes
VHV = 385.8 V, lower than before. At
t = 0.06 s, an additional 20 Ω is connected to the LV side, reducing the voltage in the LV bus to
VLV = 48 V, which makes
Iinj ≈ 0 A. At
t = 0.08 s, an additional 20 Ω is connected to the HV side; again, it does not affect the power sharing and the HV DC bus voltage drops to
VHV = 380.4 V. At
t = 0.1 s, an additional 40 Ω is connected to the LV side, reducing the voltage at this DC bus below 48 V
VLV = 47.85 V, and the power starts to flow from the HV DC bus to the LV DC bus with injected current:
Iinj = 0.52 A. At
t = 0.12 s, an additional 40 Ω is connected to the HV side and, again, it does not affect the power sharing, and the HV DC bus voltage drops to
VHV = 377.7 V. At
t = 0.14 s, an additional 20 Ω is connected to the LV side; therefore, the injected current increases
Iinj = 1.73 A and this means more power flow from the HV side to the LV side with more drop in the LV DC bus
VLV = 47.5 V. Finally, at
t = 0.16 s, an additional 20 Ω is connected to the HV side and it does not affect the power sharing, and the HV DC bus voltage drops to
VHV = 372.5 V. The results show that the power injected by the interlink converter does not depend on the HV voltage side, as the V-I curve is a function of the LV side. In addition, the interlink converter successfully directs the power between the LV and the HV sides based on the proposed V-I curves.
Figure 17 shows simulation results for a case with
VNL_HV = 395 V, where the voltage at the HV bus is higher than 390 V, from
t = 0 s to 0.6 s. In such a case, the proposed control law for the interlink converter should prevent any power flow to the HV bus, which already has a surplus of power. Initially, both DC buses are connected to 80 Ω loads, presenting voltages
VLV = 49.32 V and
VHV = 393.6 V. At
t = 0.02 s, an additional 40 Ω load is connected to the HV DC bus,
VHV decreases to 390.8 V, and there is no power flow from the LV to the HV DC bus. At
t = 0.04 s, an additional 40 Ω load is connected to the LV DC bus,
VLV = 48.72 V, still higher than 48 V, and there is no power flow from the LV to the HV DC bus because of the voltage at the HV bus. At
t = 0.06 s, an additional 40 Ω load is connected to the HV DC bus,
VHV drops to 385.26 V, below 390 V, and power starts to flow from the LV to the HV DC bus. Due to that,
VLV drops to 48.36 V with
Iinj = −1.25 A as the V-I curve in
Figure 4. At
t = 0.08 s, an additional 40 Ω load is connected to the LV DC bus,
VLV ≈ 48 V, which makes
Iinj ≈ 0 A. In this case, there is no power flow from the LV DC to the HV DC but now it is due to
VLV ≈ 48 V=
VNL_int. After that, power flow from the HV to the LV DC bus increases at
t = 0.12 s and
t = 0.16 s, when loads are added to the LV bus, but not at
t = 0.14 s, when there is a load increase in the HV DC bus. The results show that the proposed interlink V-I curve could prevent power flow from the LV to the HV side when the HV bus has a voltage higher than 390 V, which means that the HV DC bus cannot supply power to the grid for some reasons.
Figure 18 shows simulation results for a case with
VNL_HV = 380 V, where the HV DC bus is lower than 370 V, from
t = 0.1 s to 0.18 s. In such a case, the proposed control logic of the interlink converter prevents the power flow from the HV DC bus to the LV DC bus, achieved by reprogramming the current limit as in
Figure 4,
Iinj = 0. To prevent the HV DC bus batteries from discharging through the LV DC bus, initially, both DC buses are connected to 80 Ω loads, presenting voltages
VLV = 48.54 V and
VHV = 378.63 V with
Iinj = −1.87 A, meaning that power flows from the LV to the HV side. At
t = 0.02 s, an additional 40 Ω load is connected to the HV DC bus and
VHV decreases to 375.9 V without changes in the current of the interlink converter. At
t = 0.04 s, an additional 40 Ω load is connected to the LV DC bus, and
VLV decreases to 48.36 V, indicating a reduction of the power surplus on the LV side, which makes
Iinj reduce to −1.26 A. At
t = 0.06 s, an additional 40 Ω load is connected to the HV DC bus and
VHV drops to 370.63 V. At
t = 0.08 s, an additional 40 Ω load is connected to the LV DC bus,
VLV ≈ 48 V, which makes
Iinj ≈ 0 A. In this case, there is no power flow from the LV DC to the HV DC since
VLV ≈ 48 V =
VNL_int. At
t = 0.1 s, an additional 40 Ω load is connected to the HV DC bus and
VHV drops to 368.05 V, below 370 V, and the interlink should prevent the power flow from the HV DC bus to the LV DC bus as described in
Figure 4. Therefore, at
t = 0.12 s, when an additional 40 Ω is connected to LV DC,
Iinj = 0, indicating that power does not flow from the HV DC bus to the LV DC bus, even though
VLV = 47.7 V, <
VNL_int = 48 V, as discussed in
Figure 4. After that, power flow from the HV to the LV DC bus is still prevented at
t = 0.14 s and
t = 0.16 s when loads are added to the HV bus and LV bus, respectively. The results show that the proposed interlink V-I curve could prevent power flow from the HV to the LV side when the HV side has a voltage less than 370 V, which prevents the HV side batteries from discharging into the LV side.
6.2. Simulation Results of Dual DC Buses Nanogrid
MATLAB/Simulink is used to simulate the dual DC buses nanogrid in
Figure 19 under different operation conditions. A class C DC–DC converter, as in
Figure 19, is used as the main power electronics interface of the DERs: solar panels and batteries. A class C DC–DC converter is also used along with a DC–AC converter as the two-stage AC grid interface.
Regarding the power and the current sharing, the V-I in
Figure 2 and
Figure 3 were used. For the HV DC bus DERs, a 5 kW PV panel and battery were considered with a droop constant
RdS_380 =
RdB_380 = 0.763 Ω, and a 10 kW grid connection was considered with a droop constant
RdG = 0.3815 Ω. They resulted in 14.2 A, 13.11 A, and 26.22 A as current limits for the solar, battery, and grid converters. For the LV DC bus DERs, a 2 kW PV panel, battery, and interlink were considered with a droop constant
RdS_48 =
RdB_48= Rdint = 0.0289 Ω. They resulted in a 44 A current limit for the solar converter and a 43.25 A current limit for the battery and interlink converters. The supercapacitors (SC) were controlled to support the dynamics of the battery’s current by splitting the storage inductor current into low frequencies for the battery and high frequencies for the SC using a low-pass filter (LPF) with a 30 Hz cut-off frequency.
The same current control loop parameters can be used for all DERs at the same DC bus. A PI type-III controller was designed for the same equivalent plant with a transfer function shown in (12) [
47,
48]. They were designed for a crossover frequency of
fx = 2 kHz (10% of the switching frequency) and a phase margin of
PM = 80° for both DC buses. For the LV DC bus converters, the following plant parameters were used:
Vout =
VDC = 48 V,
IDC = 41.67 A,
R = 1.152 Ω,
L = 300 µH,
C = 1500 µF, and
D = 0.46 for
VPV = VB = VSC = 29 V.
R was selected as the maximum load that could be supplied by the RES alone. Finally, the PI controller parameters are computed as
KPI = 0.0117,
τ = 175 µs, and
TP = 36 µs. For the HV DC bus converters, the following plant parameters were used:
Vout = VDC = 380 V,
IDC = 13.16 A,
R = 27.94 Ω,
L = 3000 µH,
C = 1500 µF, and
D = 0.39 for
VPV = VBat = VSC = 232 V.
R was selected as the maximum load that could be supplied by the RES alone. Finally, the PI controller parameters are computed as
KPI = 0.0015,
τ = 171 µs, and
TP = 37 µs. The interlink converter with the following parameters: transformer turns ratio n = 0.25, leakage inductance L=10.7 µH, switching frequency
fs = 20 kHz, and HV and LV capacitors
CHV =
CLV = 1500 µF. Then, a PI type-III compensator is designed for a cut-off frequency of 240 Hz [
31] and a phase margin
PM = 80°. Therefore, the compensator parameters can be calculated as
τ = 1.4 ms,
TP = 318 µs, and
KPI = 0.049 at a load resistance of 1.15 Ω.
The first test of the dual DC buses nanogrid is with a grid connection, and the batteries are not fully charged. The indication of the load variations in the system with the respective times and the numerical values of the voltage and current waveforms shown in
Figure 20 and
Figure 21 are summarized in
Table 2 and
Table 3 for the HV DC bus and the LV DC bus, respectively. The figures demonstrate that while the grid, the interlink, and the battery converters operate with droop control, the solar converters operate at the MPPT. The grid converter supports the HV bus and indirectly the LV bus through the interlink converter with
Iint = 2 A when a 305 Ω load is initially attached to the HV bus and 40 Ω to the LV bus. The LV bus load increased to 7 Ω at
t = 0.1 s and additional support came from the HV bus at
Iint = 4.8 A, which raised the grid current to 5.3 A. At
t = 0.2, the HV DC bus increased to 63.4 Ω; the grid current changed to 5.2 A to support the HV bus, while the interlink converter current remained constant because it depended on the LV bus.
Figure 20 shows that the grid current varied when the HV bus load or LV bus changed, while
Figure 21 shows that the interlink converter current changed when the LV bus load changed. Based on these results, the nanogrid operates according to the V-I curves presented in
Figure 2 and
Figure 3 for the HV DC and LV DC buses, respectively. The RESs operate at maximum power. At the HV DC bus, the battery and the grid converter operate with droop control, the battery is in charging mode, and the grid supports the nanogrid by supplying power. At the LV DC bus, the battery and the interlink converter operate with droop control, the battery is in charging mode, and the interlink supports the LV DC bus. In addition,
Figure 20 and
Figure 21 show that the PI type III controller successfully controls the dynamic response of the converters where the currents reach the steady state in almost 10 ms. However, the batteries’ currents are much slower than other resources due to hybrid energy storage between the supercapacitors and the batteries, which is more efficient for the batteries.
The second test of the dual DC buses nanogrid is without a grid connection, and the batteries are not fully charged. The indication of the load variations in the system with the respective times and the numerical values of the voltage and current waveforms shown in
Figure 22 and
Figure 23 are summarized in
Table 4 and
Table 5 for the HV DC bus and the LV DC bus, respectively. Based on these results, the nanogrid operates with the V-I presented in
Figure 2 and
Figure 3 for HV DC and LV DC buses, respectively. By comparing the cases above, one can say that the grid connection gives the DC nanogrid more power availability; missing this support leads to a higher voltage drop in the DC buses, especially at the HV DC bus. Moreover, the battery started to discharge at
t = 0.6 s while in the charging mode with the grid connection.
Regarding the LV DC bus, the effect of missing the grid connection is less once the HV DC bus is higher than 370 V due to the power and current sharing V-I being based on the LV DC bus. Therefore, there is no change in the LV DC bus before
t = 0.5 s according to
Table 5 compared to
Table 3. At
t = 0.6 s, the HV DC load was increased to 24.5 Ω, and the HV DC bus dropped below 370 V; the HV battery operates in discharging mode and the interlink converter prevents the power flow from the HV DC to the LV DC bus (
Iint = 0), so the HV DC bus battery will not discharge through the LV DC bus. After
t = 0.6 s, the LV DC bus misses the support from the HV DC bus. Therefore, the voltage drops in the LV DC bus in
Table 5 increase compared with the case with grid connection in
Table 3 at the same load level. The RESs operate at maximum power at all periods. Moreover, the interlink converter prevents the LV and HV side batteries from discharging to charge each other. In addition,
Figure 22 and
Figure 23 show that the PI type III controller successfully controls the dynamic response of the converters where the currents reach the steady state in almost 10 ms. However, the batteries’ currents are much slower than other resources due to hybrid energy storage between the supercapacitors and the batteries, which is more efficient for the batteries.