Enhancement of Electrical Safe Operation Area of 60 V nLDMOS by Engineering of Reduced Surface Electrical Field in the Drift Region

Abstract

To enhance the electrical safe operation area (eSOA) of laterally diffused metal oxide semiconductor (LDMOS) transistors, a novel reduced surface electric field (Resurf) structure in the n-drift region is proposed, which was fabricated by ion implantation at the surface of the LDMOS drift region and by drift region dimension optimization. Technology computer-aided design (TCAD) simulations show that the optimal value of Resurf ion implantation dose 1 × 10¹² cm⁻² can reduce the surface electric field in the n-drift region effectively, thereby improving the ON-state breakdown voltage of the device (BV_on). In addition, the extended n-drift region length of the L_d design also improves device BV_on significantly, and is aimed at reducing the current density and the electric field, and eventually suppressing the n-drift region impact ionization. The results show that the novel 60 V nLDMOS has a competitive BV_on performance of 106.9 V, which is about 20% higher than that of the conventional one. Meanwhile, the OFF-state breakdown voltage of the device (BV_off) of 88.4 V and the specific ON-resistance (R_ON,sp) of 129.7 mΩ⋅mm² exhibit only a slight sacrifice.

1. Introduction

Recently, high-performance silicon-based LDMOS transistors featuring low specific R_ON,sp, high BV_off [1,2], have been studied for various power management modes such as DC-DC converters [3], display drivers [4], and wireless chargers [5]. In particular, the LDMOS device with a high eSOA is an effective candidate for high operating voltage and high-reliability applications such as automotive electronic fields [6]. In practice, the BV_on is usually regarded as an evaluation criterion for the eSOA capability of a device. In general, the BV_on of LDMOS is determined by the Kirk effect, which gives rise to the depletion region broadening under the high-voltage and large-current conditions in the drift region, and parasitic bipolar junction transistor (p-BJT) turning on at the source and bulk regions. To enhance BV_on, most LDMOS devices are fabricated by heavy doping in the source and bulk region to reduce the parasitic resistance (R_B) and suppress the formation of p-BJT [7,8,9,10,11,12]. However, the resulting LDMOS devices have a higher threshold voltage, which deteriorates the device switching efficiency and enhances manufacturing difficulty due to the high-energy ion implantation. Therefore, some researchers have proposed optimizing the drift region structure or doping concentration to suppress the Kirk effect, thus manufacturing LDMOS with a high BV_on [13,14,15,16,17].

Taur et al. used higher doping concentrations in the n-drift region of LDMOS to push the triggering of the Kirk effect to higher current levels to improve the BV_on [12]. However, increasing the total doping concentration in the n-drift region also degrades BV_off performance [15]. Therefore, selectively reducing the surface electric field implantation was proposed to improve the BV_on; however, the BV_off will also be degraded if the Resurf ion implantation is not well-controlled [16]. The TCAD simulation analysis shows that the BV_on is affected by not only the Kirk effect or the parasitic BJT characteristics, but also by the impact ionization weak point at the drift region of the device such as the field oxide corner or the surface near the drain side. As a result, it enables optimization of the impact ionization in the STI corner by adjusting the L_d, and at the drain side by Resurf ion implantation doping and dimensions, thus achieving the optimized BV_on while reducing the impact on the device V_th, BV_off, and R_ON,sp.

In this work, a novel LDMOS structure with reduced surface field implantation in the n-drift region and an optimized drift region length is proposed that can effectively improve the BV_on performance of the device. TCAD simulation results demonstrated that the current LDMOS device can exhibit a significantly superior tradeoff between BV_on, BV_off and R_ON,sp than that of the conventional one.

2. Materials and Methods

Figure 1a,b shows the cross-sectional schematic diagrams of the conventional LDMOS and our proposed one, respectively. For the conventional structure, the effective lengths of the channel region L_ch and the L_d are 1 and 9 μm, respectively. Meanwhile, the length of the field oxide is 1.2 μm, and the thicknesses of the gate oxide and shallow trench isolation (STI) are 12 nm and 0.4 μm, respectively. For the proposed structure, the L_ch and L_d are the same as the conventional structure; the differences lie in the Resurf ion implantation in the n-drift region and the critical dimensions of the L_d and L_s design. The threshold voltage (V_th) of both LDMOS devices is 1 V.

Referring to Figure 1b, the main fabrication process of the proposed LDMOS is illustrated as follows. First, the p type single crystalline (100) silicon wafer with a resistivity of 10 Ω·cm is chosen as the substrate. Subsequently, the active area is defined by the field oxide, i.e., STI. Afterwards, the device channel, drift region and Resurf ion implantation region are formed by ion implantation with an implantation energy ranging from 100 to 1000 KeV and an implantation dose of 1 × 10¹⁴ cm⁻². Then, the poly gate is defined by etching; the source and drain regions are generated by ion implantation with an implantation dose ranging from 1 × 10¹⁴ to 1 × 10¹⁵ cm⁻², and an energy range of 10 to 100 KeV. Finally, the device contact, metal connection and silicon surface passivation are implemented.

3. Results

In order to assure the accuracy of the subsequent TCAD simulation of 60 V nLDMOS, the simulation result was first calibrated in light of the experimental one for the 20 V LDMOS. Figure 2a shows that the transfer curves of 20 V nLDMOS, including I_ds -V_gs(lin) and I_ds -V_gs(sat), are well-calibrated by adjusting the mobility and impact ionization models during the TCAD simulation, while the breakdown characteristic curves I_ds -V_ds for OFF-state and ON-state are also calibrated, as shown in Figure 2b. It is worth noting that the I_ds -V_{gs (lin)} and I_ds -V_{gs (sat)} curves are normalized based on the I_ds of V_th = 1 V, and the BV_on and BV_off current are normalized based on the I_ds of V_ds = 20 V. As a result, the simulation results are highly consistent with the experimental results through the impact ionization and mobility model optimization. Finally, the TCAD simulation was implemented to the conventional structure of 60 V nLDMOS, and the main electrical parameters were obtained as BV_on of 88 V, BV_off of 93 V, and R_ON,sp of 116 mΩ·mm². This provided an important reference for the novel design of the 60 V nLDMOS.

3.1. Effect of Resurf Ion Implantation Dose and Energy on BV_on, BV_off, and R_ON,sp

Figure 3a shows the effect of Resurf ion implantation dose on the BV_on, BV_off, and R_ON,sp while fixing the Resurf ion implantation energy at 300 KeV for the LDMOS devices with L_ch = 1 μm and L_d = 9 μm. When the Resurf ion implantation dose increases from 0 to 2.5 × 10¹² cm⁻², the resulting BV_on increases from 88 V to a maximum value of 98 V, and then decreases to 71 V when increasing the Resurf ion implantation dose to 1 × 10¹³ cm⁻². This phenomenon can be explained by the fact that as the Resurf ion implantation dose increases, it can effectively suppress the strong electrical field caused by the Kirk effect, thereby increasing BV_on [15]. However, as the Resurf ion implantation dose further increases, the doping concentration in the Resurf region also increases. This will result in a higher current density, which enables the Kirk effect to be triggered, thus provoking the reduction in BV_on. On the other hand, as the Resurf ion implantation dose increases, the resulting BV_off decreases gradually from 93 V to 55 V (i.e., a nearly 50% drop), which is completely different to the variation trend of BV_on. This is mainly due to different electric fields across the drift region in the ON-state and OFF-state of the device. In other words, the resulting depletion region becomes narrower when the Resurf ion implantation dose increases, making it more likely that a stronger electric field in the drift region will occur, and a continuous decrease in BV_off. In addition, the R_ON,sp also decreases gradually from 116 to 96.5 mΩ⋅mm² with the increment of the Resurf ion implantation. This is mainly attributed to the enhanced doping in the n-drift region. Considering the essential requirements (BV_off > 80 V, BV_on > 90 V) of device safety operation, the ion implantation dose of 1 × 10¹² cm⁻² was chosen as the optimal condition, corresponding to BV_on = 94 V and BV_off = 77 V. Subsequently, the influence of the Resurf ion implantation energy on the BV_on, BV_off, and R_ON,sp was further studied in the case of a constant ion implantation dose of 1 × 10¹² cm⁻², as shown in Figure 3b. As the Resurf ion implantation energy increases from 100 to 600 KeV, the BV_on exhibits a small change between 93 to 95 V, and the BV_off also changes slightly from 80 to 77 V. In addition, the R_ON,sp remains unchanged at around 112 mΩ⋅mm². The above results indicate that the Resurf ion implantation energy has little effect on the BV_on, BV_off, and R_ON,sp of the nLDMOS device. This can be ascribed to the thermal processes following the Resurf ion implantation, including the formation of field oxide and the thermal diffusion of the dopant at 1100 °C for 30 min, which could result in similar profiles of dopants under different implantation energies. In order to eliminate the influence of the thermal diffusion process on the Resurf ion implantation of the device, the Resurf implantation was carried out after the field oxidation formation and the thermal diffusion. From the TCAD simulation, it can be seen that the electrical results obtained are 89 V for BV_on and 93 V for BV_off, which are close to the device performance of the 60 V nLDMOS conventional structure (88 V for BV_on and 93 V for BV_off). This means that the Resurf implantation ions cannot effectively penetrate the field oxide into the silicon substrate surface, and no significant impact is present on the device characteristics. In addition, if the field oxidation is removed from the n-drift region of the device, a high electric field will appear on the surface of the device, thereby contributing to a significant decrease in the breakdown voltage of the device. As a result, the optimal Resurf ion implant energy of 300 KeV was chosen.

Figure 4a,b shows the optimized Resurf ion implantation conditions on the surface of the n-drift region (300 KeV, 1 × 10¹² cm⁻²) that could reduce the impaction ionization rate of the device surface effectively under the same bias condition. Furthermore, Figure 4c,d shows that the optimized Resurf ion implantation on the surface of the n-drift region also reduces the horizontal and vertical electric fields of the device surface significantly. In a word, the weakened impaction ionization rate and surface electric field assist in suppressing the Kirk effect near the drain terminal of the device, thereby improving the device’s ability to withstand large currents and high voltages, and ultimately achieving the optimization of device BV_on.

3.2. Effect of Resurf Ion Implantation Length L_s and the n-Drift Region Length L_d on BV_on, BV_off, and R_ON,sp

Figure 5a shows the dependence of BV_off, BV_on and R_ON,sp on the Resurf ion implantation length L_s under the Resurf ion implantation conditions (300 KeV, 1 × 10¹² cm⁻²), and the drift region length L_d of 9 μm. When L_s increases from 1 to 5 μm, the BV_off decreases from 92.5 to 49.6 V rapidly, with a significant change of nearly 50%. At the same time, when L_s increases from 1 to 3 μm, BV_on increases from 89 V to a maximum of 94 V, and then decreases to 92 V as L_s further increases to 5 μm. As a result, the change in BV_on is only 5 V which is similar to the effect of the Resurf ion implantation dose on device BV_on. This phenomenon could be explained by the fact that it can effectively suppress the high electric field caused by the Kirk effect as L_s increases, thereby increasing BV_on [18]. However, a new high electric field will be generated as L_s further increases due to the higher doping concentration, which in turn will cause BV_on to start to decrease. Therefore, there is a maximum value for BV_on corresponding to the optimal L_s of 3 μm. In addition, R_ON,sp decreases from 115.4 to 96.6 mΩ⋅mm² with the increase of L_s, representing nearly 20% deceasing. As L_s increases, the region of high doping concentration in the n-drift region also increases, thus leading to the suppression of the electric field distribution in the OFF-state, and a significant decrease in BV_off. In addition, due to the increase of doping concentration in the n-drift region, the resistance in the n-drift region correspondingly decreases, thereby resulting in a significant decrease in the R_ON,sp from 115.4 to 96.5 mΩ⋅mm² with L_s increasing from 1 to 5 μm.

Figure 5b shows the effect of the n-drift region length L_d on the BV_off, BV_on and R_ON,sp under the L_s of 3 μm. As L_d increases from 7 to 12 μm, the BV_on increases from 54 to 115 V, nearly a double enhancement. Meanwhile, the BV_off also has a significant improvement from 47 to 95 V. However, the R_ON,sp also increases rapidly. Therefore, L_d has a significant impact on device parameters such as BV_on, BV_off, and R_ON,sp. Under a high gate voltage condition, such as V_gs = 5 V, the longer the n-drift region is, and the lower the conduction current of the device, making it more resistant to triggering of the Kirk effect, thereby improving the BV_on. In addition, it is also conducive to a more uniform distribution of the electric field in the n-drift region when the device is turned off, as the length of the n-drift region increases, resulting in an increase in BV_off. Finally, as the length of the n-drift region increases, it will increase the resistance of the n-drift region, which is responsible for a weakening of the device’s conduction current ability and an increase in the specific conduction resistance.

4. Discussion

An interesting phenomenon is found in the TCAD optimization design of the n-drift region length L_d. When L_d is increased to 10 μm, the BV_on and BV_off of the device begin to saturate. It is worth noting that the BV_off is determined by the avalanche impact ionization under the off state, while the BV_on is determined by the impact ionization under the on state of the large current. As a result, the underlying mechanisms affecting BV_on and BV_off are different. In Figure 6a, the factors affecting the BV_off saturation include the generation of the first avalanche impact ionization position and the depletion region broadening in the horizontal direction. When L_d increases to a certain extent, the width of the horizontal depletion region reaches its maximum, and the critical electric field of the avalanche occurs at the first avalanche impact ionization position. The BV_off is determined by the first avalanche impact ionization position. When L_d continues to increase, it no longer affects the distribution broadening of the depletion region and the avalanche impact ionization. As a result, the BV_off is no longer related to L_d. In Figure 6b, the factors that contribute to the saturation of BV_on include the generation of the first avalanche impact ionization position and the generation of the second avalanche impact ionization position. When L_d increases to a certain extent, the electric field at the second avalanche impact ionization position has not yet reached the avalanche critical electric field; however, the first avalanche impact ionization position has already reached the avalanche critical electric field [19,20]. This means that BV_on is ultimately determined by the position of the first high electric field, and that the BV_on reaches its maximum value. Regarding the overall device performance, including optimal BV_on, BV_off, and R_ON,sp, the L_d of 10 μm is chosen as the optimal condition. In this condition, the BV_on will increase to 106.9 V and BV_off will increase to 88.4 V, but R_ON,sp will sacrifice to 129.7 mΩ⋅mm².

Finally, the electrical performance of the novel designed 60 V nLDMOS is 106.9 V for BV_on, 88.4 V for BV_off, and 129.7 mΩ⋅mm² for R_ON,sp, and the BV_on is nearly 20% higher than that of conventional device structures, and there is a slight sacrifice for BVoff and R_ON,sp, as shown in Figure 7a,b. This result indicates that the Resurf ion implantation and the n-drift region dimension design is an effective method for improving the performance of device BV_on.

5. Conclusions

In summary, a novel 60 V nLDMOS with Resurf engineering in the n-drift region was proposed that enhances the device electrical safe operation area by suppressing the Kirk effect. The TCAD simulations showed that an optimized Resurf ion implantation can effectively reduce the surface electric field in the n-drift region. Furthermore, for the design of key dimensions of the device, such as the n-drift region length L_d, the device BV_on was significantly improved. Finally, the electrical performance of the novel designed 60 V nLDMOS optimized by Resurf ion implantation and device dimension design was optimized with 106.9 V for BV_on, 88.4 V for BV_off, and 129.7 mΩ⋅mm² for R_ON,sp. The novel structure BV_on is 20% higher than that of the conventional one, combined with a slight sacrifice on BV_off and R_ON,sp. This work provides a very useful method for manufacturing high-reliability nLDMOS.