Normally Off AlGaN/GaN MIS-HEMTs with Self-Aligned p-GaN Gate and Non-Annealed Ohmic Contacts via Gate-First Fabrication

Abstract

This study introduces an enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) featuring a self-aligned p-GaN gate structure, fabricated using a gate-first process. The key innovation of this work lies in simplifying the fabrication process by utilizing gate metallization for both electrical contact and etching mask functions, enabling precise self-alignment. A highly selective Cl₂/N₂/O₂ inductively coupled plasma (ICP) etching process was optimized to etch the p-GaN layer in the access regions, with a selectivity ratio of 33:1 and minimal damage to the AlGaN barrier. Additionally, a novel, non-annealed ohmic contact formation technique was developed, leveraging ICP etching to create nitrogen vacancies that facilitate contact formation without requiring thermal annealing. This technique streamlines the process by combining ohmic contact formation and mesa isolation into a single lithographic step. Incorporating a SiNx gate dielectric layer led to a 4.5 V threshold voltage shift in the fabricated devices. The resulting devices exhibited improved electrical performance, including a wide gate voltage swing (>10 V), a high on/off current ratio (~10⁷), and clear pinch-off characteristics. These results demonstrate the effectiveness of the proposed fabrication approach, offering significant improvements in process efficiency and manufacturability.

1. Introduction

AlGaN/GaN high-electron-mobility transistors (HEMTs) leverage high-density two-dimensional electron gas (2DEG) channels, combining wide bandgap energy with low on-resistance and high breakdown voltage. Their intrinsically low gate charge facilitates high switching frequencies, making them promising candidates for power electronic applications [1]. However, the polarization-induced 2DEG formation at zero gate bias results in normally on operation for most HEMTs, posing safety risks, reliability challenges, and design complexity. Various strategies, including recessed gate architectures (thin-barrier heterostructures) [2,3], p-type cap layers [4,5], and fluorine ion implantation, have been explored to achieve enhancement-mode operation [6,7]. However, fluorine-based treatments demonstrate thermal instability, whereas recessed gates are prone to increased gate leakage currents. Although commercially available p-GaN gate HEMTs on Si substrates represent the current mainstream solution for enhancement-mode devices, their fabrication remains challenging due to complex processing requirements. In these structures, a thick p-GaN layer is typically grown on a thin AlGaN barrier, followed by gate metal deposition on the p-GaN cap. The excess p-GaN outside the gate region is then removed via dry etching. Self-aligned etching with the gate metal as an etch mask effectively reduces alignment errors while ensuring uniform potential distribution within the p-GaN layer. However, precise etch control combined with minimization of the AlGaN barrier damage is critical to maintaining high electron density in the access regions.

Conventional high-temperature (HT) annealing for ohmic contact formation risks gate degradation, as demonstrated by microcrystallites in gate dielectrics and elevated interface trap density after annealing, both of which exacerbate leakage currents [8,9]. To overcome this limitation, a non-annealed ohmic contact formation technique was developed using inductively coupled plasma (ICP) etching. This process creates nitrogen vacancies through controlled plasma-induced damage, which act as donor-like defects to establish ohmic conduction while preventing gate degradation [10,11]. Concurrently, the metallization achieves enhanced sidewall contact with the two 2DEGs, facilitating ohmic contact formation along the etched trench sidewalls [12]. Furthermore, the intrinsically low hole concentration in p-GaN confines threshold voltages (${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$) to sub-3 V ranges, which are inadequate for most practical applications. Moreover, excessive gate leakage currents severely limit the operational gate voltage window [13]. The integration of a dielectric interlayer between the gate metal and p-GaN has been demonstrated as an effective approach to enhance ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ while suppressing leakage currents [14].

Herein, we present a novel normally off MIS-HEMT device integrating gate self-alignment technology with a gate dielectric layer, which fulfills the aforementioned requirements while reducing process complexity. The optimized etching process demonstrates an ICP etching selectivity of 33:1 for P-GaN over AlGaN through process parameter optimization, accompanied by ultralow etching-induced damage. Notably, the developed non-annealed ohmic process simultaneously implements ICP etching of ohmic contacts and mesa isolation—the first reported implementation for P-GaN gate devices to our knowledge—achieving ohmic characteristics while significantly simplifying process flow. The fabricated device exhibits a threshold voltage (${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$) of 4.5 V, positioning it at the forefront of reported values for comparable structures. Compared with conventional HEMT devices without gate dielectric layers, this architecture demonstrates a significant positive shift of +2.5 V in ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$. Moreover, the proposed device achieves an excellent electrical performance including a wide gate swing of 10 V, an on/off ratio exceeding ${10}^7$, while maintaining subthreshold swing and dynamic on-resistance (Ron) comparable to conventional dielectric-free HEMT devices.

2. Device Structure and Fabrication

The E-mode AlGaN/GaN heterostructure was epitaxially deposited on 8-inch silicon substrates using a planetary Aixtron G5+ metal–organic chemical vapor deposition (MOCVD) system at Suzhou Hanhua Semiconductor Ltd. (Suzhou, China). Trimethylgallium (TMGa), trimethylaluminum (TMAl), and NH₃ served as the gallium, aluminum, and nitrogen precursors, respectively. Prior to growth, the substrate underwent thermal annealing at 1100 °C in a hydrogen atmosphere to eliminate surface oxides. This was followed by an aluminum pre-deposition step conducted without NH₃. The E-mode HEMT layers were subsequently grown, with the epitaxial structure (Figure 1a) consisting of the following sequential layers: an AlN nucleation layer, a 4.8-μm AlN/AlGaN superlattice buffer, a 350 nm GaN channel, a 13 nm Al_0.23Ga_0.77N barrier, and an 80 nm Mg-doped p-GaN cap layer designed for normally off operation. The p-GaN layer was doped with magnesium at a concentration of 2 × 10¹⁹ cm⁻³, with in situ activation achieved under a nitrogen ambient during MOCVD growth. The wafers were then fabricated into devices, and the schematic of the device fabrication process flow is depicted in Figure 1.

The device fabrication is initiated with gate stack formation. Before processing, the as-grown wafer was subjected to sequential surface preparation: (1) oxide removal using buffered oxide etch (BOE, HF: H₂O = 1:6) for 90 s, (2) ultrasonic cleaning in acetone and isopropanol each for 10 min. A 20 nm ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ dielectric was deposited on the p-GaN surface by low-pressure chemical vapor deposition (LPCVD) at 785 °C and 300 mTorr, using N₂ as carrier gas with dichlorosilane (DCS) and NH₃ as precursors. The gate pattern was defined by photolithography, followed by electron-beam evaporation of a 350 nm-thick Ni layer and lift-off patterning. The Ni gate structure also served as a hard mask for subsequent p-GaN dry etching. A fluorine-based inductively coupled plasma (ICP) dry etch was first employed to remove the ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ in non-gate regions. Subsequently, a low-damage, high-selectivity Cl₂/O₂/N₂ (30/10/10 sccm) inductively coupled plasma (ICP) etching process was implemented with 100/25 W ICP/bias power and 15 mTorr chamber pressure to etch the p-GaN layer. The etching process was conducted for 5 min, including an over-etching duration of 1 min to ensure the complete removal of the p-GaN material, resulting in an etch depth of 80 nm. Benefiting from the high selectivity characteristics of this process, the etching was automatically terminated at the AlGaN interface. Post-etch damage was chemically passivated through immersion in 25 wt.% tetramethylammonium hydroxide (TMAH) solution maintained at 85 °C for 15 min. Mesa isolation with 120 nm depth was formed using Cl₂/N₂ ICP etching. Ohmic regions were defined through ICP etching, whereby plasma-induced nitrogen vacancies facilitated ohmic contact formation through donor-type defects, eliminating the requirement for high-temperature annealing and thus avoiding gate degradation. A Ti/Al/Ni/Au (20/130/50/50 nm) ohmic-contact metallization stack was deposited using electron-beam evaporation and defined by lift-off patterning. Additionally, a Ni metal–gate reference device (without dielectric) was fabricated for comparative analysis, The device with a gate dielectric layer will be referred to as the insulator gate device, and will be described using this terminology in the following text. The structural diagrams of the two types of devices are shown in Figure 2.

Figure 3a presents optical microscopy images of the fabricated devices, while Figure 3b shows a top-view SEM image of the fabricated device, with the gate, source, and drain electrodes clearly identified. Notably, the ICP-etched recess features of the ohmic contacts at the source and drain demonstrate distinct morphological properties. Figure 3c presents a cross-sectional scanning electron microscopy (SEM) image showing the Ni gate electrode, ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ gate dielectric, and p-GaN layer.

3. Results and Discussion

3.1. Self-Terminated Etching of GaN over AlGaN

In AlGaN/GaN HEMTs, achieving an enhancement-mode (E-mode) operation requires complete depletion of the 2DEG under zero gate bias, implying that the AlGaN barrier must be sufficiently thin. However, the thin AlGaN barrier layer renders the 2DEG sheet carrier density (${\mathrm{n}}_{\mathrm{s}}$) highly sensitive to both the unintentional recess depth formed in AlGaN during p-GaN etching and the presence of residual p-GaN material, as demonstrated in [15]. These dependencies significantly impact device output characteristics, underscoring the need for precise control of p-GaN etch depth while minimizing AlGaN surface damage.

Achieving a high etch selectivity between p-GaN and AlGaN—i.e., maximizing the p-GaN etch rate while minimizing (or nearly eliminating) the AlGaN etch rate—is critical to completely removing the p-GaN layer without damaging the AlGaN barrier. Chlorine-based dry etching demonstrates monotonic etch rate reduction correlating with elevated aluminum composition AlGaN [16]. Controlled oxygen introduction during plasma processing facilitates self-limiting (Al,Ga)O_x passivation layer formation via plasma-enhanced oxidation, effectively terminating the AlGaN etching process [17]. Tuning the competition between oxidative passivation and ion-assisted oxide removal enables active selectivity control throughout the etching process. The ICP etch rate and selectivity depend strongly on RF power, ICP power, and chamber pressure parameters. Through design-of-experiments on HanHua Semiconductor’s ICP system (Suzhou, China), we established parameter optimization protocols guided by established plasma-etch models [18,19], yielding high-selectivity, low-damage p-GaN etching over AlGaN. Specifically, reduced ICP/bias power (100/25 W) lowered the etch rate, while increasing chamber pressure to 15 mTorr shortened the ion mean free path, inhibiting etch product desorption. Oxygen flow rates were varied (0–10 sccm) to investigate its role.

Experiments utilized GaN and Al_0.23Ga_0.77N samples grown on Si substrates via MOCVD. To facilitate etch depth measurements, Sample A (GaN) was grown up to the buffer layer termination, whereas Sample B (Al_0.23Ga_0.77N) was designed with an intentionally thickened barrier layer without p-GaN capping, as schematically shown in Figure 4b. Substrates were diced into 10 × 10 mm² specimens, where a 200 nm SiO₂ layer deposited by plasma-enhanced CVD served as an etching mask. Etch depths under varying O₂ flows (0–10 sccm) were quantified using atomic force microscopy (AFM) to determine the etch rates. Notably, the process demonstrated excellent uniformity and repeatability. Figure 4b systematically compares the etch rates of p-GaN and Al_0.23Ga_0.77N layers under varying oxygen flow rates, with calculated selectivity ratios (p-GaN: AlGaN), as shown in Figure 4a, illustrating process tunability.

As shown in Figure 4, the ICP etch rate of Al_0.23Ga_0.77N decreases significantly with increasing O₂ flow, while the p-GaN etch rate remains consistently higher than that of Al_0.23Ga_0.77N. This disparity arises from the formation of an etch-resistant (Al,Ga) Ox film on the Al_0.23Ga_0.77N surface during oxygen-assisted etching. Notably, the p-GaN etch rate initially increases with O₂ flow, peaking at 96 nm/min for 4 sccm O₂, before declining to 20 nm/min at 10 sccm. In contrast, the Al_0.23Ga_0.77N etch rate decreases monotonically with rising O₂ flow, achieving maximum selectivity (p-GaN:AlGaN) at 4 sccm. At 10 sccm O₂, the process achieves both low etch rates and high selectivity, making it suitable for high etching accuracy applications.

For process validation, the full epitaxial stack shown in Figure 1a was diced into four 5 × 5 mm² specimens. Selected regions were protected by a 200 nm-thick SiO₂ mask deposited via PECVD and patterned through photolithography. Dry etching was subsequently performed using a Cl₂/O₂/N₂ gas mixture (30:10:10 sccm ratio) at 15 mTorr, with ICP source power and bias power maintained at 100 W and 25 W, respectively. Etching durations of 0, 1, 3, and 5 min were applied to the corresponding specimens. After etching, the SiO₂ mask was removed using BOE (buffered oxide etch), and characterization was performed by AFM. The experimental results are presented in Figure 5.

Figure 5 displays 2 μm × 2 μm AFM images comparing the etch duration effects, including reference images of as-grown p-GaN and Al_0.23Ga_0.77N surfaces. The root mean square (RMS) roughness of the p-GaN surface progressively increased from 0.38 nm (unetched) to 0.48 nm after 1 min of etching, further rising to 0.69 nm following 3 min of etching. Following complete p-GaN removal with subsequent 1 min overetching, the exposed Al_0.23Ga_0.77N surface showed reduced roughness (0.47 nm), representing an approximately 28% decrease compared to the as-grown reference surface (0.66 nm). This surface quality enhancement confirms the low-damage characteristics inherent to the high-selectivity, low-rate etching process. The residual features observed on the etched Al_0.23Ga_0.77N surface (Figure 5d) originate from intrinsic material features associated with the epitaxial growth process.

AFM step-height measurements quantified a total etch depth of ~80 nm, matching the nominal p-GaN layer thickness. Notably, the Al_0.23Ga_0.77N barrier layer exhibited less than 1 nm thickness loss during the 1 min overetch phase, demonstrating exceptional selectivity. This controlled barrier modification preserves the 2DEG density in access regions, a critical factor for maintaining low on-resistance in HEMT operation.

3.2. Non-Annealed Ohmic Contacts

ICP etching was implemented in ohmic regions to simultaneously fabricate recessed patterns and generate nitrogen vacancies at the contact interface, enabling non-annealed ohmic contact formation. During ICP dry etching, higher bias power improved current linearity, promoting ohmic behavior. Based on previous reports [11], a 100 W bias power was selected to optimize carrier transport. The ICP etching duration was precisely regulated (30–90 s) to achieve optimal contact resistance. Figure 6a shows the current-voltage (I-V) characteristics of recessed ohmic contacts under varying etch conditions, with the highest current density observed at 60 s etching.

Transfer length method (TLM) measurements yielded a contact resistance (${\mathrm{R}}_{\mathrm{c}}$) of 81.41 Ω·mm and a sheet resistance (${\mathrm{R}}_{\mathrm{s}\mathrm{h}}$) of 320 Ω/□, higher than the values obtained from conventional annealed contacts (850 °C rapid thermal annealing for 30 s). This elevated resistance primarily stems from surface damage induced by ICP etching and the reduced Al_0.23Ga_0.77N barrier layer in p-GaN-capped heterostructures. Figure 6b presents the TLM fitting curve for the 60 s ICP-etched contact, validating the feasibility of implementing this non-annealed process in p-GaN/AlGaN/GaN HEMTs while maintaining acceptable ohmic performance.

The relatively thin barrier layer (13 nm) and low Al composition (23%) in these structures suggest that contact resistance could be further reduced by optimizing epitaxial growth conditions. To simplify fabrication, the current process simultaneously defines ohmic recesses and mesa isolation in a single lithography step. However, the mesa isolation depth requirement (≥120 nm) inevitably limits the minimum ICP etching duration to 30 s. Introducing an additional lithography step to decouple these processes, along with precise tuning of ICP parameters, could enable shorter ohmic-specific etching times and lower ${\mathrm{R}}_{\mathrm{c}}$.

3.3. Device Performance

Devices were fabricated with a gate length ${\mathrm{L}}_{\mathrm{g}}$ = 2 μm, an effective gate width ${\mathrm{W}}_{\mathrm{g}}$ = 100 μm, a gate-source spacing (${\mathrm{L}}_{\mathrm{g}\mathrm{s}}$) of 2 μm, and a gate-drain spacing (${\mathrm{L}}_{\mathrm{g}\mathrm{d}}$) of 11 μm, as shown in the optical micrographs of the fabricated devices (Figure 3a). Figure 7a,b compare the output characteristics of insulator gate (${\mathrm{V}}_{\mathrm{g}}$ = −2 to +10 V) and metal gate (${\mathrm{V}}_{\mathrm{g}}$ = −3 to +4 V) devices. The insulated gate device exhibits an extended gate voltage swing compared with the metal gate device. Both devices demonstrate clean pinch-off characteristics at their maximum gate biases (4 V and 10 V, respectively). This improvement originates from the gate-first fabrication sequence—gate metal deposition precedes mesa isolation—which eliminates edge-type leakage pathways typically induced by mesa edge defects in conventional gate-last processes.

The metal gate device exhibited a maximum drain current density (${\mathrm{I}}_{\mathrm{D}}$,max) of 13 mA/mm at ${\mathrm{V}}_{\mathrm{g}}$ = 4 V, whereas the insulated gate device demonstrated ${\mathrm{I}}_{\mathrm{D}}$,max = 29 mA/mm at ${\mathrm{V}}_{\mathrm{g}}$ = 10 V, representing a 123% enhancement despite identical ohmic contacts and epitaxial structures. This performance enhancement was consistently observed in transfer characteristics (Figure 7c). The insulated gate device showed a threshold voltage (${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$) of 4.5 V (extracted via linear extrapolation), significantly higher than the metal gate device’s ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ of 2 V. This positive ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift originates from voltage division across the ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ gate dielectric, p-GaN layer, and channel region. The extended gate swing to 10 V further confirms effective gate leakage suppression by the ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ dielectric.

Notably, the maximum transconductance (gm,max = 13.6 mS/mm) of the insulated gate device shows no significant improvement over the metal gate version. This limitation arises from the increased gate-to-2DEG distance introduced by the dielectric layer. Device performance can be improved by the substitution of ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ with high-κ dielectrics ALD-based optimization of dielectric thickness and interface quality. The lack of secondary gm peaks (characteristic of hole injection [5]) indicates effective suppression of valence band parasitic conduction even at high gate biases.

Figure 8 illustrates energy band diagrams at threshold conditions for metal gate and insulated gate devices. For the metal gate device, the conduction band minimum (${\mathrm{E}}_{\mathrm{C}}$) achieves alignment with the Fermi level (${\mathrm{E}}_{\mathrm{F}}$) at ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$, thereby enabling the 2DEG recovery. The insulator gate device requires a higher gate bias to overcome the dielectric barrier while inducing equivalent band bending for 2DEG formation. Given identical epitaxial structures (dielectric excluded), the charge requirement (Q) for 2DEG activation is identical, which leads to the establishment of the following relationship:

$${\mathrm{Q}}_{\mathrm{M}\mathrm{e}\mathrm{t}\mathrm{a}\mathrm{l} \mathrm{G}\mathrm{a}\mathrm{t}\mathrm{e}}={\mathrm{Q}}_{\mathrm{I}\mathrm{n}\mathrm{s}\mathrm{u}\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{o}\mathrm{r} \mathrm{G}\mathrm{a}\mathrm{t}\mathrm{e}}$$

(1)

$${\mathrm{Q}}_{\mathrm{M}\mathrm{e}\mathrm{t}\mathrm{a}\mathrm{l} \mathrm{G}\mathrm{a}\mathrm{t}\mathrm{e}}={\mathrm{C}}_{\mathrm{o}\mathrm{x}}{\mathrm{V}}_{\mathrm{t}\mathrm{h}}\left(\mathrm{M}\mathrm{e}\mathrm{t}\mathrm{a}\mathrm{l}\right)$$

(2)

$${\mathrm{Q}}_{\mathrm{I}\mathrm{n}\mathrm{s}\mathrm{u}\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{o}\mathrm{r} \mathrm{G}\mathrm{a}\mathrm{t}\mathrm{e}}={\displaystyle \frac{1}{\frac{1}{{\mathrm{C}}_{\mathrm{S}\mathrm{i}\mathrm{N}}}+\frac{1}{{\mathrm{C}}_{\mathrm{O}\mathrm{x}}}}}{\mathrm{V}}_{\mathrm{t}\mathrm{h}}(\mathrm{I}\mathrm{n}\mathrm{s}\mathrm{u}\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{o}\mathrm{r} \mathrm{G}\mathrm{a}\mathrm{t}\mathrm{e})$$

(3)

where ${\mathrm{C}}_{\mathrm{O}\mathrm{x}}$ denotes the AlGaN barrier capacitance and ${\mathrm{C}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$ represents the ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ dielectric capacitance. From Equations (1)–(3), the threshold voltage relationship can be derived as follows:

$${\mathrm{V}}_{\mathrm{t}\mathrm{h}}(\mathrm{I}\mathrm{n}\mathrm{s}\mathrm{u}\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{o}\mathrm{r} \mathrm{G}\mathrm{a}\mathrm{t}\mathrm{e})={\mathrm{V}}_{\mathrm{t}\mathrm{h}}(\mathrm{M}\mathrm{e}\mathrm{t}\mathrm{a}\mathrm{l})\times (1+{\displaystyle \frac{{\mathrm{C}}_{\mathrm{O}\mathrm{x}}}{{\mathrm{C}}_{\mathrm{S}\mathrm{i}\mathrm{N}}}})$$

This establishes an inversely proportional relationship between Vth enhancement and ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ capacitance. Under varying ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ thicknesses, the electric field (${\mathrm{E}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$) remains constant throughout the heterostructure: ${\mathrm{U}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$ = ${\mathrm{E}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$ × ${\mathrm{t}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$. Here, ${\mathrm{U}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$ denotes the voltage drop across the dielectric, ${\mathrm{E}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$ represents the electric field, and ${\mathrm{t}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$ corresponds to the dielectric thickness. Consequently, ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ (insulator gate) exhibits direct proportionality to ${\mathrm{t}}_{\mathrm{S}\mathrm{i}\mathrm{N}}$, since thicker dielectrics require higher gate biases to maintain equivalent E-field conditions.

Figure 9a compares semi-log transfer characteristics, revealing an enhanced on/off ratio of ~${10}^7$ for the insulator gate device—two orders of magnitude higher than the metal gate device. The insulator gate exhibits superior gate leakage suppression, demonstrating significantly lower gate currents than those of metal gates. Subthreshold swing (SS) analysis yields average values of 157 mV/dec (insulated-gate) and 134.48 mV/dec (metal-gate) at ${\mathrm{V}}_{\mathrm{d}}$ = 10 V. Notably, both devices lack passivation layers, yet the metal gate SS outperforms the reported values in [20], highlighting the intrinsic interface quality benefits achieved through the gate-first process.

The on-resistance (Ron) was extracted from the linear region of the output characteristics at ${\mathrm{V}}_{\mathrm{g}}$ = 4 V (metal-gate) and ${\mathrm{V}}_{\mathrm{g}}$ = 10 V (insulated-gate), as documented in Figure 9b. The insulated gate device exhibits Ron = 347 Ω, higher than the metal gate counterpart (321 Ω); it is important to emphasize that both ohmic contact resistance and access region resistance values remain comparable between the two device configurations. This minimal difference (<8%) confirms comparable channel resistance and indicates no significant degradation in 2DEG carrier concentration or mobility due to the ${\mathrm{S}\mathrm{i}\mathrm{N}}_{\mathrm{x}}$ dielectric integration.

Further improvements in leakage and switching performance could be achieved through passivation layer optimization and tailored dielectric stress engineering. The absence of passivation in this work provides fundamental insights for the subsequent process optimization.

4. Conclusions

In conclusion, we have presented a gate-first self-aligned fabrication scheme for p-GaN HEMTs, which integrates high-selectivity dry etching, minimal etch damage, and non-annealed ohmic contacts. The Cl₂/O₂/N₂-based ICP-RIE process developed achieves high selectivity in etching p-GaN, ensuring that the AlGaN barrier layer remains intact while preserving the key two-dimensional electron gas (2DEG) density. The integrated non-annealed ohmic process eliminates the need for high-temperature annealing, significantly simplifying the manufacturing process. Notably, the non-annealed ohmic contact process results in a contact resistance of 81.41 Ω·mm, demonstrating effective ohmic contact formation without the risk of gate degradation associated with high-temperature annealing in conventional gate-first methods.

From a manufacturing perspective, the gate-first process offers significant advantages in terms of cost and simplicity. By integrating the gate metal as both etch mask and electrical contact while eliminating additional photolithography and etching steps, the approach reduces complexity while minimizing potential alignment errors. Furthermore, the process requires fewer steps, avoids high-temperature treatments, and provides a cost-effective solution for rapid device fabrication and performance testing.

A normally off AlGaN/GaN heterojunction field-effect transistor with SiNx gate die-electric was fabricated using the proposed gate-first process. The device exhibited excellent electrical performance with a threshold voltage shift of +4.5 V, an on/off current ratio exceeding ${10}^7$, a gate voltage swing of 10 V, and outstanding pinch-off characteristics. The dielectric integration further enhances the stability and performance of the device due to the expanded gate voltage swing and superior gate leakage suppression.

Overall, the proposed fabrication method not only provides high-performance, normally off GaN-based power devices, but also simplifies the manufacturing process, making it a promising solution for cost-effective, high-quality semiconductor device production.