An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA

Abstract

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.

1. Introduction

Clear communication has always been hindered by the problem of unreliable or noisy channels, ever since telecommunication systems and information theory were developed. With the prevalence of cellular communication and the transmission of sensitive data, the problem has seen a significant rise [1].

Richard Hamming invented the first Error Correction Code (ECC) in 1950 [2] to control and correct errors in data transmission over noisy channels. The encoding component of the ECC’s error control procedure includes the addition of redundant information to address potential errors across the message. The decoding process automatically detects and corrects errors once the data are received.

In the context of 5G, significant advancements have been made in the error correction process, as depicted (see Figure 1). This process involves CRC (Cyclic Redundancy Check) verification, where a short, fixed-size check-sum is initially computed based on the information packet. On the other hand, the CRC check recalculates this checksum and compares it to the one received to ensure data integrity. Block segmentation serves the purpose of splitting a longer data stream into smaller segments. Conversely, block concatenation involves combining smaller data blocks into a continuous stream. The rate matching/adaptation technique is employed to synchronize the data rates across various components of the system, ensuring efficient data transfer without overloading certain parts of the system. Bit interleaving involves merging bits from multiple source data streams into a unified stream, following a particular pattern.

The BER and Signal-to-Noise Ratio (SNR) metrics are employed to characterize the decoding capabilities [3,4]. The SNR is defined as the signal power divided by the noise power, whereas the BER is the number of errors divided by the total number of transmitted bits.

The main contribution of coding theory is to achieve lower SNRs for the same BER [5,6]. If an uncoded system has a BER of 10⁻⁴ at an SNR level of 4 dB, the corresponding coded system should have the same BER at a lower SNR (3.5 dB). In this case, the coding gain is 0.5 dB, which will decrease the signal power for the same BER. After being long ignored, LDPC codes have become one of the major codes for contemporary standards, as in the second-generation satellite digital video broadcast (DVB-S.2) and 5G-NR wireless communication [7,8]. They were invented by Robert Gallagher at the beginning of the 1960s [9]. Recently, they have been adopted for use in many significant communication systems, such as the Consultative Committee for Space Data Systems (CCSDS) [10].

The min-sum algorithm, a foundational technique in iterative decoding for LDPC codes, was initially derived as a simplified approximation of the Belief Propagation (BP) algorithm. Its efficiency and relatively low computational complexity have made it a popular choice for practical implementations. Subsequent variants such as Offset Min-Sum (OMS) [11], Approximate Min-Sum (AMS) [12], and Scaling Min-Sum (SMS) [13] have been introduced to enhance performance by incorporating additional approximations.

The OMS algorithm introduces an offset value to the message passing process, aiming to improve error floor performance. AMS simplifies the min-sum computations by using approximations, potentially reducing computational complexity. Finally, SMS applies scaling factors to the messages to enhance decoding performance.

The authors in [11] proposed a fully parallel architecture built on the first base graph (BG1). The internal modules of this architecture are equipped with multiplexers that have been designed based on the columns of the base graph. This has led to 19 parallel 68:1 multiplexers, which may require additional resources as they are constructed based on columns instead of rows. Additionally, the circular shifting blocks in this architecture receive addresses from a ROM memory, which can limit its design flexibility based on the characteristics of the base graph. The research outlined in reference [12] strives to improve the MS algorithm for decoding fixed-point 5G-LDPC codes. While the “improved adapted MS (IAMS)” algorithm showcased promising results in the study, the conducted decoding simulation (utilizing BG1 with R = 2/3 and Z = 104) suffered from alarming latency issues, requiring an excessive number of 15 iterations to achieve satisfactory decoding.

In their research paper [14], the authors introduced a sequential check node design to estimate the second smallest value in the MS algorithm by incorporating a variable weight parameter to the first minimum value. This design approach reduces hardware complexity by eliminating the need to calculate the second minimum value. However, the decoding process using this check node structure still poses challenges in terms of flexibility and latency, requiring up to 20 iterations. Furthermore, attaining the ideal level of parallelism becomes challenging due to the partially parallel architecture implemented in both the [12,14] designs.

To the best of our knowledge, despite extensive research on LDPC decoding, no prior investigations have succeeded in developing a single module for 5G-LDPC decoding that seamlessly combine reduced complexity, decreased latency, and superior performance, thus highlighting the novelty and significance of our study. This article aims to revolutionize 5G-LDPC decoding by introducing a ground-breaking decoder tailored explicitly for extended codeword lengths, emphasizing flexibility and reduced latency as its core objectives. Due to the 5G base graphs’ smaller number of rows compared to the columns, the read and write networks are built using Mp:1 and 1:Mp multiplexers (based on rows) to alleviate the interconnection blocks. The shifting amounts specified as base graph entries can be utilized as inputs of the decoder thanks to the flexible shifting block design proposed in our architecture. Moreover, our architecture empowers the model to seamlessly adapt to diverse structures of the first base graph (BG1), liberating the decoder from the confines of a singular application and rendering it invaluable across a multitude of assorted applications. An optimal low-latency method [15] is included in the control node processing block with very satisfactory results in terms of decoder latency. We have modified this approach and applied it to our 5G-NR decoder for the first time. Following the simulation of this architecture, our decoder achieves a remarkable feat by accomplishing the error correction process in a remarkably low number of iterations—a mere six. The discussed performance is substantiated through extensive simulations conducted across a range of iterations and code rates, affirming the exceptional efficiency and effectiveness of our design.

The rest of the article is structured as follows. Preliminaries for LDPC codes in the 5G-NR standards are presented in Section 3. Next, a digital representation of the internal blocks of the proposed architecture is given in Section 4. We discuss the results and related analyses in Section 5 and Section 6. Finally, the article concludes in Section 7.

2. Materials and Methods

Initially, the structure was constructed in Simulink using fundamental blocks to create a basic model consisting of 280 bits as a codeword. Subsequently, this design was transcribed into hardware description language (VHDL) and tested using ModelSim SE 10.6 software, focusing on a single frame. The development of this architecture paved the way for enhanced versions, as elaborated in the results section. A co-simulation process was undertaken to evaluate the decoder’s performance-based on signal-to-noise ratio (SNR) and bit error rate (BER). The co-simulation process utilizes two software components: MATLAB/Simulink r2022b handles all the blocks of the communication system, incorporating the AWGN model for flexibility and future modifications, whereas the HDL simulator (such as Vivado, ModelSim, or Quartus) describes the decoding process.

3. LDPC Codes in 5G-NR

LDPC codes have been adopted by 5G standards because of their remarkable error correction performance for high codeword lengths and built-in parallelism for hardware implementation [16]. They specify a sparse M × N Parity-Check Matrix (PCM) H that contains a much smaller number of 1s compared to 0 s [17]. For Hi, j represents the i-th column and j-th row of H, with N − M = K information bits and M parity bits, where the code rate is denoted as R = K/N. Furthermore, N and M represent the number of variable nodes (VNs) and check nodes (CNs), respectively. The j-th column represents the j-th VN (vj), and the i-th row represents the i-th CN (ci) [18].

Considering C = [x1, x2, …, xN], where xi ϵ [0, 1], C is a codeword if and only if

H · C^T = 1

(1)

The weight (dci, dvi) is defined as the number of 1s within the rows and columns, respectively. The LDPC codes are classified into two categories; a regular code is when both dci and dvi are constant, otherwise, it is characterized as an irregular code [19].

During each iteration, the sum-product algorithm (SPA) [20] computes the extrinsic information of each node using the data received from their connected nodes.

l_n = log(P_r(x_i = 0/r_i)/P_r(x_i = 1/r_i)) = 2Y_n/σ²

(2)

The a priori data (Y_n) refer to the received information (r_i) that represents the decoder input. The a posteriori (l_n) is the updated information, based on belief propagation according to the probabilities of the Log-Likelihood Ratio (LLRs) [11,21]. Next, the CN units compute the new soft information based on the following equation:

f(x) = log tanh(|x|/2)

(3)

The VN units update the LLRs coming from the corresponding CNs as follows:

VN(Y_i) = Y_i,1 + Y_i,2 + … + Y_i,n

(4)

Then, each VN sends the computed messages again to the corresponding CNs for the next iteration.

The min-sum algorithm (MSA) simplifies the complexity of the sum-product [22,23] by approximating the SPA function (Equation (3)) within the CN process into the minimum function:

CN(Y_i) = П(sgn(Y_i) · min(|Y_i|))

(5)

There have been numerous updates made to the MS algorithm, including Offset MS (OMS) and Adapted MS (AMS). The enhanced MS algorithms diminish the overestimation of message magnitudes [11,12].

The LDPC codes in conformity with 5G standards recognize a significant breakthrough relating to decoding performances and the length of transmitted data [24,25]. They constitute a family of QC-LDPC codes, which can be described by the use of protograph codes [26,27].

A protograph code is defined by its matrix Hp = Mp × Np and its expansion factor Z [28,29,30]. The values of the lifting size (Z) fall within an integer range (2 ≤ Z ≤ 384). The entries (Hp(i,j)) of the matrix Hp would be from −1 to Z − 1. Each entry of the matrix is expanded as zeros Z × Z binary submatrix for (Hp(i,j)) = −1, and the identity Z × Z matrix is shifted by (Hp(i,j)) for positive values [31,32].

Following the expansion of Hp, the LDPC matrix becomes H = M (Mp × Z) × N (Np × Z) [33,34]. The 5G standards indicate two base graphs:

BG1 = 46 × 68, used in scenarios requiring high throughput [24,35].

BG2 = 42 × 52, which is used for applications with lower throughput [12,35].

The structures of the two base matrices are presented (see Figure 2).

For both base graphs, the block “A” corresponds to the information (message) bits, while “B” has the double diagonal structure that assigns the encoding process, and “C” is an all-zeros matrix. The extension matrices “D” (message bits) and “E” (parity bits) support incremental redundancy requests [36,37].

Figure 3 provides a comparative analysis of BG1 and BG2, clarifying their operational characteristics within communication systems. By contrasting these base graphs, key performance indicators such as achievable encoding rates (R) and supported message bit sizes (K) can be determined, aiding in the selection of optimal parameters for specific coding applications.

4. Proposed 5G-NR Decoder Architecture

Within this section, we introduce our innovative decoder micro-architecture that redefines the landscape of the IMT-2020 (5G-NR) wireless standards. Our design not only offers unparalleled flexibility, reduced latency, and low hardware requirements, but also achieves an unprecedented level of throughput, surpassing all prior endeavors in the field. The proposed design exhibits unparalleled versatility, seamlessly accommodating a wide spectrum of 5G applications ranging from immersing VR (virtual reality) experiences and cutting-edge AR (augmented reality) technologies to the integration of smart homes and cities, as well as the automation needs of industrial sectors.

4.1. Comprehensive Decoder Architecture

The decoder is based on the first base graph (BG1). As previously mentioned, the entries of the base matrix vary within the range −1 ≤ Hp(i,j) ≤ 383 [38,39,40].

The first 22 columns of BG1 entries correspond to the message bits and the following 46 correspond to parity bits. The rate matching determines how many parity bits should be added to the message bits to accomplish the decoding process by applications and their needed performance. Using the maximum expansion factor, and after the expansion of the matrix, this architecture affords the maximum information length in 5G-NR 8448-bits (22 × Z) [41,42]. A simplified schematic of the architecture is presented (see Figure 4). To provide the decoder with the channel’s received LLRs during initialization in the first iteration, the control unit’s In-Adr output sends a binary “1” to the “2:1Mux” (see Figure 4). After the first iteration, In-Adr provides a binary “0” to the “2:1Mux” for the subsequent decoding iterations of the processed frame, until the correction is carried out or a maximum number of iterations is achieved. The same process is repeated for the next frames coming from the channel. The second output of the control unit is the Lyr-Ctrl, which indicates the current processing layer for all the blocks.

After being supplied into the decoder, the received LLRs are separated using a read-network into treated and raw data corresponding to non −1s and −1s entries of the base graph, respectively, based on the current processes row (layer). The row weight dc deviates between dcmin = 3 and dcmax = 19; therefore, the treated data are passed using 19 “Mp:1Mux” during each layer process. The raw data are simultaneously sent by several (Np-3) “Mp:1Mux” directly to the write-network so that they can be concatenated with the processed data after the layer decoding is complete.

Following the read network, the (19 × Z) LLRs are handled by the dcmax shifting blocks. The construction of the shifting blocks is based on a new particular method that involves assembling a (‘Z’ by ‘b’) matrix of “2:1Mux” with Z ≤ 2b. The shifting blocks obtain the base graph entries through the input LC after they are converted to binary addresses using the binary conversion block. The matrix [Z × b] “2:1Mux” accomplishes the shifting of every 384 LLR sequence by addressing the “2:1Mux” with the converted LC entries. Similar steps are taken for the shift-back blocks, while the multiplexers contained therein are managed by the minus circuit that subtracts the base graph’s elements from the expansion factor (Z−Hp(i,j)).

Before the shift-back blocks and immediately after the shifting blocks, the data proceed along their path to the processing units. The recorded check node output values of the same layer from the previous iterations are received from the MS-mem and subtracted from the current data values (received LLRs) via a tree of dcmax subs-units, each of which has Z subtractors. It must be noted that the data do not change throughout the subs-unit blocks during the first iteration since there is no data stored in memory. The internal architecture of the MINU block is discussed in the following subsection where the subs-unit blocks outputs take place to find the two minimums. According to MSA, the block yields the first min instead of all the other values and then replaces the first min value with the second min. Each block of the dcmax add-unit accommodates Z adders, so it calculates the summation of MINU and subs-unit outputs to determine the processed LLRs. The write-network collects both the processed and raw data along with two different demultiplexer trees (1:Mp Demux), based on the locations of non-1 and −1 entries in the base graph, to store in memory for future decoding layers.

The decoder architecture requires only two principal memories. First, the MS-mem block stores the MINU outputs at the end of each decoding layer to be used for the subunit subtraction. It consists of several Mp memory subblocks. Every subblock corresponds to a layer in the base matrix. Therefore, each subblock is designed according to the weight of the convenient row. In the base graph, the first four layers’ weights are dc = 19, so they require 19 sub-memories each, while the fifth layer weighs 3, so it requires 3 sub-memories. Furthermore, each sub-memory contains Z memory locations. Then, the Lay-Mem block comprises Np memory banks of Z units to store the updated data after each layer process.

4.2. MINU Processing Unit

The MINU processing unit receives Z sequences of dcmax values. Thus, it covers Z check node (CN) units, where each one processes 19 values to find the two minimums.

The CN unit structure is presented (see Figure 5). Each of the 384 CNs within the MINU is constructed from the SOLL unit and an output selector that organizes the two minimums in their positions according to the index of Min1. Every CN unit input is regulated by a “2:1Mux”, which supplies a maximum stored value to complete its 19 inputs for the layers of a weight smaller than dcmax.

The SOLL unit performs parallel computations of the first and second minimums (Min1 and Min2), as well as the index of the first minimum, while also indicating the original sign of each LLR and its product. Moreover, the process involves only (2 × dcmax-3) comparison blocks. With BG1 and the maximum codeword length, the SOLL approach requires only 35 comparison blocks for every CN unit. This method involves conducting two types of comparisons. Initially, the MMB evaluates and sorts two inputs, assigning the lesser and greater values to the corresponding ‘S’ and ‘B’ outputs, respectively. Subsequently, MB determines the minimum value among the ‘B’ outputs from the MMB blocks, with the MB having a single output ‘S’ which represents the second minimum output of the SOLL unit after the comparison is complete.

After the MMB blocks have completed their comparison operation, the SOLL unit assigns the smallest value between the ‘S’ outputs of MMB as the first minimum output. Additionally, each MMB block indicates the position of the smaller values, with the ‘L’ output being assigned binary ‘0’ if the left input is smaller and ‘1’ if the right input is smaller. A tree of “2:1Mux” is then used to generate an address, with the ‘L’ outputs of the MMB blocks being used to address the tree and identify the min1-indexed position (see Figure 6).

5. Results

The simulation results unveil a remarkable enhancement in the decoder’s ability to tackle 5G-NR applications, surpassing the performance of all previous studies [11,12,13,14,39,43] in multiple dimensions. Not only do our results showcase a superior performance in terms of the number of iterations and BER (bit error rate) analysis, but they also outshine earlier studies regarding handling extended codeword lengths.

Our decoder’s baseline architecture (Z = 8, R = 2/3) was modeled in Simulink, converted to VHDL, and then updated to the highest codeword length in 5G-NR (Z = 384, R = 1/3) with the intent of FPGA implementation.

Table 1. Comparison of the proposed 5G-NR LDPC decoder with the state-of-the-art.

	This Study		[11]	[12]	[13]	[14]	[39]	[43]
	Model 1	Model 2
Expansion factor	384	384	384	104	32	384	384	-
Rate	1/3	2/3	1/3	2/3	4/5	1/2	1/3	1/2
SNR (dB)	1.7 dB	2.9 dB	-	-	4 dB	-	2.4 dB	-
Codeword length	26,112	13,440	26,112	3432	1280	16,128	26,112	12
Information length	8448	8448	8448	2288	-	8448	8448	-
Number of iterations	4	6	10	15	20	20	15	10
Decoding algorithm	MS	MS	OMS	AMS	SMS	MS	MS	MS
Matrix size	46 × 68	13 × 35	46 × 68	13 × 35		22 × 44		-
Decoding parallelism	Fully	Fully	Fully	Partially		Partially		Partially
Standard	5G-NR	5G-NR	5G-NR	5G-NR		5G-NR		4G-LTE

presents the simulation outcomes of the enhanced architecture (Z = 384) in comparison to prior works, showcasing two codeword rates of 2/3 and 1/3. The rate 1/3 (model 1) exhibits the best performance compared to 2/3 (model 2) because it offers all BG1 entries and uses the maximum number of parity bits. However, the rate of 2/3 provides fewer parity bits, reducing hardware complexity for certain applications such as live streaming.

6. Discussion

It should also be noted that the maximum number of iterations is improved over previous designs in 5G-NR and 4G-LTE. Model 1 can be compared to the design in [11] because it has the same decoder parameters. In particular, our design significantly reduces latency with six iterations of improvements and up to a 0.2 dB (for BER = 2.10⁻³) SNR increase (see Figure 7a). The rate 2/3 was not simulated for the maximum expansion factor in previous studies, and therefore we are providing an estimated comparison with references [12,14]. In [12], a rate of 2/3 was used with an expansion factor of Z = 104, while in [14], they used a rate of 1/2 which was expected to perform better than 2/3. Despite this, our design achieved an SNR performance gain of up to 0.2 dB compared to [14] and 0.6 dB compared to [12] for BER = 2.10⁻² (see Figure 7b). Furthermore, we have achieved a remarkable reduction in the number of iterations, bringing it down to 6, as opposed to 15 and 20 iterations found in references [12,14], respectively (see Table 1). It is noteworthy that our study has simulated the maximum attainable codeword length for a rate of 2/3.

The previously discussed decoder simulation results were obtained using the MS algorithm. The AMS and OMS algorithms are known to outperform the MS algorithm because they tend to overestimate LLR values. However, this issue was not a significant challenge in our work, and due to the small number of iterations, the correction process was achieved before the overestimation became a concern.

7. Conclusions

This paper presents an innovative architecture for a layered QC-LDPC decoder that conforms to the 5G-NR standards. Our proposed design enables the processing of the maximum information length in 5G-NR. The decoder features a low latency, flexible model design, and reduced complexity due to the read/write networks, check node units, and shifting block designs. This research has also demonstrated the efficiency of the modified SOLL method for 5G-NR, highlighting its convenience and demonstrating positive outcomes. This shows significant improvements in SNR analysis and the number of iterations when compared to previous works. Moreover, the design supports a wide range of expansion factors and base matrices and can be easily modified to accommodate different code rates. As a next step, we plan to implement the decoder on FPGA; the synthesis process has already commenced. The promising results thus far reinforce our design’s potential for practical IMT-2020 applications.