Two-Phase Interleaved Boost Converter with ZVT Turn-On for Main Switches and ZCS Turn-Off for Auxiliary Switches Based on One Resonant Loop

Abstract

A two-phase interleaved boost converter with soft switching is proposed herein. By means of only one auxiliary circuit with two auxiliary switches having zero-current switching (ZCS) turn-on, two main switches are switched on with zero-voltage transition (ZVT) to enhance the overall efficiency. Moreover, a current-balancing circuit with a no current-balancing bus is utilized to render the load current extracted from the two phases as even as possible, so that the system stability is upgraded. In such a study, this converter, having the input of $24\mathrm{V}\pm 10\%$ and the rated output of 36V/6A, was employed to demonstrate the effectiveness of such a converter by experiment.

1. Introduction

As well known, the switching power supply is widely used today. This is because of its small volume, high efficiency, etc. However, it has some disadvantages due to its hard switching, such as high switching loss, large voltage/current stress and strong electromagnetic interference.

To overcome the demerits mentioned above, the quasi-resonant converter (QRC) [1,2,3,4,5,6] has been investigated since 1980, mainly on the condition that the voltage/current waveform is sinusoidal. This converter contains the resonant inductor in a series with the switch or the diode, and hence resonates with the switch parasitic capacitor or the diode parasitic capacitor so that the zero-voltage switching (ZVS) during the turn-on period or the zero-current switching (ZCS) during the turn-off period can be realized. However, this inductor locates on the path of the main power stage such that the high voltage/current on/in the switch or diode will occur and hence the circulation current is unavoidable, thereby creating a large conduction loss. Moreover, the resonant energy comes from the input and the load such that the soft switching can be achieved only for some input voltage range as well as some load range.

To overcome the demerits of QRCs, a resonant network paralleled with the main power stage path was developed. Some derived structures were presented, such as active clamp [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21], zero-voltage transition (ZVT) and zero-current transition (ZCT) [22,23,24,25,26,27,28,29,30,31,32,33]. The last two structures use resonant networks, which will make the main switch have ZVS and ZCS according to the auxiliary switch. Furthermore, the voltage on the switch and the current in the switch are of sinusoidal form. By doing so, the voltage stress and current stress for the switch are effectively alleviated, causing the circulation current to be small and hence the unavoidable conduction loss to be reduced. Moreover, the required resonant energy is not all determined by the input voltage and output load. Accordingly, in design of the resonant parameters for soft switching all over the range of input voltage and output load, only the minimum input voltage and the maximum output load were considered.

On the other hand, to increase the output current as well as to upgrade the corresponding overall efficiency, the multiphase converter along with interleaved control are commonly utilized. Since the AC components of the inductor currents for multiple phases are cancelled with each other to some extent, not only is the output current ripple thereby decreased but also the frequency of the output current ripple is increased. Accordingly, not only will the design of the required filter be easier, but the corresponding size will also be smaller. Generally, the total loss generated from multiple phases will be smaller than that generated from one phase. Furthermore, the soft switching multiphase converter is proposed so that the overall efficiency is further upgraded. The literature [34,35,36,37] takes multiple phases with the accompanying number of auxiliary resonance circuits, thereby resulting in increasing the number of components and hence increasing not only the conduction loss but also the cost. In the literature [36], the two-phase converter utilizes the same auxiliary resonant circuit. However, only the ZVS is employed so that the improvement in efficiency is restricted. In the literature [37], a two-phase converter adopts one snubber circuit to force the main switches to realize soft switching. Nevertheless, the resonant inductor is put on the power path, thus increasing the conduction loss. In addition, since there are differences in component features and line impedance between the two phases, the current-balancing control will be required. Regarding current balance, there are two types of current-balancing control strategies. One method is passive; the other method is active. The former adopts differential-mode transformers or capacitors or both to do current balance [38,39,40,41], while the latter consists of current regulators and sensors to do current balance [42,43,44,45,46].

Accordingly, only one resonant circuit, which is comprised of relatively few elements as compared with [47] is presented and imposed on a two-phase interleaved boost converter to force two main switches to have ZVT turn-on and two auxiliary switches to have ZCS turn-off. Moreover, as the switches operate under soft switching, the output current ripple is not affected such that the life of the capacitor can be prolonged. As for the current balance, a simple method, based on digital control with no current-balancing bus, is proposed to render the load current evenly distributed between the two phases.

2. Proposed Converter

Figure 1 shows the proposed converter containing a traditional two-phase boost converter with the parasitic diodes D_S1 and D_S2 and parasitic capacitors C_S1 and C_S2 for the main switches S₁ and S₂, respectively, the output didoes D₁ and D₂, and one output capacitor C_o, along with a resonant circuit, which is composed of only one resonant inductor L_r, only one resonant capacitor C_r, one resonant diode D_r, and two auxiliary switches S_a and S_b with parasitic diodes D_Sa and D_Sb and parasitic capacitors C_Sa and C_Sb, respectively. Moreover, the output resistor is indicated by R.

3. Operation Behavior

Before tackling this section, there are some assumptions and symbols to be given as below: (i) all the elements are viewed as ideal except the parasitic diodes and capacitors for the main switches and auxiliary switches; (ii) the input inductors can be regarded as current sources represented by I_L1 and I_L2; (iii) the output capacitor can be viewed as a voltage source V_o; (iv) this converter operates in the continuous current mode (CCM); (v) the gate-driving signals for the switches S₁, S₂, S_a and S_b are denoted by v_g1, v_g2, v_ga and v_gb, respectively; (vi) the voltages across the switches S₁, S₂, S_a and S_b are signified by v_S1, v_S2, v_Sa and v_Sb, respectively; (vii) the currents flowing through the switches S₁, S₂, S_a and S_b are represented by i_S1, i_S2, i_Sa and i_Sb, respectively; (viii) the currents flowing through D₁, D₂ and D_r are indicated by i_D1, i_D2 and i_Dr, respectively; (ix) the current flowing through L_r and the voltage across C_r are denoted by i_Lr and v_Cr, respectively.

According to the aforementioned assumptions and symbols, the converter in Figure 2 is an equivalent for that in Figure 1. In Figure 3, there are sixteen operation modes in this circuit. Since such a converter is controlled by interleave, namely, the gate-driving signal v_g2 shifted by 180 degrees from the gate-driving signal v_g1, the behavior of the first eight operation modes is identical to that of the last eight operation modes. Hence, only the first eight operation modes are illustrated.

Mode 1: $\left[{\mathit{t}}_0\le t\le t_1\right]$. As in Figure 4, the auxiliary switch S_a is switched on at the instant t₀. Since the output diodes D₁ and D₂ are also switched on, thereby making the parasitic capacitor of S_b, called Cs_b, abruptly discharged to zero. Meanwhile, the output voltage V_o was imposed on the resonant inductor L_r and the resonant capacitor C_r, thereby making L_r and C_r resonate. Moreover, the current i_Sa is equal to i_Lr and both are increasing, but the current i_D1 begins to fall. As soon as i_Lr is equal to I_L1, namely i_Lr(t₁) = I_L1, this mode ends. During such a mode, the accompanying equations are described as below:

$$\{\begin{array}{l}{i}_{Lr}(t)=\frac{(V_o-v_{Cr}(t_0))}{Z_1}\sin ({\mathsf{\omega }}_1(t-t_0))+i_{Lr}(t_0)\cos ({\mathsf{\omega }}_1(t-t_0))\\ \\ v_{Cr}(t)=V_o-(V_o-v_{Cr}(t_0))\cos ({\mathsf{\omega }}_1(t-t_0))+i_{Lr}(t_0)Z_1\sin ({\mathsf{\omega }}_1(t-t_0))\end{array}$$

(1)

where

$${\mathsf{\omega }}_1=\sqrt{\frac{1}{L_r{C}_r}}\mathrm{and}{Z}_1=\sqrt{\frac{L_r}{C_r}}$$

(2)

At the instant t₀, i_Lr(t₀) is close to zero and v_Cr(t₀) is much smaller than V_o, so the expression of the current i_Lr from Equation (1) can be approximately represented by

$$i_{Lr}(t)=\frac{V_o}{Z_1}\sin ({\mathsf{\omega }}_1(t-t_0))$$

(3)

From Equation (3), the elapsed time for this mode can be obtained to be

$$(t_1-t_0)=\frac{1}{{\mathsf{\omega }}_1}{\sin }^{-1}\left[\frac{I_{L1}{Z}_1}{V_o}\right]$$

(4)

Mode 2: $\left[t_1\le t\le t_2\right]$. As in Figure 5, the output diode D₁ is switched off. Meanwhile, the current I_L2 charges the parasitic capacitor of the auxiliary switch S_b, called C_Sb, to the output voltage V_o abruptly, while the resonant inductor L_r resonates with the resonant capacitor C_r in series with the parasitic capacitor of the main switch S₁, called C_S1. Since the current i_Sa is equal to i_Lr, the current I_L1 is the sum of the currents of i_Lr and i_S1. Therefore, I_Lr will force C_S1 to discharge, thereby causing the voltage across S₁, called v_S1, to be dropped. As soon as v_S1 is zero, this mode ends. During such a mode, the accompanying equations are described as below:

$$\{\begin{array}{ll}\hfill i_{Lr}(t)=& \frac{V_1}{Z_2}\sin ({\mathsf{\omega }}_2(t-t_1))+I_1\cos ({\mathsf{\omega }}_2(t-t_1))-I_1+i_{Lr}(t_1)\hfill \\ \hfill v_{S1}(t)=& \frac{C}{C_{S1}}(V_1\cos ({\mathsf{\omega }}_2(t-t_1))-I_1{Z}_2\sin ({\mathsf{\omega }}_2(t-t_1))-V_1)+\hfill \\ & \frac{I_{L1}}{C_r+C_{S1}}(t-t_1)+V_o\hfill \\ \hfill v_{Cr}(t)=& -\frac{C}{C_r}(V_1\cos ({\mathsf{\omega }}_2(t-t_1))-I_1{Z}_2\sin ({\mathsf{\omega }}_2(t-t_1))-V_1)+\hfill \\ & \frac{I_{L1}}{C_r+C_{S1}}(t-t_1)+v_{Cr}(t_1)\hfill \end{array}$$

(5)

where

$$\begin{array}{l}C=\frac{C_r{C}_{S1}}{C_r+C_{S1}},{\mathsf{\omega }}_2=\sqrt{\frac{1}{L_{r}C}}=\sqrt{\frac{C_r+C_{S1}}{L_r{C}_r{C}_{S1}}}\\ \\ Z_2=\sqrt{\frac{L_r}{C}}=\sqrt{\frac{L_r(C_{S1}+C_r)}{C_r{C}_{S1}}}\\ \\ V_1=V_o-v_{Cr}(t_1),I_1=i_{Lr}(t_1)-\frac{C}{C_{S1}}{I}_{L1}\end{array}$$

(6)

As the voltage v_S1 is identical to the voltage v_Cr, the resonant current i_Lr, which flows through the auxiliary switch S_a, will be a maximum value, called I_Lr-peak, which can be expressed as

$$I_{Lr-peak}=\frac{\sqrt{V_1^2+{(I_1{Z}_2)}^2}}{Z_2}+\frac{C}{C_S{}_1}{I}_{L1}$$

(7)

Mode 3: $\left[t_2\le t\le t_3\right]$. As in Figure 6, the voltage across S₁, called v_S1, is zero due to the parasitic diode of the switch S₁, called D_S1, conducting the current. Therefore, as S₁ is switched on during this mode, S₁ has ZVT turn-on without conduction. Since L_r resonates with C_r, the voltage on L_r is identical to the minus voltage across C_r, thereby causing i_Lr to begin to drop. Moreover, the current I_L1 is the sum of the currents of i_Lr, i_S1 and i_Dr. As soon as i_Lr drops to I_L1, this mode ends. During such a mode, the accompanying equations are described as below:

$$\{\begin{array}{l}{i}_{Lr}(t)=i_{Lr}(t_2)\cos ({\mathsf{\omega }}_1(t-t_2))-\frac{v_{Cr}(t_2)}{Z_1}\sin ({\mathsf{\omega }}_1(t-t_2))\\ \\ v_{Cr}(t)=v_{Cr}(t_2)\cos ({\mathsf{\omega }}_1(t-t_2))+i_{Lr}(t_2)Z_1\sin ({\mathsf{\omega }}_1(t-t_2))\end{array}$$

(8)

Mode 4: $\left[t_3\le t\le t_4\right]$. As in Figure 7, the current i_Lr is equal to the current I_L1 at the instant t₃, and hence both the currents i_S1 and i_Dr are zero, thereby causing the diodes D_S1 and D_r to be switched off. During this mode, the main switch S₁ is switched on with conduction. Meanwhile, the resonant inductor L_r still resonates with the resonant capacitor C_r, and i_Lr is still reduced, but i_S1 increases from zero gradually. Moreover, the current I_L1 is the sum of the currents i_S1 and i_Sa, and i_Sa is identical to i_Lr. As i_Lr drops to zero, the auxiliary switch S_a is switched off, thereby causing S_a to operate under ZCS turn-off. As soon as i_Lr is identical to zero, this mode ends.

Mode 5: $\left[t_4\le t\le t_5\right]$. As in Figure 8, the main switch S₁ remains switched on. During this mode, the resonant inductor L_r still keeps resonating with the resonant capacitor C_r, and the current i_Lr increases in the negative direction and flows through S₁, thereby making the parasitic diode of the auxiliary switch S_a, called D_Sa, switched on. Moreover, as soon as i_Lr goes from the minimum value to zero, this mode ends.

Mode 6: $\left[t_5\le t\le t_6\right]$. As in Figure 9, the main switch S₁ still remains switched on. During this mode, the resonant inductor L_r, with its current in the positive direction, resonates with the resonant capacitor C_r, thereby making the resonant diode D_r switched on and hence a resonant loop is generated. Moreover, the current in the main switch S₁, called i_S1, is identical to the current I_L1. As soon as S₁ is switched off, this mode ends.

Mode 7: $\left[t_6\le t\le t_7\right]$. As in Figure 10, the main switch S₁ is switched off at the instant t₆. During this mode, the current I_L1 charges the parasitic capacitor of the main switch S₁, called C_S1, and the parasitic capacitor of the auxiliary switch S_a, called C_Sa, causing the voltage across S₁ to be increased. Moreover, the resonant loop is the same as that displayed in mode 6. As soon as the voltage v_S1 is identical to the output voltage V_o, this mode ends.

Mode 8: $\left[t_7\le t\le t_8\right]$. As in Figure 11, during this mode, all the switches are switched off, but only the output diode D₁ conducts with the current i_D1 identical to the current I_L1. Moreover, the resonant loop is the same as that displayed in mode 7. As soon as the main switch S_b is switched on, this mode ends, and hence the other phase begins to work, coming back to state 1 until this cycle is finished. After this, the next period will be repeated.

4. Current Control Strategy

Figure 12 displays the proposed current-balancing control strategy. The duty cycle of the gate-driving signal v_g1 for the first phase after the first pulse-width modulation (PWM) generator is tuned to get the wanted output voltage V_o, based on the voltage loop with the controller G_c1(z) having the voltage command reference V_ref and the digital sensed voltage $V_o^{\prime }$, which is obtained from the sensed voltage $v_o^{\prime }$ by the voltage divider with a gain k and the first analog-to-digital converter (ADC1). Meanwhile, the sensed current of the first phase, named $i_{L1}^{\prime }$, is sent to ADC2, to get the digital sensed current $I_{L1}^{\prime }$, which will be used as the current command reference for the current-balancing loop with the controller G_c2(z) having the digital sensed current $I_{L2}^{\prime }$ from the sensed current of the second phase, named $i_{L2}^{\prime }$, after ADC3, so that the duty cycle of the gate-driving signal v_g2 for the second phase after the second PWM generator is automatically tuned to force the input current to be evenly distributed between the two phases and hence the load current balancing between the two phases can be realized.

Afterwards, the current-balancing behavior is described below. First, by assuming that the output power (P_o) is identical to the input power (P_i), the output current (I_o) is identical to the product of the DC inductor current (I_L) and one minus duty cycle (1–D). Therefore, if I_L = I_L1 + I_L2 and I_o = I_o1 + I_o2, then under I_L1 = I_L2 = 0.5I_L, I_o = 0.5I_L1 (1–D_a) + 0.5I_L2 (1–D_b), where D_a is the duty cycle of v_g1 generated from the controller G_c1 (z) and D_b is the duty cycle of v_g2 generated from the controller G_c2 (z). For example, if I_o1 is larger than I_o2, then D_a will be increased and D_b will be decreased, thereby causing I_o1 to go down and I_o2 to go up. Eventually, both I_o1 and I_o2 are equal to 0.5 I_o, making the current balancing realized.

5. Design Considerations

Prior to designing the key parameters of this converter, the associated specifications of the system are shown in

Table 1. System Specifications (CCM: continuous current mode)

System Parameters	Specifications
Operating Mode	CCM
Input Voltage	24 V
Switching Frequency	50 kHz
Output Voltage	36 V
Rated Output Power/Current	216W/6A
Min. Output Power/Current	21.6W/0.6A

.

5.1. Design of L₁ and L₂

Since this converter is a two-phase structure, the values of the input inductors can be approximately decided by a single phase with the rated output power/current reduced by a factor of 2. Moreover, the converter operates in the CCM, so the minimum value of L₁, called L_{1, min}, can be represented by

$$L_1\ge \frac{{RD}_a{(1-D_a)}^2{T}_s}{2}$$

(9)

where R is the output resistor, whose value is located between 12 Ω and 120 Ω.

Based on (9), the maximum duty cycle is obtained to be 0.33, which corresponds to the input voltage of 24 V and the output voltage of 36 V. Therefore, L_{1, min} = 178 μH after some calculations, and eventually the value of L₁ is chosen to be 200 μH, which is also for the value of L₂.

5.2. Design of C_o

Regarding the output capacitor design, Equation (11) is used on condition that the maximum output voltage ripple is equal to 20% of the output voltage V_o, the value of R is 12Ω, T_s is 20 μs, D = 0.33, and V_o = 36 V. After some calculations, the value of C_o is larger than 275 μF. Eventually, a 470 μF capacitor is chosen, and this is because the value of the electrolytic capacitor will be decreased if the frequency is increased:

$$\Delta v_o=\Delta v_{Co}=\frac{1}{C_o}{\displaystyle \int {}_0^{D{T}_s}{i}_{Co}dt}=\frac{I_{o}D{T}_s}{C_o}=\frac{V_{o}D{T}_s}{R{C}_o}$$

(10)

5.3. Design of L_r and C_r

The proposed soft switching structure is based on the turn-on of the auxiliary switch S_a/ prior to the turn-on of the main switch S₁, so that the resonant inductor L_r resonates with the resonant capacitor C_r and the parasitic capacitor of S₁, called C_S1. As the current i_Lr is larger than the current I_L1, the voltage across S₁, called v_S1, drops to zero abruptly, the parasitic diode of S₁, called D_S1, is switched on, and afterwards S₁ is switched on with ZVT. To avoid the converter operating abnormally, the time interval, used to execute resonance, is not too long. Therefore, the turn-on time interval of the auxiliary switch S_a is chosen to be one tenth of the switching period T_s, about 2 μs. Meanwhile, to reduce the effect of i_Lr on S₁, the turn-on instant of S_a is prior to the turn-on instant of S₁ by one fifth of the turn-on time interval of S_a, namely 0.4 μs. Hence, to obtain the soft switching of S₁, the time interval for v_S1 to drop to zero is chosen to be 0.5 μs or less as shown in (11):

$$(t_1-t_0)+(t_2-t_1)\le 0.5 \mathsf{\mu }\mathrm{s}$$

(11)

where during the time interval between t₁ and t₀, the resonant current i_Lr rises from zero to the current I_L1, whereas during the time interval between t₂ and t₁, the voltage across S₁ drops from the output voltage V_o to zero.

In Equation (11), the former time interval was quite significantly larger than the latter time interval, so the former time interval at a rated load is set at half of the time interval between the turn-on instant of S_a and the turn-on instant of S₁, namely 0.2 μs, so as to make sure that S₁ can operate under ZVT turn-on within the time interval of 0.5 μs. Therefore, the following equation can be obtained to be:

$$(t_1-t_0)=\frac{1}{{\mathsf{\omega }}_1}{\sin }^{-1}\left[\frac{I_{L1}{Z}_1}{V_o}\right]=0.2 \mathsf{\mu }s$$

(12)

To make sure that the resonant period of the auxiliary circuit, called T₁, can make the ZVS turn-on of the main switches S₁ and S₂ happen within the switching period T_s, T₁ is set at 0.75 T_s, equal to 7.5 μs, and afterwards, based on (12), the values of L_r and C_r can be determined to be 1.25 μH and 1.14 μF.

6. Experimental Results

To verify the performance of the proposed soft switching control strategy, the waveforms of the converter operating at minimum and rated loads are given. Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22 and Figure 23 are for the converter operating at a minimum load, whereas Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, Figure 33 and Figure 34 are for the converter operating at a rated load. Figure 13 displays v_g1 and v_g2 for S₁ and S₂, respectively. Figure 14 displays v_g1 and v_ga for S₁ and S_a, respectively, whereas Figure 15 shows v_g2 and v_gb for S₂ and S_b, respectively. Figure 16 displays i_Lr and v_Cr. Figure 17 shows v_S1, i_L1 and i_Lr. Figure 18 displays v_S2, i_L2 and i_Lr. Figure 19 shows v_g1, v_S1 and i_S1. Figure 20 displays v_g2, v_S2 and i_S2. Figure 21 displays v_ga, v_Sa and i_Sa. Figure 22 displays v_gb, v_Sb and i_Sb. Figure 23 shows the current balancing between the two phases. As for Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, Figure 33 and Figure 34, the measured items are the same as those for Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22 and Figure 23.

From Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23 and Figure 24, we can see that v_g2 is shifted from v_g1 by 180 degrees. From Figure 14 and Figure 25, S_a is switched on before S₁ is switched on, whereas from Figure 15 and Figure 26, we can see that S_b is switched on before S₂ is switched on. In Figure 16 and Figure 27, we can see that L_r resonates with C_r. From Figure 17 and Figure 28, we can see that as S_a is switched on prior to S₁, i_Lr is rising abruptly and then is larger than i_L1, causing the voltage across C_S1 to be dropped to zero and then S₁ to be switched on with ZVT, whereas from Figure 18 and Figure 29, we can see that as S_b is switched on prior to S₂, i_Lr is rising abruptly and then is larger than i_L2, causing the voltage across C_S2 to be dropped to zero and then S₂ to be switched on with ZVT. From Figure 19 and Figure 30, we can see that S₁ has ZVT turn-on, whereas from Figure 20 and Figure 31, we can see that S₂ has ZVT turn-on. From Figure 21 and Figure 32, we can see that due to resonance, i_Sa is dropped to zero and then clamped at zero, thereby making S_a switched off with ZCS, whereas from Figure 22 and Figure 33, we can see that due to resonance, i_Sb is dropped to zero and then clamped at zero, thereby making S_b switched off with ZCS. From Figure 23 and Figure 34, we can see that the current balancing between the two phases performs well for any load.

From Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35, we can know that all over the load range, both the main switches have ZVT turn-on and both the auxiliary switches have ZCS turn-off.

7. Comparisons

In

Table 2. Comparisons between the circuits from [37], [47] and the proposed circuits (ZVS: zero-voltage switching; ZVT: zero-voltage transition; ZCS: zero-current switching; ZCT: zero-current transition).

Comparisons	Resonant Count	Soft Switching Type for Main Switches								Overall Efficiency
		Turn-On				Turn-Off
	No.	ZVS	ZVT	ZCS	ZCT	ZVS	ZVT	ZCS	ZCT	Min.	Max.
[37]	5				*		*			84%	90%
[47]	7		*						*	91%	93%
Proposed	5		*							94%	96%

The sign * means that the converter possesses this soft switching type.

, the numbers of resonant components are five, seven and five for the circuits from [37] and [47], and the proposed circuits, respectively. The circuit shown in [37] has ZCT turn-on and ZVT turn-off. The circuit displayed in [47] has ZVT turn-on and ZCT turn-off. The proposed circuit has ZVT turn-on. The minimum values of the overall efficiency are 84%, 91% and 94% for the circuits [37] and [47], and the proposed, respectively. The circuit [47] has ZVT turn-on and ZCT turn-off but the number of resonant components is seven, whereas the proposed circuit only has ZVT turn-on, but the number of resonant components is five. In general, the ZVS turn-on or ZVT turn-on is quite important for reducing the switching loss of the metal-oxide-semiconductor field-effect transistor (MOSFET) [48]. Accordingly, the proposed circuit has the best performance among the three.

8. Conclusions

In this paper, to reduce the switching loss as well as to upgrade the overall efficiency, the proposed converter with the main switches S₁ and S₂ had ZVT turn-on as well as the auxiliary switches S_a and S_b having ZCS turn-off. All the soft switching operations are achieved based on only one resonant loop. The ZVT behavior is realized by switching on the auxiliary switch S_a (or S_b) before the main switch S₁ (or S₂) is switched on, so that the voltage across S₁ (or S₂) is dropped to zero and hence S₁ (or S₂) has an ZVT turn-on. On the other hand, the ZCS behavior was achieved based on the characteristics of the auxiliary circuit, so that S_a and S_b have a ZCS turn-off. From the experimental results, we can know that soft switching can be realized all over the load range. In addition, the current balancing between the two phases is performed well for any load.