Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET

Round 1

Reviewer 1 Report

- The article is interesting, although it is somewhat descriptive. It would be nice to see a brief discussion of the differences in the behavior and properties of the JL and MOS FETs, since all CVCs look very similar.

- It seems to me it would be instructive to give the derivation of the only formula (1) in an appendix.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Dear authors,

First of all I would like to congratulate you for your task on this piece of work. Now then, I have several aspects you should correct. Thus:

- Along the introduction section I miss some explanation about the benefits to use junctionless devices instead of the MOS ones. Which benefits do you expect to obtain to use it? A more detailed explanation of the junctionless devices could help the non-expert reader!

- In the same to help the non-expert reader a schematic of the circuit presented in Fig. 1 will help. Additionally, a layout with the connections of the circuit will help a lot!

- There is a problems with the references are not well corresponded, you should check it.

- Table 1 makes reference to the MOS and JL device dimesions. But it is hard to see if there is some difference between both types. The table should be improved. You mention that the VT is defined when Inds is of 0.1uA, why do you choose this value?

- In line 77 you present the different models (CVT, SRH, AUGER,
and FERMI) used to simulate the device behavior. Why do you choose these models?

- In line 78 you mention a leakage current about 10^-8 A, how you can ensure/prove it? Could you explain it, please?

- In the figure caption of Fig. 2 you finish telling that you use W/L=0.2/0.03 um. What does it mean? Because in the figure, you explain that you change Lg from 20 to 50 nm.

- In line 95 there is a typo mistake: I miss an 's' in "threhold". Check for more typo mistakes, please!!

- Explain in more detail the meaning and relevance of yhe capacitive coupling ratio presented in line 113.

- I missed the figure caption of Fig. 5.

- To complet your work, and thinking on the non-experted or non-familiarity readers, you have to inset a small schematic of both CMOS inverter and SRAM.

-Explain what does Vm mean?

- For a better understanding of the reader Tables 2 & 3 can be substituied by some graphs showing more easiuly the difference between both proposals. Note that SNM is the minimum value of NMh or NMl so you have to choose only the smallest one to be presented. And a graph comparing both proposals could be bettter instead of the two tables.

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

General comments:

The simulated transistors include SiO2 as gate dielectric. At 0.9nm SiO2 thickness what is the gate leakage and is it taken into consideration in the simulation?

The real devices are likely to use a high-k gate dielectric. This will impact the total gate capacitance. Please include a comment on whether the presence of a high-k gate dielectric will change the results of the simulations presentated in this paper.

Minor Comments:

Page 3 line 77 (also in page 6): The Silvaco reference should be [13] instead of [14]

Please explain what the following models are: CVT, SRH, AUGER and FERMI and why they are used.

Is the leakage current sated in page 3 (10^-8A) the off state leakage of the transistor? Would it be better to express it in A/um?

It would be easier to list the parameters of table 1 in alphabetical order.

What is the ngate and pgate material for each type of transistor?

The paragraph at the bottom of page 4 is unclear (lines 103-112). Please re-word it.

Figure 5 caption is missing

Author Response

Please find an attached file.

 

Author Response File: Author Response.pdf