The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology
Round 1
Reviewer 1 Report
1) The authors has use a S2P interface with no address to serve as comparison. However I think that S2P interface with address capability exists in the market, such as TI's SN74LV8153-Q1. Thus, from architecture point of view the addressing method has little novelty. 2) The reset in the Fig. 2c should be reset'? 3) Is there any additional temperature data to demonstrate the S2P work properly under different temperature with the bit rate of 40MHz?
Author Response
First, thank you for the paper review.
We wrote a report based on your comments, so please see the attached file.
Thank you.
Author Response File: 
Author Response.docx
Reviewer 2 Report
The architecture of S2P converter is revised in this manuscript such that 160-bit data is input in a group of 8 bits, addressable by 20 bytes.
The 28 nm CMOS technology is introduced in Sec. 2. It could be emphasized more on the information related to the S2P converter design, such as the effect of transistor speed on the converter performance.
The performance of the S2P converter needs to be characterized clearly. Fig. 7 shows various clock rates. The data waveforms at 20 MHz and 40 MHz appears to be questionable for correct data acquisition.
Author Response
First, thank you for the paper review.
We wrote a report based on your comments, so please see the attached file.
Thank you.
Author Response File: Author Response.docx
Round 2
Reviewer 1 Report
On the 3rd point, I would like to point out that usually the high speed operation the clocks is also limited by the post layout routing capacitance. It will be always good to include post layout simulation if you are not able to reproduce it in lab.
Author Response
Please see the attachment.
Author Response File: Author Response.docx
Reviewer 2 Report
The proposed shift register is focused on addressable design for high-speed control with high-speed clock. Eq. (1) indicates that 28 nm CMOS provides high cutoff frequency for low noise. If not related, this paragraph can be removed. Otherwise, it is suggested to describe clearly.
Judged by the waveforms in Fig. 7, data acquisition at 20 MHz and 40 MHz clocking rates would fail for circuit control. It is inappropriate to claim operation up to 40 MHz. The authors can provide performance comparison with other works.
Author Response
Please see the attachment.
Author Response File: Author Response.docx
Round 3
Reviewer 2 Report
The authors have replied to comments and given a revised manuscript with better clarity.
