Processor-in-the-Loop Architecture Design and Experimental Validation for an Autonomous Racing Vehicle
Abstract
:1. Introduction
2. Method
2.1. Autonomous Vehicle Pipeline and Vehicle Setup
2.1.1. Environment Perception
2.1.2. Path Planning
2.1.3. Vehicle Modeling
2.1.4. Control
2.2. Hardware Implementation and PIL Architecture
3. Results
3.1. Driving Scenarios and Environment Perception
3.2. Processor-in-the-Loop and Simulations Comparison
4. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Parameter | Symbol | Value | Unit |
---|---|---|---|
Mass | 190 | [kg] | |
Moment of Inertia about z-axis | 95.81 | [kgm2] | |
Vehicle wheelbase | 1.525 | [m] | |
Overall length | 2.873 | [m] | |
Front axle distance to CoG | 0.839 | [m] | |
Rear axle distance to CoG | 0.686 | [m] | |
Vehicle track width | 1.4 | [m] | |
Overall width | 1.38 | [m] | |
Height of CoG | 0.242 | [m] | |
Wheel radius | 0.241 | [m] | |
Longitudinal drag area | 2 | [m2] | |
Longitudinal drag coefficient | 0.3 | - | |
Longitudinal lift coefficient | 0.1 | - | |
Longitudinal drag pitch moment | 0.1 | - | |
Maximum power (total vehicle) | 80 | [kW] | |
Motors peak torque | 84 | [Nm] | |
Steering transmission ratio | 4.23 | [-] | |
Maximum energy stored | 6.29 | [kWh] |
Raspberry Pi 4B | Speedgoat Baseline | |
---|---|---|
CPU | Broadcom BCM2711 quad-core Cortex-A72 64-bit SoC @ 1.5 GHz | Intel Celeron 2 GHz 4 cores |
Memory | 4 GB LPDDR4 | 4 GB DDR3 |
EEE 802.11b/g/n/ac wireless | 1 × USB 3.0 and 2 × USB 2.0 | |
Network | Bluetooth 5.0 | Gigabit Ethernet 2 (Intel I210) |
Gigabit Ethernet | ||
I/O | USB, 40-pin GPIO header | 4 × mPCIe |
OS | Debian, Raspberry Pi OS | Simulink Real-Time™ |
Power | 5 V DC via USB-C connector | 8–36 VDC Input Range |
Raspberry | Speedgoat | ||||||
---|---|---|---|---|---|---|---|
Straight | Left Turn | Right Turn | Straight | Left Turn | Right Turn | ||
RMSE | |||||||
MAE | |||||||
RMSE | 1.70 × 10−5 | 1.67 × 10−5 | 0.003 | ||||
MAE | 7.26 × 10−6 | 6.89 × 10−6 |
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Tramacere, E.; Luciani, S.; Feraco, S.; Bonfitto, A.; Amati, N. Processor-in-the-Loop Architecture Design and Experimental Validation for an Autonomous Racing Vehicle. Appl. Sci. 2021, 11, 7225. https://doi.org/10.3390/app11167225
Tramacere E, Luciani S, Feraco S, Bonfitto A, Amati N. Processor-in-the-Loop Architecture Design and Experimental Validation for an Autonomous Racing Vehicle. Applied Sciences. 2021; 11(16):7225. https://doi.org/10.3390/app11167225
Chicago/Turabian StyleTramacere, Eugenio, Sara Luciani, Stefano Feraco, Angelo Bonfitto, and Nicola Amati. 2021. "Processor-in-the-Loop Architecture Design and Experimental Validation for an Autonomous Racing Vehicle" Applied Sciences 11, no. 16: 7225. https://doi.org/10.3390/app11167225
APA StyleTramacere, E., Luciani, S., Feraco, S., Bonfitto, A., & Amati, N. (2021). Processor-in-the-Loop Architecture Design and Experimental Validation for an Autonomous Racing Vehicle. Applied Sciences, 11(16), 7225. https://doi.org/10.3390/app11167225