Luo, J.; Wu, W.; Xing, Q.; Xue, M.; Yu, F.; Ma, Z.
A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches. Appl. Sci. 2022, 12, 12458.
https://doi.org/10.3390/app122312458
AMA Style
Luo J, Wu W, Xing Q, Xue M, Yu F, Ma Z.
A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches. Applied Sciences. 2022; 12(23):12458.
https://doi.org/10.3390/app122312458
Chicago/Turabian Style
Luo, Jifeng, Wenqi Wu, Qianjian Xing, Meiting Xue, Feng Yu, and Zhenguo Ma.
2022. "A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches" Applied Sciences 12, no. 23: 12458.
https://doi.org/10.3390/app122312458
APA Style
Luo, J., Wu, W., Xing, Q., Xue, M., Yu, F., & Ma, Z.
(2022). A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches. Applied Sciences, 12(23), 12458.
https://doi.org/10.3390/app122312458