A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Round 1

Reviewer 1 Report

Authors performed a study on a short review of TSV interconnects with Metrology and Analysis. 

Following revisions must be done before publish as :

The title can be revised as "A short review of Through‐silicon via interconnects: Metrology and Analysis"

It is better if authors give parameters in abstract. 

Graphics are not quality in Fig. 5.

A cconclusion part is needed for the work. 

Some of abbreviations must be explained.

Theory part must be extended.

Then, manuscript can be published. 

Authors performed a study on a short review of TSV interconnects with Metrology and Analysis. 

Following revisions must be done before publish as :

The title can be revised as "A short review of Through‐silicon via interconnects: Metrology and Analysis"

It is better if authors give parameters in abstract. 

Graphics are not quality in Fig. 5.

A cconclusion part is needed for the work. 

Some of abbreviations must be explained.

Theory part must be extended.

Then, manuscript can be published. 

Author Response

TO Reviewer 1:

Thank you for your thorough guidance! I would like to express my sincere gratitude for your comments!

1. The title has been modified according to your opinion.
2. According to your opinion, the Abstract has added some parameters.
3. Figure 5 has been redrawn
4. Conclusion part is added
5. The theory of each part has been expanded and is marked in red.
6. Once again, the abbreviations without full names were checked and corrected.

Reviewer 2 Report

Dear Author,

The manuscript titled A short review of TSV interconnects: Metrology and Analysis have been well analysed and poorly formatted. Even though the paper came perfectly. The following points are against its paper quality

 

1.      Abstract: does not have final results and discussion about the proposed method

2.      Introduction: The introduction part, objective, scope and research methods are missing. Try to add it

3.      The methodology: (2.1 Profile): give a brief example of X-ray diffraction.

4.      Section 3 (3.1 Cu contamination): the Author claims to reduce the leakage current. How is it possible? What is the residue resistance of the contamination

5.      Section 3.2 Thermal Management: The first paragraph gives a justification about what ambient temperature

6.      In figure 9 (a); If Author expressed Cu and Si component molten temperature (about annealing process)

7.      During the annealing process, what is the ACM temperature line?

8.      What is the effect of Notch in Figure 9(b) and (c)

9.      Section 3.3: What is the quenching process and coolant agent

10.  Figure 11: has to give a technical justification

11.  If Author, compared with recent relevant Author and would be appreciated

12.  In the summary and outlook Section: The new etching technique and design tool and approaches must be put in appropriate places.

13.  References: Please put the number properly/

14.  Some of places, the year, vol and issue number are misleading. Please arrange it properly

 

 

Comments for author File: Comments.pdf

Author Response

Thank you for your thorough guidance! I would like to express my sincere gratitude for your comments!

1. Based on your comments, the abstract was rewritten.
2. Based on your comments, the introduction section has been expanded.
3. Non-destructive FI （fault isolation） techniques are key to revealing multiple faults in complex 3D packages and can reduce production time (TPT) and improve success rates. For open circuit and high resistance faults, Time Domain Reflectometry (TDR) and Electro-Optical Terahertz Pulse Reflectometry (EOTPR) have proven effective in SIP packages with POP configurations.1TDR is a low cost, traditional non-destructive FI technique for isolating electrical faults in flip chip packages. Step electrical pulses with a rise time of 35-40 ps are injected into the package interconnect and the impedance changes along the circuit can be analysed by interpreting the reflected signals collected from the package. The location of the fault can be isolated in the chip or package sub-strate by comparing the reflected waves from the faulty cell with those from a good reference cell and bare substrate.3 The resolution of the TDR depends on the rise time, the bandwidth of the TDR system and the material properties within the package. TDR time domain resolution can be estimated as 1/10th to 1/5th of the TDR rise time.
4. Nowadays CMOS damascene copper interconnects EM wear-out mechanism is characterized by the nucleation of a void and its growth. Maximal current flow divergence occurs close to the via at the cathode of the line and leads to a void nucleation at the copper-dielectric interface (Cu/SiN or Cu/SiCN), which is the weakest interface largely due to its poor adhesion and consequent high diffusion rate. Therefore, an unsuitable barrier can lead to leakage currents.
5. Generating higher heat in a concentrated area fundamentally leads to greater temperature rise, which can result in reduced performance and, in extreme cases, physical damage to the circuit. As one end of a 3D IC chip stack is typically used for electrical interconnects, only one end can be used for heat dissipation. The paths available for heat dissipation may be limited, particularly from the middle of the stack.

6-8. Fig.9 have been redrawn, the description is now much clearer. The effect of temperature on protrusion is more significant than that of annealing time. The effect of annealing temperature on the residual stresses in the TSV structure is also significant. Higher annealing temperatures cause higher stresses and deformations at higher temperatures and at room temperature. When the annealing temperature exceeds 350°C, the protrusion height rises sharply. As the annealing temperature increases, the Cu can only expand continuously and vertically due to the constraint of the surrounding Si substrate. Due to the large CTE mismatch between Si and Cu, increasing stresses are generated in Cu as the TSV undergoes heat treatment. At a certain high temperature, when the thermal stress in the Cu TSV is greater than the yield stress of Cu, irreversible and permanent plastic deformation will occur. As a result, the Cu will extrude out of the TSV structure and when the wafer cools to room temperature, the elastic deformation will return, but the irreversible and permeable deformation that occurs in the Cu will never return to its original shape or length, and then a Cu protrusion will form. Disrupting the electrical connection of the device and causing the substrate protrusion to fail.

9. It is very difficult to quench TSVs during manufacturing service, it is annealed and relies on air cooling.
10. Conclusion part is added
11. Checked and corrected the format of the references again

Reviewer 3 Report

 

In this review article, comprehensively discusses measurement methods for through‐silicon via (TSV), different parameters to be focused while fabricating a TSV and reliability problems along with their solutions. Authors are requested to address following comments:

 

Authors have provided detailed explanations of device parameters, however, they have not significantly discussed the effects of electrical parameters during different fabrication steps.

 

Section 2.2, Discusses several approaches for void characteristics measurement but correlation between them is missing.

 

 Section 3.1, Line 361, Authors are requested to briefly explain the types of atomic migration.

 

 Figure 4, In the figures of filling mechanism of TSV, deposition of Copper metal is shown. Authors have not considered the barrier layer but have shown an underlined layer of the same Copper metal. Kindly improve the figure, using distinguished colors for different layers.

 

  Section 3.2, Line 429, “The introduction of TSVs …. impact signal integrity and power consumption.” I recommend that Authors should provide a detailed explanation for the decrease in performance of ICs by introducing TSVs based on parameters, like signal integrity, resistance, and other relevant parameters.

 

 Section 3, Line 310, “In order to ensure the reliability of the liner…..injected into the pad during the test.” Authors should kindly elaborate this statement, that how this phenomenon for increasing the reliability of liner works.

 

Acronyms are not correctly defined. Also, the same acronym has been given for multiple definitions.

 

a.      Section 3.3, Line 509, Kindly correct the full form of MEMS.

 

b.     Section 3.3, Line 505 and 516, “packaging and fabrication processes” and “package flatness planarity” both have been assigned acronym PFP.

 

Authors should kindly rectify the grammatical errors, some of them are mentioned below:

 

a.      Section 3.2, Line429, “The introduction of TSVs can lead to increased parasitic capacitance…. power consumption.”

 

b.     Section 3.2, Line 420, “However, designing reliable copper TSVs remains a significant challenge.”

 

The authors must consider the driver characteristics also while analysing the crosstalk. Must take inputs from following papers:

 

An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method. Microelectronics Journal 45 (4), 441-448

 

Crosstalk analysis of simultaneously switching interconnects. International Journal of Electronics 96 (10), 1095-1114

 

 How would the analysis be different from FDTD models considering the stability issues. A comparison can be mentioned with respect to previous results of paper:

 

 

An unconditionally stable FDTD model for crosstalk analysis of VLSI interconnects

 

IEEE Transactions on Components, Packaging and Manufacturing Technology 5

 

Does the line resistance and driver size play an important role while driving the TSVs. Can discuss vis-à-vis interconnect based results in

 

 

Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects

 

Microelectronics International

 

There are several issues with the fabrication of CNTs and its variants in form of MWCNTs. The authors must address these issues as well with respect to following analysis presented:

 

 

Carbon nanotube based 3-D interconnects-A reality or a distant dream

 

IEEE Circuits and Systems Magazine 14 (4), 16-35

 

 

 

Fabrication of liners with MWCNTs can be quite challenging leading to inaccuracies in the model. How would authors handle such inaccuracies.

 

Fabrication and application of carbon nanotubes/cellulose composite paper

 

Vacuum, Volume 122, Part A, December 2015, Pages 135-142

 

In overall sense, the work is quite impressive and acceptable provided above issues are handled/mentioned in the paper.

Proofread the article properly....

Author Response

Thank you for your thorough guidance! I would like to express my sincere gratitude for your comments：

1. The manuscript complements the influence of the electrical parameters in the different manufacturing steps.
2. The structure of Section 2.2 was reorganized and we refined the discussion of void characteristics measurements.
3. Fig,4 has been redrawn
4. Atomic migration consists of electro-migration (EM), stress-migration (SM), and ther-mal-migration (TM)
5. Additional description of the impact of TSV in IC design.
6. The problem of abbreviations was corrected according to your suggestion
7. The grammar problem was corrected
8. All the Articles you mentioned has been correctly cited.

Reviewer 4 Report

Well written article. 

Author Response

Thank you for your thorough guidance!

Reviewer 5 Report

1.     In lines 282-284, the “Eq.1.” could be arranged as Eqs. (1), (2) and (3.)

2.     The font type of symbols could be unified as the same ones in Eqs. (1)-(3).

3.     The format in the references should be unified according to the Author Guidelines.

 

4.     Some errors were highlighted in fluorescent as attached manuscript. The authors could double-check the correctness before re-submission. 

Comments for author File: Comments.pdf

Some errors in English presentation were highlighted in fluorescent as attached manuscript. The authors could double-check the correctness before re-submission. 

Author Response

TO Reviewer 5:

Thank you for your thorough guidance! I would like to express my sincere gratitude for your comments：

1. Corrections were made in accordance with your comments
2. Corrections were made in accordance with your comments, The symbol format was standardized.
3. Correction to the reference format.
4. The problems you pointed out have been corrected.

Round 2

Reviewer 2 Report

Dear author, 

As per previous reviews, if you are compared with any an existing circuit/results and would have been appreciated. but you are fail to do that one. 

But you are managed to cover all my review points

 

Author Response

Thanks for your hard work again.I'm so sorry we didn't understand your meaning correctly. We have now supplemented the contents you mentioned in three tables： 

Table 1， Percentage Difference in Crosstalk Delay of Defected TSV Compared to Defect Free Case.

Table 2,   Typical parameters for different TSV fabrication technologies.

Table 3,   TSV parameters under different new processes.