A Multilevel Switched Capacitor Inverter with Reduced Components and Self-Balance

Abstract

This paper presents a novel 13-level switched capacitor multilevel inverter, which uses less devices to achieve six-fold voltage gain. The proposed topology structure consists of twelve transistors, two diodes, and three capacitors. It is worth mentioning that characteristics as having five complementary switch pairs and self-balanced electric capacity voltages are conducive to simplifying the control strategy. Moreover, the above components constitute the switched capacitor unit and L-type unit. The inverter can acquire more voltage levels and a higher voltage gain by using multiple L-type units with fewer elements. Furthermore, the cost function is employed to comprehensively appraise the performance of the proposed inverter. The comparison with other existing 13-level inverters shows that the proposed multilevel inverter can effectively decrease the value of the cost function. Finally, the simulation and experimental results are presented to demonstrate the feasibility and effectiveness of the 13-level inverter.

1. Introduction

Multilevel inverters (MLIs) have emerged as an important tool for medium-voltage high-power applications like renewable energy system, electric vehicles (EVs), and flexible AC transmission systems [1,2,3]. MLIs possess many excellent features in contrast with the two-level inverter, such as a better performance in terms of total harmonic distortion (THD), reduced dv/dt stresses, a lower switching frequency, etc. [4]. Generally, conventional MLIs are divided into neutral-point clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) inverters [5]. However, NPC and FC inverters use numerous components with increasing voltage levels, and it is complicated to keep control of the balance of the capacitor voltage [6]. In addition, CHB inverters have drawbacks like a strong demand for isolated DC sources and a lack of boost capacity [7]. It is noteworthy that the MLIs based on the switched capacitor (SC) technique are capable of self-balancing the capacitor voltage as well as raising the input voltage [8,9].

With these unique advantages, switched capacitor multilevel inverters (SCMLIs) have been widely studied and have produced various topologies. For instance, the inverters in [10,11,12,13,14] use several DC sources combined with switched capacitors to produce a multilevel output. The SCMLIs proposed in [10,11] can achieve a double voltage gain with self-charging capacitors. To obtain a greater number of voltage levels, the 17-level switched capacitor inverter in [12] was developed using two SC cells. In [13,14], the inverters achieved a higher boosting factor with a number of SC units. Nevertheless, the above topologies have a common defect, namely that of employing multiple DC sources, which results in the growth of application cost.

In order to solve the aforesaid issue, several single-source SCMLIs were proposed in [15,16,17,18]. The inverter in [15] achieved seven-level output with a single source, and more levels were obtained in [16,17,18] using extended structures. However, these topologies all use the H-bridge to transform the direction of the output voltage, which can raise the total standing voltage (TSV) of switches. The H-bridge was removed in [19,20,21,22] due to the intrinsic inversion ability. The multilevel inverter based on the K-type unit in [19] has a voltage gain of 1.5, while a triple boosting factor was obtained in [20,21,22]. The three MLIs include a T-type which maintains the capacitor voltage at half of the input voltage to produce more output levels. Nevertheless, the above topologies could be improved if they did not require abundant devices for a higher boosting factor, an issue identical to that found in [23].

The works [24,25,26,27] developed 13-level switched capacitor inverters which achieve a voltage gain of six with fewer components. Through the regular charging–discharging of the capacitor, the inverter proposed in [24] can realize the self-balancing of capacitor voltages, but the voltage stress of the switches is high. The stress on the devices of the inverter in [25] decreased, which was restricted to half the maximum output voltage. The multilevel inverter proposed in [26] used fifteen transistors and three capacitors, and the output voltage polarity was changed with two half-bridge modules. Two switched capacitor inverters proposed in [27] only used twelve switches. The topologies contain a triple-mode SC unit and a simplified SC unit. The inverter proposed in [28] also uses a triple-mode SC, but employs four capacitors, which leads to an increase in volume. In addition, the abovementioned structures cannot be expanded and the application scenarios are restricted.

Based on the previous analysis, a new 13-level SCMLI is proposed in this paper, and it has the following excellent features:

(1)

The proposed multilevel inverter can acquire six-fold voltage gain with a reduced number of components;

(2)

Only twelve transistors are employed and there are five complementary switch pairs, which simplifies the control strategy;

(3)

The capacitor voltage is self-balancing without the need for extra loops;

(4)

The proposed SCMLI is capable of extending to acquire more voltage levels and a higher boost factor;

(5)

A low-value cost function (CF) can be obtained in the topology.

The remaining sections are organized as follows: Section 2 gives the structure of the proposed 13-level switched capacitor boost inverter, and its working states at different levels are also introduced. Section 3 analyzes the power losses and gives the parameter calculation of the multilevel inverter. Section 4 introduces the topology extension and comprehensive results of comparisons with other MLIs. Section 5 presents the simulation and experimental platform to verify the validity of the 13-level inverter. In the end, conclusions are given in Section 6.

2. Design of Proposed SCMLI

2.1. Topology

The proposed 13-level switched capacitor topology is depicted in Figure 1. It is made up of four switches (S₁–S₄), a switched capacitor unit (SCU), a L-type unit (LTU), two diodes, and three capacitors. The SCU contains a single DC source, five switches (S₅–S₉), a diode D₁, as well as capacitors C₁ and C₂. Figure 2 shows the working states of the proposed switched capacitor basic unit. In Figure 2a, the capacitor voltage can be maintained at V_dc when it is connected in parallel with the DC source. Figure 2b,c displays the discharge of capacitors connected in parallel/series. The SCU can achieve a triple voltage gain when the two capacitors are connected in parallel with the DC source. LTU includes the capacitor C₃, three switches (S₁₀–S₁₂), and a diode D₂, whilst the capacitor voltage of C₃ can be maintained at 3 V_dc through the L-type circuit loop.

2.2. Operating Mode

The proposed topology possesses a 13-level output and fourteen operating modes. The different switching modes and output levels are shown in

Table 1. Operating modes of the proposed MLI.

Modes	Output Voltage	Switches						Capacitors
		S1,2	S3,4	S5,6	S7/8,9	S10,11	S12	C1	C2	C3
1	+6 Vdc	01	10	10	01	01	0	D	D	D
2	+5 Vdc	01	10	10	10	01	0	D	D	D
3	+4 Vdc	01	10	01	10	01	0	C	C	D
4	+3 Vdc	01	10	10	01	10	1	D	D	C
5	+2 Vdc	01	10	10	10	10	0	D	D	–
6	+Vdc	01	10	01	10	10	0	C	C	–
7	0	01	01	10	01	10	1	D	D	C
8		10	10	10	01	10	1	D	D	C
9	−Vdc	10	01	01	10	10	0	C	C	–
10	−2 Vdc	10	01	10	10	10	0	D	D	–
11	−3 Vdc	10	01	10	01	10	1	D	D	C
12	−4 Vdc	10	01	01	10	01	0	C	C	D
13	−5 Vdc	10	01	10	10	01	0	D	D	D
14	−6 Vdc	10	01	10	01	01	0	D	D	D

, where “0” and “1” indicate the “off” and “on” statuses of the switches, respectively. The working conditions of capacitors are presented by “C”, “D”, and “–”, which denote the charging, discharging, and idle states. A total of five complementary switch pairs are employed to prevent the capacitors from being short-circuited. Moreover, capacitors C₁ and C₂ have the same state and a high charging frequency, which is beneficial to diminish the capacitor voltage ripple and improve the waveform quality of the output voltage.

Figure 3 shows the positive conducting paths in each operating state. Note that the lines highlighted in green represent the charging circuit of the capacitors, and that the lines highlighted in red represent the paths of the synthetic voltage level. In addition, the proposed 13-level topology can integrate the inductive load, because there is a reverse current path composed of capacitors and anti-parallel diodes. For the simplicity of analysis, the assumption is that all devices are ideal and that the voltages of capacitors C₁ and C₂ are constant at V_dc, while the voltage of capacitor C₃ is constant at 3 V_dc. The positive polarity voltage is generated when switches S₂ and S₃ are turned on, and the negative polarity voltage is generated when the switches S₁ and S₄ are turned on.

2.3. Modulation Strategy

A number of modulation strategies have been put forward to control multilevel inverters, such as sinusoidal pulse width modulation (SPWM) [29], nearest level control (NLC) [30], and selective harmonic elimination (SHE) [31]. To reduce the operational complexity and the value of THD, the phase disposition pulse width modulation (PD-PWM) is used to generate the drive signal of the switches, as shown in Figure 4.

For the proposed 13-level inverter, there are twelve triangular carriers (u₁~u₁₂) with the same amplitude A_c and frequency f_c, which are compared with the sinusoidal reference wave with amplitude A_ref and frequency 50 Hz (f_o). The processes of the capacitor charge and discharge in one cycle are also presented. The voltage of capacitors C₁ and C₂ can be kept at V_dc with the same voltage ripple ∆V_c1,2, and the voltage of capacitor C₃ can be kept at 3 V_dc with the voltage ripple ∆V_c3. The modulation logic of the 13-level inverter is presented in Figure 5. There are five complementary switch pairs and a 13-level output is obtained through logical combinations.

For the modulation strategy adopted in the proposed topology, the number of output levels is related to the modulation index, and the modulation index M can be expressed as

$$M=\frac{A\mathrm{ref}}{6A\mathrm{c}}.$$

(1)

Table 2. The relationship between M and the output level.

M	Number of Levels	Output Voltage Levels
0 < M ≤ 1/6	3	±Vdc, 0
1/6 < M ≤ 1/3	5	±2 Vdc, ±Vdc, 0
1/3 < M ≤ 1/2	7	±3 Vdc, ±2 Vdc, ±Vdc, 0
1/2 < M ≤ 2/3	9	±4 Vdc, ±3 Vdc, ±2 Vdc, ±Vdc, 0
2/3 < M ≤ 5/6	11	±5 Vdc, ±4 Vdc, ±3 Vdc, ±2 Vdc, ±Vdc, 0
5/6 < M ≤ 1	13	±6 Vdc, ±5 Vdc, ±4 Vdc, ±3 Vdc, ±2 Vdc, ±Vdc, 0

shows the output voltage levels and the corresponding range of M, which varies between 0 and 1.

2.4. Capacitor Analysis

The capacitor voltage of the proposed SCMLI can be balanced without the extra loops, which is crucial to generate the ideal voltage. The capacitors C₁, C₂, and C₃ can be charged through a parallel charging mechanism in each cycle, as shown in Table 1 and Figure 3.

To diminish the voltage ripple and improve the quality of the voltage waveform, the maximum voltage ripple of the capacitor is set to remain below 10% of the rated capacitor voltage. The voltage ripple is related to the continuous discharging amount of capacitor. It can be seen in Figure 4 that the points of u_ref intersect and that the carriers are set to t_i (i = 1, 2, 3…, 12), which can be calculated by

$$t_i=\frac{\arcsin \left(\frac{i}{6M}\right)}{2\mathsf{\pi }{f}_{\mathrm{o}}},$$

(2)

where f_o is the output frequency and M is set to 0.9. As is shown in Figure 4, the maximum discharging interval of the capacitors C₁ and C₂ is [t₄–t₇], whilst the maximum discharging interval of capacitor C₃ is [t₃–t₈]. The instants t₃, t₄, t₇, and t₈ can be calculated by

$$t_3=\frac{\arcsin \left(\frac{1}{2M}\right)}{2\mathsf{\pi }{f}_{\mathrm{o}}},$$

(3)

$$t_4=\frac{\arcsin \left(\frac{2}{3M}\right)}{2\mathsf{\pi }{f}_{\mathrm{o}}},$$

(4)

$$t_7=\frac{\mathsf{\pi }-\arcsin \left(\frac{2}{3M}\right)}{2\mathsf{\pi }{f}_{\mathrm{o}}},$$

(5)

$$t_8=\frac{\mathsf{\pi }-\arcsin \left(\frac{1}{2M}\right)}{2\mathsf{\pi }{f}_{\mathrm{o}}},$$

(6)

The capacitors C₁ and C₂ have the same discharge cycle and rated capacitor voltage. For the simplicity of analysis, only capacitor C₁ is calculated. According to Equations (3)–(6), the maximum discharge amount of C₁ and C₃ can be obtained as

$$\Delta Q_1={\displaystyle {\int }_{t_4}^{t_7}{I}_{\mathrm{o}}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)dt,$$

(7)

$$\Delta Q_3={\displaystyle {\int }_{t_3}^{t_8}{I}_{\mathrm{o}}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)dt,$$

(8)

where ∆Q₁ and ∆Q₃ are the maximum discharge amounts of C₁ and C₃, respectively, whilst I_o is the output current. Supposing that the coefficient defining maximum admissible voltage ripple is 0.1, then the capacitance can be calculated by

$$C_1=C_2\ge \frac{\Delta Q_1}{0.1V_{C1}},$$

(9)

$$C_3\ge \frac{\Delta Q_3}{0.1V_{C3}},$$

(10)

where V_C1 and V_C3 are the rated voltages of C₁ and C₃, respectively. The voltage ripple of the capacitors can be kept within an acceptable bound through a suitable capacitance.

3. Power Losses Analysis

For the proposed 13-level topology, three kinds of power loss are calculated, namely the switching losses (P_sw), conduction losses (P_con), and ripple losses of capacitors (P_rip).

3.1. Switching Losses

The switching losses are produced by the overlapping of the voltage and current during the switch on/off process, which includes the switch-on loss (P_sw,on) and switch-off loss (P_sw,off). For simplicity, the switching losses are calculated according to the linear approximation of the voltage and current. According to the calculation method in [16], the P_sw,on and P_sw,off of the i-th switch are expressed as

$$\begin{array}{l}{P}_{\mathrm{sw},\mathrm{o}\mathrm{n},i}=f_{\mathrm{sw}}{\displaystyle {\int }_0^{t_{\mathrm{on}}}{v}_{\mathrm{s}\mathrm{w},i}\left(t\right)i\left(t\right)}dt\\ \hspace{1em}\hspace{1em}\hspace{1em}=f_{\mathrm{sw}}{\displaystyle {\int }_0^{t_{\mathrm{on}}}\left(-\frac{V_{\mathrm{s}\mathrm{w},i}}{t_{\mathrm{on}}}\left(t-t_{\mathrm{on}}\right)\right)\left(\frac{I_{\mathrm{on},i}}{t_{\mathrm{on}}}t\right)}dt,\\ \hspace{1em}\hspace{1em}\hspace{1em}=\frac{f_{\mathrm{sw}}{V}_{\mathrm{s}\mathrm{w},i}{I}_{\mathrm{on},i}{t}_{\mathrm{on}}}{6}\end{array}$$

(11)

$$\begin{array}{l}{P}_{\mathrm{sw},\mathrm{off},i}=f_{\mathrm{sw}}{\displaystyle {\int }_0^{t_{\mathrm{off}}}{v}_{\mathrm{s}\mathrm{w},i}\left(t\right)i\left(t\right)}dt\\ \hspace{1em}\hspace{1em}\hspace{1em}=f_{\mathrm{sw}}{\displaystyle {\int }_0^{t_{\mathrm{off}}}\left(\frac{V_{\mathrm{s}\mathrm{w},i}}{t_{\mathrm{off}}}t\right)\left(-\frac{I_{\mathrm{off},i}}{t_{\mathrm{off}}}\left(t-t_{\mathrm{off}}\right)\right)}dt\\ \hspace{1em}\hspace{1em}\hspace{1em}=\frac{f_{\mathrm{sw}}{V}_{\mathrm{s}\mathrm{w},i}{I}_{\mathrm{off},i}{t}_{\mathrm{off}}}{6},\end{array}$$

(12)

where f_sw is the switching frequency of the inverter, V_sw,i represents the stress of the i-th switch, t_on and t_off are the turn-on time and turn-off time of the switch, respectively, and I_on,i and I_off,i represent the current through the i-th switch after turning on and before shutting off, respectively. Thus, the P_sw of the all switches is expressed as

$$P_{\mathrm{sw}}={\displaystyle \sum _{i=1}^{12}\left(P_{\mathrm{sw},\mathrm{on},i}+P_{\mathrm{sw},\mathrm{off},i}\right)}.$$

(13)

3.2. Conduction Losses

The conduction losses can be produced by the impedance of semiconductor devices and capacitors, which include the conduction resistance R_s of switches, the internal resistance R_d of diodes, and the equivalent series resistance ESR_C of capacitors. Figure 6 provides the predigested circuits for all operating states.

Table 3. Parameters of the equivalent circuits.

j	Vo, j	Req, j
0	0	Rs + Rd
1	±Vdc	2 Rs + 2 Rd
2	±2 Vdc	3 Rs + 3 Rd/2 + ESRC/2
3	±3 Vdc	4 Rs + Rd + 2 ESRC
4	±4 Vdc	3 Rs + Rd + ESRC
5	±5 Vdc	4 Rs + Rd/2 + 3 ESRC/2
6	±6 Vdc	5 Rs + 3 ESRC

shows the equivalent parameters of each operating state. Herein, V_{o, j} and R_eq,j are the output voltage and equivalent parameters, respectively. For the interval of [0, t₁], the energy loss can be expressed as

$$E_{0~V_{\mathrm{dc}}}={\displaystyle {\int }_0^{t_1}{[I_{\mathrm{o}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)]}^2}\times [R_{\mathrm{eq},1}\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)}{A_{\mathrm{c}}}+R_{\mathrm{eq},0}(1-\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)}{A_{\mathrm{c}}})]dt.$$

(14)

For other intervals, the energy losses can be calculated in the same way.

$$E_{V_{\mathrm{dc}}~2V_{\mathrm{dc}}}={\displaystyle {\int }_{t_1}^{t_2}{[I_{\mathrm{o}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)]}^2}\times [R_{\mathrm{eq},2}\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-A_{\mathrm{c}}}{A_{\mathrm{c}}}+R_{\mathrm{eq},1}(1-\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-A_{\mathrm{c}}}{A_{\mathrm{c}}})]dt,$$

(15)

$$E_{2V_{\mathrm{dc}}~3V_{\mathrm{dc}}}={\displaystyle {\int }_{t_2}^{t_3}{[I_{\mathrm{o}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)]}^2}\times [R_{\mathrm{eq},3}\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-2A_{\mathrm{c}}}{A_{\mathrm{c}}}+R_{\mathrm{eq},2}(1-\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-2A_{\mathrm{c}}}{A_{\mathrm{c}}})]dt,$$

(16)

$$E_{3V_{\mathrm{dc}}~4V_{\mathrm{dc}}}={\displaystyle {\int }_{t_3}^{t_4}{[I_{\mathrm{o}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)]}^2}\times [R_{\mathrm{eq},4}\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-3A_{\mathrm{c}}}{A_{\mathrm{c}}}+R_{\mathrm{eq},3}(1-\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-3A_{\mathrm{c}}}{A_{\mathrm{c}}})]dt,$$

(17)

$$E_{4V_{\mathrm{dc}}~5V_{\mathrm{dc}}}={\displaystyle {\int }_{t_4}^{t_5}{[I_{\mathrm{o}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)]}^2}\times [R_{\mathrm{eq},5}\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-4A_{\mathrm{c}}}{A_{\mathrm{c}}}+R_{\mathrm{eq},4}(1-\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-4A_{\mathrm{c}}}{A_{\mathrm{c}}})]dt,$$

(18)

$$E_{5V_{\mathrm{dc}}~6V_{\mathrm{dc}}}={\displaystyle {\int }_{t_5}^{t_6}{[I_{\mathrm{o}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)]}^2}\times [R_{\mathrm{eq},6}\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-5A_{\mathrm{c}}}{A_{\mathrm{c}}}+R_{\mathrm{eq},5}(1-\frac{A_{\mathrm{ref}}\sin (2\mathsf{\pi }{f}_{\mathrm{o}}t)-5A_{\mathrm{c}}}{A_{\mathrm{c}}})]dt.$$

(19)

Based of the above, the P_con of the proposed 13-level topology can be obtained by

$$P_{\mathrm{con}}=(4E_{0~V_{\mathrm{dc}}}+4E_{V_{\mathrm{dc}}~2V_{\mathrm{dc}}}+4E_{2V_{\mathrm{dc}}~3V_{\mathrm{dc}}}+4E_{3V_{\mathrm{dc}}~4V_{\mathrm{dc}}}+4E_{4V_{\mathrm{dc}}~5V_{\mathrm{dc}}}+2E_{5V_{\mathrm{dc}}~6V_{\mathrm{dc}}})\times f_{\mathrm{ref}}.$$

(20)

3.3. Ripple Losses

The ripple losses can be produced by the voltage fluctuation of the capacitor, and the voltage ripple of capacitors C₁, C₂, and C₃ can be obtained as

$$\Delta V_{C1}=\Delta V_{C2}=\frac{\Delta Q_1}{C_1},$$

(21)

$$\Delta V_{C3}=\frac{\Delta Q_3}{C_3},$$

(22)

where the ∆V_C1, ∆V_C2, and ∆V_C3 are the voltage ripples of capacitors C₁, C₂, and C₃, respectively. According to the calculation method in [28], the ripple losses of the capacitors are expressed as

$$P_{\mathrm{rip}}=\frac{f_{\mathrm{o}}}{2}{\displaystyle \sum _{k=1}^3{C}_k\Delta V_{Ck}^2.}$$

(23)

Overall, the power losses of the proposed 13-level topology are expressed as

$$P_{\mathrm{loss}}=P_{\mathrm{sw}}+P_{\mathrm{con}}+P_{\mathrm{rip}}.$$

(24)

Finally, the theoretical efficiency is indicated by $\eta$, which is defined by

$$\eta =\frac{P_{\mathrm{o}}}{P_{\mathrm{sw}}+P_{\mathrm{con}}+P_{\mathrm{rip}}+P_{\mathrm{o}}},$$

(25)

where P_o is the output power of the inverter.

4. Topology Extension and Comparison

4.1. Topology Extension

One of the main benefits of the proposed 13-level topology is that it allows for modular extensions. As illustrated in Figure 7, each L-type unit (LTU) contains a capacitor, three power switches, and a diode. It can be learned from a previous analysis that capacitor C₃ is charged in series with the capacitors C₁ and C₂ through switches S₁₀ and S₁₂. Theoretically, n LTUs can be integrated into the proposed switched-capacitor multilevel inverter. For the n-th LTU, capacitor C_n+2 can be charged to (3 × 2ⁿ⁻¹) V_dc through series connection with the capacitors C₁~C_n+1, since the voltage levels and boost factor will be increased by connecting multiple L-type units.

The extended inverter consists of n number of LTU, the switch count N_switch, the diode count N_diode, the switched capacitor count N_capacitor, the voltage levels N_level, and the boost factor G can be expressed as:

$$N_{\mathrm{switch}}=3n+9,$$

(26)

$$N_{\mathrm{diode}}=n+1,$$

(27)

$$N_{\mathrm{capacitor}}=n+2,$$

(28)

$$N_{\mathrm{level}}=3\times 2^{n+1}+1,$$

(29)

$$G=3\times 2^n.$$

(30)

The THD of the proposed inverter can be further reduced with the increase in output levels, while the control of switches will be more complex, and the demand for carriers will also increase significantly, which is twice as much as voltage gain. Therefore, reasonable output levels and voltage gain can be chosen according to application requirements.

4.2. Comparison Analysis

To assess the pros and cons of the proposed SCMLI, a comprehensive contrast with other 13-level topologies is shown in

Table 4. Comparison with other 13-level SCMLIs.

Reference	Ndc	Nswitch	Ndriver	Ndiode	Ncapacitor	G	TSV	CF		Extensibility
								α = 0.5	α = 1.5
[10]	2	11	7	1	1	2	39	4.577	7.577	No
[11]	2	14	11	0	2	2	32	5.384	7.846	No
[16]	2	14	14	2	4	3	34	6.103	7.846	Yes
[18]	1	10	8	10	5	6	43	2.814	3.365	Yes
[19]	1	12	8	2	4	1.5	15	2.385	3.154	Yes
[20]	1	12	7	4	4	3	13	2.243	2.577	No
[21]	1	14	13	2	4	3	18	2.769	3.230	Yes
[22]	1	13	11	1	3	3	17	2.372	2.808	Yes
[23]	1	29	29	5	5	6	29	5.416	5.788	Yes
[24]	1	13	9	2	3	6	39	2.327	2.827	No
[25]	1	14	10	1	3	6	33	2.365	2.788	No
[26]	1	15	12	0	3	6	35	2.532	2.981	No
[27]	1	12	6	4	3	6	36	2.154	2.615	No
[29]	1	13	9	2	3	6	32	2.282	2.692	No
Proposed	1	12	6	2	3	6	38	2.013	2.500	Yes

. Items which are compared include the number of power elements, the number of DC sources, the number of drivers (N_driver), the voltage gain, the total standing voltage (TSV), and the extensibility of SCMLIs. The cost function in [16] is defined as follows

$$\mathrm{CF}=\left(N_{\mathrm{switch}}+N_{\mathrm{driver}}+N_{\mathrm{diode}}+N_{\mathrm{capacitor}}+\alpha \frac{\mathrm{TSV}}{G}\right)\times \frac{N_{\mathrm{dc}}}{13},$$

(31)

where α is the “weighing factor” reflecting the proportion of TSV in the cost function, which is considered to be 0.5 or 1.5. Therefore, the multilevel inverters with a lower cost function have a better performance.

It can be concluded from Table 4 that the multilevel inverter in [10] can achieve 13-level output with less components, but the voltage gain is only of 2, which is the same as the inverter in [11]. The topology in [16] requires more components in the extended structure. In addition, the above three topologies use two DC sources, which also leads to a high CF value. The inverter in [18] uses a single source to achieve the high-voltage gain. However, the H-bridge will increase the voltage stress of the switches.

Compared with the above topologies, TSV is significantly reduced in [19,20,21,22], but their voltage gain is no more than 3, and the application range is limited. Due to plenty of elements being used, the inverter in [23] has a higher CF. The 13-level inverters in [24,25,26,27] and [29] can achieve a six-fold voltage gain. The inverter in [24] has a lower CF value when α = 0.5, while the inverter in [25] has a lower CF value when α = 1.5, because they have a different TSV.

Although the proposed multilevel inverter has a higher TSV, it uses fewer power devices to achieve a six-fold voltage gain. Due to the fact that the proposed inverter has five switch pairs operating in complementary states, fewer drivers are needed to control the switches, and the lowest value of N_driver can be achieved. Compared with the inverters in [24,25,26,27,29], the proposed topology with good extensibility can easily increase the output levels and acquire a higher voltage gain, which is conducive to applying more scenarios. Moreover, it can be seen that the CF of the proposed 13-level switched-capacitor inverter is lowest regardless of whether α is 0.5 or 1.5, which also confirms that the proposed topology has a better overall performance.

5. Simulation and Experimental Analysis

5.1. Simulations

To validate the correctness of the proposed switched-capacitor multilevel inverter, the 13-level inverter model was built and simulated in the MATLAB/Simulink environment. The simulation parameters are listed in

Table 5. Simulation parameters.

Parameters	Values
Input voltage (Vdc)	25 V
Output frequency (fo)	50 Hz
Triangle carrier frequency	3 kHz
Capacitors C1/C2/C3	2200 μF
Modulation index (M)	0.9
Load	80 Ω/80 Ω + 15 mH

. In the simulation model, the input voltage V_dc is 25 V, the load is 80 Ω or 80 Ω + 15 mH, the output frequency is 50 Hz, and the value of M is 0.9.

Figure 8 shows the corresponding results of the proposed topology. The waves of the output voltage and current under resistive–inductive load is shown in Figure 8a. The proposed inverter outputs 13 levels and the peak voltage is close to 150 V, which also indicates a voltage gain of 6. The load current is sinusoidal, so the inverter can provide a channel for reverse current. Figure 8b presents the waves of the output voltage and current under pure resistive load. Figure 8c gives the waves of all capacitors voltage. It can be seen that the voltage of the capacitors fluctuates slightly within the allowable range during charging and discharging.

The THD of the inverter is approximately 10.37%, as shown in Figure 9, which indicates that the modulation method used can effectively reduce the harmonic content and improve the quality of the output voltage. In addition, due to the carrier frequency being 3 kHz, the 60th harmonic component is the highest compared to the others. Moreover, the low THD can be further reduced by smaller filters or optimized modulation strategies.

5.2. Experimental Result

To validate the effectiveness of the proposed topology, a 13-level switched capacitor inverter test prototype has been built, as shown in Figure 10.

Table 6. Experimental parameters.

Components	Specifications
Input voltage (Vdc)	25 V
Output frequency (fo)	50 Hz/25 Hz/100 Hz
Carrier frequency	3 kHz
Capacitors C1/C2/C3	2200 μF
Resistive-inductive load	80/160 Ω + 15 mH
Switches (S1~S12)	SPP20N60C3
Diode	MBR20200CTG
Optocouplers	TLP250
Current probe	Tektronix A622

gives the specific experiment parameters. The carrier frequency is set to 3 kHz and the output frequency is set to 50 Hz. The steady-state and dynamic performance of the proposed multilevel topology are experimentally analyzed.

The strain capacity of the SCMLI was tested under complicated working states by changing the experimental parameters, such as the change of the input voltage, load, modulation ratio, and frequency.

Figure 11a gives the steady-state wave of output voltage and current when the modulation ratio M = 0.9. The switched capacitor inverter can output 13-level voltage and achieve a six-fold voltage gain, which is in line with the theoretical analysis. In addition, the output current is close to the sine wave, indicating that the proposed topology has a reverse current loop to carry out the inductive load. Figure 11b shows the waves of the capacitors voltage, which slightly fluctuates within the allowable range.

Figure 12 shows the waves of the output voltage and current under input voltage changes between 25 V and 15 V. It is apparent that the voltage levels and boost factor of the inverter remain unchanged during the sudden change in input voltage, and the output voltage and load current can alter synchronously and stably with the input voltage.

Figure 13 presents waves of the capacitors’ voltage under the input voltage of the topology changes between 25 V and 15 V. It is apparent that the capacitor voltage is relatively rapid and reaches the steady state after a short transition.

Figure 14 gives the output voltage and current waveform under the mutation of the load (unloaded to 80 Ω + 15 mH and 80 Ω + 15 mH to 160 Ω + 15 mH). It is apparent that the output voltage remains stable during the sudden change in load, and that the current quickly changes from 0 to the working state before decreasing as the load increases.

Figure 15 presents the experimental waveforms of the proposed SCMLI under the mutation of the modulation index M. It is apparent that the voltage levels decrease from 13 to 9 when M alters from 0.9 to 0.6, and the voltage gain is reduced to 4, whilst voltage levels decrease from 9 to 7 when M is altered from 0.6 to 0.4, and the voltage gain is reduced to 3, which is consistent with the analysis in Table 2.

Figure 16 gives the waves of the output voltage and current when the output frequency changes between 25 Hz and 100 Hz. It is apparent that, when the output frequency of the topology changes, the amplitude of the output voltage and the load current remain unchanged, and the frequency change response is rapid, which verifies that the proposed topology can work normally in a complex environment.

6. Conclusions

This article introduces a new 13-level SCMLI, which can reduce the number of power elements and achieve voltage self-balance. Through the combination of a switched capacitor unit (SCU) and an L-type unit (LTU), the proposed inverter is capable of a six-fold voltage gain with a single DC source and twelve switches. At the same time, the modulation method and loss calculation are briefly described. In addition, the proposed topology also has the capability of modular expansion. By increasing the number of LTUs, the voltage levels and boost factor can be significantly increased. Moreover, the proposed inverter has been compared with existing 13-level switched-capacitor inverters in detail. The results show that the proposed inverter employs fewer power devices and has obvious advantages in reducing the CF value. Finally, the proposed multilevel topology is built through an experimental prototype. The static and dynamic analysis results validate the effectiveness of the proposed SCMLI, which can quickly adjust a complex working environment.