A Low-Power ECG Processor ASIC Based on an Artificial Neural Network for Arrhythmia Detection

Abstract

The early detection of arrhythmia can effectively reduce the risk of serious heart diseases and save time for treatment. Many healthcare devices have been widely used for electrocardiogram (ECG) monitoring. However, most of them can only complete simple two-classes detection and have unacceptable hardware overhead and energy consumption. For achieving accurate and low-power arrhythmia detection, a novel ECG processor application specific integrated circuit (ASIC) is proposed in this paper, which can perform the prediction of five types of cardiac arrhythmias and heart rate monitoring. To realize hardware-efficient R-peak detection, an ECG pre-processing engine based on a first derivative and moving average comparison method is proposed. Efficient arrhythmia detection is realized by the proposed low-power classification engine, which is based on a carefully designed lightweight artificial neural network (ANN) with good prediction accuracy. The hardware reuse strategy is used to implement the hardware logic of ANN, where computations are executed by only one processing unit (PU), which is controlled by a flexible finite state machine (FSM). Also, the weights of ANN are configurable to facilitate model updates. We validate the functionality of the design using real-world ECG data. The proposed ECG processor is implemented using 55 nm CMOS technology, occupying an area of 0.33 mm². This design consumes 12.88 μW at a 100 kHz clock frequency, achieving a classification accuracy of 96.69%. The comparison results with previous work indicate that our design has advantages in detection performance and power consumption, providing a good solution for low-power and low-cost ECG monitoring.

1. Introduction

Arrhythmia refers to an abnormal heart rhythm, which is a common heart disease that can lead to heart attacks, strokes, and even death [1]. Traditional methods for detecting arrhythmia include electrocardiogram (ECG) examinations and echocardiography. These methods have the following shortcomings: (1) Limitations of location: Due to the requirement of specialized equipment available only in hospitals, patients cannot perform rapid ECG monitoring at home or elsewhere; (2) Limited monitoring time: Traditional methods of examination usually only provide a limited time window, and sudden arrhythmia may not be captured, which requires long-term monitoring to detect; (3) Reliance on professionals: The detection methods in hospitals rely on the assistance and analysis of doctors. This requires professional experience and additional time for manual analysis. These limitations prevent patients from detecting arrhythmia in a timely manner, thus missing the best time for treatment. Early portable ECG monitoring devices wirelessly transmitted the raw ECG data for analysis. However, wireless transmission consumes high power, which limits the battery life of these devices [2]. In recent years, with the development of semiconductor manufacturing technology, ECG processors for wearable or implantable devices have been widely used [3]. Some proposed ECG processors, cardiac sensors, and ECG classifiers are assisted by artificial intelligence (AI) algorithms to perform on-chip classification and detect heart diseases, effectively reducing the data transmission time and saving valuable treatment time.

The typical methods used for ECG classification in hardware include support vector machines (SVM), decision logic (DL), and neural networks (NN). A machine-learning-assisted cardiac sensor SoC is proposed in [4]; a switchable classification engine that can perform maximum likelihood classification (MLC) and SVM is applied to detect arrhythmia, achieving an accuracy of 95.8%. An SVM-based classifier is used as a strong classifier for arrhythmia detection in [5]. To improve energy efficiency, this design proposes a weak linear classifier, which first classifies heart beats based on simple features to reduce the activation rate of the SVM classifier. However, this SVM classifier can only achieve two-class classification, and the specific types of arrhythmia cannot be obtained. An adaptive derivative-based detection algorithm for potential arrhythmia recording is proposed to detect arrhythmia with the occasional abnormal heart beats [6], while it is also not applicable to the classification with multiple types. Neural network (NN)-based classifiers are widely adopted in ECG processors. In [7], the ECG recordings are digitalized by a level-crossing ADC, which is used to detect the position of R peaks, and the converted data are fed to a neural network for classification. However, this design requires up to 64 kB of memory capacity for storing parameters and weights. A Deep Neural Network (DNN)-based cardiac arrhythmia classifier is proposed in [8], which can detect five types of ECG rhythms with a classification accuracy of 91.6%. In [9], an arrhythmia classification processor using heartbeat difference encoding and an event-driven NN was presented, while the complex network architecture required a high hardware cost. An inference engine based on an extreme learning machine for robust ECG anomaly detection is presented in [10]; the intensive computation decreases the power efficiency, and the power of this design is 2940 μw. The authors in [11] proposed a biomedical AI processor with a reconfigurable NN engine that supports multifunctional bio-signal processing. An adaptive learning architecture is utilized to address inter-patient variations. However, the complex architecture leads to increased hardware costs and power consumption. A hardware architecture based on a Convolution Neural Network (CNN) for arrhythmia classification is proposed in [12], which increases the throughput at the cost of consuming more hardware overhead.

It can be observed that previous works have limitations including limited types of arrhythmia detection, a relatively low classification accuracy, a high hardware overhead, and unsatisfactory power performance. However, mobile health monitoring devices generally have strict cost and energy consumption requirements. To overcome existing problems, a low-power ECG processor ASIC is proposed in this paper, which can be used in wearable or portable healthcare devices with a limited battery life. This ASIC can classify heart beats into five types to detect arrhythmia. A low-computation-complexity method based on the first derivative and moving average comparison is adopted to detect R peaks in ECG signals. The classification is performed by a hardware-efficient computing engine, which is based on a simple ANN model with few parameters, achieving an acceptable accuracy and low detection power. All inference computations are based on 16-bit fixed point values and operated by reusing one processing unit (PU), which makes this ASIC have a low chip area overhead. This paper is organized as follows. Section 2 depicts the overall architecture of the proposed ECG processor. Section 3 describes the details of the system modules. Section 4 presents the hardware implementation and results. Finally, the conclusions are given in Section 5.

2. Overall Architecture

The architecture of the proposed ANN-based ECG processor ASIC is shown in Figure 1. The ASIC consists of a pre-processing engine, a data handler, a classification engine, and data interfaces. The digitized ECG data are inputted to the ASIC through a Serial Peripheral Interface (SPI), and the parameters for classification computing are also transmitted by SPI. Once the pre-processing engine detects an R peak, its index address in the ECG data buffer will be calculated and temporarily saved in a register that holds R-peaks indexes. The earliest index will be discarded when the latest index is saved. To ensure that 100 data points containing the complete R-peak can be obtained for subsequent classification, when the R-peak index register stores three indexes, 50 ECG data points before and after the index address of the penultimate R-peak will be transferred from the ECG data buffer to the input feature buffer of the classification engine, which is completed by the data handler. In addition, the R-R interval (RRI) is calculated simultaneously, which is an important parameter for obtaining the heart rate (HR). In this paper, RRI is represented by the number of sampling points between two peaks, so the heart rate can be calculated as follows:

HR = 60 × SR/RRI,

(1)

where SR is the sampling rate of ECG, generally not exceeding 1 kHz. The classification engine performs an inference of the input feature data, and a parameter buffer is included to store bias values and weights. The inference computation is completed by the PU under the control of a finite state machine (FSM). At the end of the classification, the RRI value and inference result are packaged into a frame and sent out by a Universal Asynchronous Receiver/Transmitter (UART).

3. System Modules

3.1. Pre-Processing Engine

The application scenario of this design is that the ECG is collected using single lead ECG sensors (Xunda Radio Equipment, Hangzhou, Zhejiang, China) at a sampling frequency of 360 Hz and quantified as signed values with a bit-width of 16. The raw digitized ECG signals are first filtered using a 69-tap Finite Impulse Response (FIR) filter in the pre-processing engine to remove noise, such as power-line interference, baseline drift, electromyographic (EMG) noise, and motion artifacts [13]. Considering the frequency range of the QRS complex, the bandwidth is set to 2–28 Hz. The schematic of the FIR filter is shown in Figure 2. A 16-bit × 128 SRAM (Static Random-Access Memory) (UMC, Hsinchu, Taiwan, China) is used to cache the ECG data within a filtering convolution window. When new data arrive, the earliest data within the window are discarded to accommodate the latest data. The symmetry of the FIR coefficients is utilized here, and only half of the coefficients need to be stored. A counter is used to generate read addresses for SRAM and registers to obtain data. Due to the low sampling frequency, only a few hundred filtering operations are required per second. Thus, the time division multiplexing strategy is adopted, using only one multiplier accumulator (MAC) unit to complete all multiplication and addition operations, which greatly reduces the hardware overhead compared to filter structures based on a delay chain. The entire convolutional filtering operation takes N clock cycles (N is the number of taps).

The filtered data are then fed to the R-peak detector; the detection process is shown in Figure 3. First, the first derivative of the filtered ECG data X(i) is calculated as (2), and then the average value within a moving window is obtained as (3), where the window size W is 30.

D(i) = X(i) − X(i − 1),

(2)

$$\mathrm{A}(\mathrm{i})=\frac{{\sum }_{\mathrm{i}-\mathrm{W}+1}^{\mathrm{i}}\mathrm{X}\left(\mathrm{i}\right)}{\mathrm{W}},(\mathrm{i} \ge \mathrm{W}),$$

(3)

If D(i) > THR_D and X(i) > A(i), then p_cnt is increased by 1. THR_D represents the threshold of the first derivative values, which is set to five in this paper. When the above judgment conditions are met twice, the current data point X(i) is considered as an R-peak point, the R-peak detection flag is set to high, and the R-peak value is equal to X(i). In order to eliminate the interference of false peaks near the R-peaks, a non-response period (nresp_period) of 0.2 s is applied here, which is equal to the time of 60 sampling points. The nresp_cnt signal is used for counting the non-response time. When it is equal to 0, it indicates the end of the non-response period, and then the next R-peak will continue to be detected. The performance of the proposed R-peak detection method is evaluated using all 48 records in the MIT-BIH arrhythmia database [14], the true positives (TP), false positives (FP), and false negatives (FN) of each record are obtained, and the sensitivity (Sen) and positive precision rate (P+) are calculated as follows:

Sen = TP/(TP + FN),

(4)

P+ = TP/(TP + FP),

(5)

The records with the worst Sen are 114 and 207, while the rest are greater than 97%, and the record with the worst P+ is 114, while the other records are greater than 90%. Figure 4 shows the evaluation results of part of the records. The total Sen and P+ of all records are 98.62% and 98.74%, respectively. We compared the performance of the proposed method with other R-peak detection methods used for hardware, as shown in

Table 1. Performance comparison with other R-peak detection methods.

Reference	[15]	[16]	[17]	[18]	This Design
Method	derivative and squaring	morpho- logical filter	wavelet transform	slope comparison	derivative and MA 2 comparison
Sen (%)	95.65	99.82	99.72	96.9	98.62
P+ (%)	99.36	99.71	99.49	99.1	98.74
Memory Used (kB 1)	N.A. 3	1	1	N.A.	0.25

¹ Kilo-Bytes. ² Moving Average. ³ Not Applicable.

. It is observed from the table that our proposed method realizes comparable Sen and P+ to those of recent works, achieving a good compromise between the hardware cost and performance.

A buffer is used in the pre-processing engine to temporarily store input ECG data, which includes a 16-bit × 1 k SRAM and a write address generator; the sampling data points of at least three heart beats can be stored in it. When ECG data are received from the SPI receiver, the write address will be incremented by 1. Once the write address reaches its maximum value, it will restart from 0, so the previous data will be overwritten. It should be noted that the write address can be considered as the index of the current input data in the buffer, which is further used to calculate the index of the R-peak point; this will be discussed later.

3.2. Data Handler

The data handler is used to transfer the data of segmented heart beats from the pre-processing engine to the classification engine, as shown in Figure 5a. The 50 data points before and after the R-peak are transmitted to the input feature buffer of the classification engine for a subsequent inference. Figure 5b illustrates the workflow of the data handler. The starting address (start_addr) for data handling is located 50 data points before the R-peak position. Once an R-peak is detected, the start_addr is calculated according to the index of the current input data, i.e., its corresponding write address (write_addr). Due to the delay caused by FIR filtering in the R-peak detection process, this delay needs to be subtracted in the calculation. After the starting address is determined, the data handling begins. The data_cnt signal is used to count the number of transmitted data points, which is also used as an offset to add to the starting address for generating read addresses (rd_addr); the addresses are input into the ECG Data Buffer along with the read request signal (rd_req). On the other hand, the data_cnt signal can be regarded as the write addresses, which are fed to the classification engine with the write request signal (wr_req). After the data_cnt reaches 100, the handle_finish signal is set to 1 to indicate the end of handling.

3.3. Classification Engine

The proposed ECG classification engine is based on a feed-forward neural network—specifically, a multi-layer perceptron (MLP). MLP is an ANN composed of multiple layers of neurons, where each neuron is connected to neurons in the next layer. This architecture is based on the following considerations: (1) Data processing: ANN is suitable for processing structured data. The ECG signal is time series data, where the features of each time point are used as the input; (2) Feature extraction: ANN can automatically learn features from the original ECG signal data without the need for additional feature extraction; (3) Nonlinear relationship: There are complex nonlinear relationships in the ECG signal, such as the amplitude and slope of QRS waves. ANN can capture these relationships by using nonlinear activation functions; (4) Multi-types classification: Arrhythmias contain multiple categories; classification can be achieved by adjusting the output layer neurons. Figure 6 shows the proposed ANN model, which includes one input layer, one hidden layer, and one output layer, with sizes of 100, 8, and 5, respectively. The calculation of hidden layer neurons is as follows:

$${\mathrm{H}}_{\mathrm{N}\mathrm{k}}={\sum }_{\mathrm{i}=1}^{{\mathrm{S}}_{\mathrm{i}}}{\mathrm{x}}_{\mathrm{i}}{\mathrm{w}}_{\mathrm{ik}}+{\mathrm{b}}_{\mathrm{k}},$$

(6)

$$\mathrm{f}({\mathrm{H}}_{\mathrm{Nk}})=\max (0, {\mathrm{H}}_{\mathrm{Nk}}),$$

(7)

where ${\mathrm{S}}_{\mathrm{i}}$ is the size of the input layer, and ${\mathrm{x}}_{\mathrm{i}}$, ${\mathrm{w}}_{\mathrm{ik}}$, and ${\mathrm{b}}_{\mathrm{k}}$ are the input, weight, and bias of one neuron, respectively. The results are activated by the rectified linear unit (ReLU) function, which is defined by (7). The output layer contains five neurons, representing a normal beat (NOR), left bundle branch block beat (LBBB), right bundle branch block beat (RBBB), premature ventricular contraction beat (PVC), and atrial premature beat (APB). The calculation of each neuron is the same as (6). To obtain the probability of each type, Softmax is used as the transfer function, which is defined as:

$${\mathrm{P}}_{\mathrm{j}}=\frac{{\mathrm{e}}^{{\mathrm{O}}_{\mathrm{Nj}}}}{{\sum }_{\mathrm{i}=1}^{{\mathrm{S}}_{\mathrm{o}}}{\mathrm{e}}^{{\mathrm{O}}_{\mathrm{Ni}}}},$$

(8)

where ${\mathrm{S}}_{\mathrm{o}}$ is the size of the output layer, and ${\mathrm{O}}_{\mathrm{Nj}}$ is the result of the j-th output layer neuron.

More than ten thousand segmented heart beats centered around the R-peak are obtained from the MIT-BIH database, which is achieved through a simple ECG segmentation algorithm containing R-peak detection. Each arrhythmia type contains 2500 heartbeat records with a length of 100 sampling points. These data are randomly disrupted and divided into a training set and testing set, each containing 6250 records. The dataset has been normalized by subtracting the mean to reduce the risk of numerical overflow and ensure the stability of the training. The error Backpropagation (BP) algorithm is used for training this model. For a training case $\overrightarrow{({\mathrm{x}}_{\mathrm{k}}}, \overrightarrow{{\mathrm{y}}_{\mathrm{k}}})$, the output of the neural network is ${\overrightarrow{{\mathrm{y}}_{\mathrm{k}}}}^{\prime }=({{\mathrm{y}}_1^{\mathrm{k}}}^{\prime },{{ \mathrm{y}}_2^{\mathrm{k}}}^{\prime }, \dots , {\mathrm{y}}_{{\mathrm{S}}_{\mathrm{o}}}^{\mathrm{k}\prime })$, and the mean square error of the network is:

$${\mathrm{E}}_{\mathrm{k}}=\frac{1}{2}{\sum }_{\mathrm{j}=1}^{{\mathrm{S}}_{\mathrm{o}}}{({{\mathrm{y}}_{\mathrm{j}}^{\mathrm{k}}}^{\prime }-{\mathrm{y}}_{\mathrm{j}}^{\mathrm{k}})}^2,$$

(9)

The BP algorithm updates weights in the negative gradient direction. Taking the example of the weights connecting the hidden layer to the output layer, denoted as ${\mathrm{w}}_{\mathrm{kj}}$, the update can be computed as follows:

$${\Delta \mathrm{w}}_{\mathrm{kj}}=-\mathsf{\alpha }\frac{{\partial \mathrm{E}}_{\mathrm{k}}}{{\partial \mathrm{w}}_{\mathrm{kj}}}$$

(10)

where α represents the learning rate, which is set to 0.001 in this paper. The training epochs are set to 30 because our experiments show that more epochs do not significantly improve the accuracy and loss performance.

In addition to the already determined input and output layers, the construction of an ANN model is based on considerations of classification accuracy and energy efficiency. On one hand, the size of the hidden layer is an important parameter of ANN, which has a critical impact on the classification accuracy. On the other hand, by reducing hidden layer neurons while ensuring acceptable accuracy, the computation complexity and memory overhead can be reduced, resulting in less computing time and low energy consumption. We used grid search to try different hidden layers; as shown in Figure 7a, the computing time is estimated by the number of processing clock cycles required by PU. A hidden layer with eight neurons is selected because the model achieves a good trade-off, with R² scores of 0.935 for training and 0.932 for testing. The loss curve for the proposed NN is shown in Figure 7b. The confusion matrix containing the prediction results is shown in Figure 8, and the overall classification accuracy is 96.69%. The sensitivity and positive predictive value (PPV) of each type are summarized, as shown in

Table 2. Sensitivity and positive predictive value (PPV) of each type.

Reference	NOR	LBBB	RBBB	PVC	APB	Overall
Sensitivity (%)	99.20	95.08	98.57	98.10	92.36	96.66
PPV (%)	97.41	96.38	95.76	98.88	94.93	96.67

.

The proposed classification ANN model is described in Verilog HDL for hardware implementation. Note that the hardware computing time of the ANN should be within a reasonable range, which determines the minimum clock frequency. According to the work process of this design, once an R-peak is detected, a classification of the heartbeat centered at the previous R-peak is performed subsequently. Considering that the maximum heart rate in extreme cases is 220 bpm, the minimum time interval between the two R-peaks is 272 ms. To obtain the results report of each heartbeat, it is necessary to leave a time margin for other processing and UART data transmission; thus, the time for each inference in this design should not exceed 100 ms.

Due to the fact that the storage and computation of fixed-point values require fewer hardware resources compared to floating-point values, the weights and biases obtained from training are converted into a 16-bit fixed-point format with a 1-bit sign, a 7-bit integer, and 8-bit decimals. PU is the basic computing unit in the classification engine; Figure 9 shows its schematic structure. It has two functions that can be switched through the Add_sel signal: (1) Multiply-Add: I × W + B = O; (2) Multiply-Accumulate: I × W + O(i − 1) = O(i). The first function is to add the product of the input feature values and weights with the bias values. And the second function is to accumulate the current product with the output value generated by the last operation, which is used to process the accumulation of the products. The partial sum register can be initialized to 0 through the Clear signal.

The feed-forward inference computation of ANN is completed by reusing the PU to serially process neurons, which is controlled by an FSM, as shown in Figure 10. When the transmission from the data handler to the input feature buffer is finished, the startup signal is set to high to activate the FSM. In the DATA_REQ state, the ecg_req and param_req signals are set to one to require input feature values and NN parameters. The computation of each neural network layer is divided into four steps. Taking the hidden layer as an example: (1) In the BIAS_UPDATE1 state, the bias register is updated to the corresponding bias value of the currently processed neuron; (2) The computing of input feature values and weights is completed in the HIDE_COMPU state. The input_cnt signal is responsible for counting the number of input values; when input_cnt is equal to the length of the input feature, indicating that all input values of one neuron have been calculated, then the state jumps to HIDE_STORE; (3) The ReLU operation is performed in the HIDE_STORE state, which is implemented by comparing the signed bit of the previous output values of the PU. If the sign bit is 1, which represents the negative value, 0 is stored as the result; otherwise, the input value will remain unchanged and will be stored directly, and an 8 × 16-bit register group is used to store the results of hidden layer neurons; (4) Finally, the processed neurons are counted in the HIDE_CHECK state. Once the hide_cnt is equal to the number of hidden layer neurons, the computation of the entire layer is completed. Otherwise, the next state will enter BIAS_UPDATE1 to start computing the next neuron. The operation of the output layer is similar to the above process, except that there is no ReLU operation in the OUT_STORE state, and the results are directly stored.

The generation of classification results is achieved by comparing the five results of the output layer one by one. First, assume that the value of the first output neuron is the maximum value, and set the initial value of the class index to 1. Then, compare it with the second output neuron value. If the latter is greater than the former, the class index is set to 2, and the maximum value is updated to the larger one. Otherwise, these values will remain unchanged and continue to be compared with the next output neuron until all output neurons are compared. Obviously, the value of the class index is the final classification inference result.

3.4. Data Transmitter

The data transmitter includes a data packaging module and a UART module. After an R-peak is detected and the classification of its previous heartbeat is completed, all results are collected and packaged into a data frame, which includes the RRI, prediction result, and R-peak value, as shown in Figure 11. To ensure correct transmission, each data frame also includes a header, sequence code, and checksum. The header is a fixed 16-bit width value. For each data frame sent, the sequence code is incremented by one. A simple addition verification method is adopted to generate the checksum. The data frame is transmitted by UART, which is used due to its low resource usage, and the communication rate fully meets the application requirements.

4. Hardware Implementation

To verify the hardware functionality, a behavior-level simulation of this design is conducted using real-world human ECG signals. The ECG signal is acquired from a palm single-lead [19] and digitized by AD7606 (ADI, Norwood, MA, USA), with a signed 16-bit binary format at 360 samples per second (S/s). In the testbench, the digitized raw ECG data are input to the ASIC using the SPI protocol at the same sampling rate. The partial simulation waveform is shown in Figure 12, where adc_data and ecg_data represent the raw data and filtered data, respectively. Each R-peak is successfully detected, and after detecting three R-peaks, the RRI and classification results for each heartbeat are obtained. The RRI in the figure are 0fb, 0f9, and 0ee (hexadecimal), respectively. According to (1), the corresponding HR can be calculated as 86, 87, and 91 bpm, respectively. The ECG signal used for the test is acquired from a healthy individual, and the waveform diagram shows a classification result of 1, indicating NOR, which means the prediction performed by the ASIC is correct. After each classification, the uart_en signal generates high-level pulses that enable the UART module to transmit the data frame containing the results.

The proposed ANN-based ECG processor ASIC is implemented using 55 nm Low-K CMOS technology (UMC, Hsinchu, Taiwan, China). The post placement and routing are completed using the Innovus Implementation System (Cadence, San Jose, CA, USA); Figure 13 shows the layout photograph. The core size is 0.308 mm × 0.308 mm, and the entire chip size is 0.578 mm × 0.578 mm. The power consumption after the layout is estimated using the Power Analysis tab, and the activity file is generated by a testbench that simulates inputting ECG data to the ASIC at a 360 Hz sampling rate. This design consumes 12.88 μW at a 100 kHz clock frequency and a power supply of 1.2 V, the details of the power analysis are shown in Figure 14. The energy efficiency (Energy Eff.) can be evaluated by the energy consumption of each classification, which is calculated as follows:

Energy Eff. = Power × Time/Classifi.

(11)

The time taken for each classification is 18.2 ms, which fully meets the requirements for the inference time. Therefore, the energy consumed for one inference is 234.4 nJ.

Table 3. Performance comparison with state-of-the-art ECG processors.

Reference	[4]	[7]	[8]	[10]	[11]	This Work
Process (nm)	90	180	180	40	65	55
Frequency (Hz)	40 M	10 k–25 M	12 k	70 M	5 M	100 k
VDD (V)	0.5–1.0	1.8	1.98	0.6	1	1.2
Power (μW)	20.1	13.34	8.75	2940	46.8	12.88
Area (mm2)	4.99	0.925	1.32	0.2123	1.74	0.33
Algorithm Model	SVM	ANN	DNN	ELM	ANN	ANN
Energy Eff. (nJ/Classifi.)	N.A.	3210	2080	212	2250	234.4
Memory (kB)	20	64	N.A.	52	73	4.5
Accuracy (%)	95.8	99.32	91.6	92	99.3	96.69
Number of classes	2	5	5	2	2	5

presents a comparison of our proposed ECG processor with other works. It can be seen that our design achieves low power and a low hardware overhead while also having a good classification performance. The accuracy of our design is lower than that of [7,11]. It should be noted that the use of complex neural network models in [7] leads to more memory overhead and computing time, which further increases the classification energy consumption. Reference [11] is capable of processing various bio-signals and features a reconfigurable neural network engine. However, the large-scale MAC unit array and the high SRAM usage of up to 73 kB result in excessive hardware costs, and each classification consumes nearly 10 times the energy compared to our design. The classification engine in [4] can only perform two-class classification and requires a complex feature extraction engine, which occupies a considerable chip area and power. In [10], the inference engine also classifies abnormal beats into two classes. To support multi-dimensional inputs, 10 processing elements (PEs) and a large-capacity matrix memory are employed. However, its power consumption is unacceptable for wearable ECG monitoring. Reference [8] has the lowest power in this table and also has five types of classification. However, its prediction accuracy is relatively low, and the classifier based on 4-layer ANN consumes more energy in the inference. It should be mentioned that our design consumes the fewest memory resources in the above designs, which is suitable for low-cost portable healthcare devices. Compared with commercial chips such as MAX30003 [20], our design can not only monitor HR in real-time but also rapidly detect cardiac arrhythmias with low power and classify abnormal beats into five classes, which is important for the early prevention of heart diseases.

We will improve this ECG processor ASIC in terms of three aspects in the future. (1) Improve configurability: In order to adapt the algorithm model to different application scenarios, the hardware can be improved to achieve a configurable number of neurons in the hidden layer and output layer; (2) Power optimization: By reducing the bit-width of weights or lowering the activation rate of the classification engine, further power reduction can be achieved; (3) Function expansion: Integrating this design with an analog front-end (AFE) to form an efficient cardiac sensor chip.

5. Conclusions

This paper proposes an ECG processor ASIC based on ANN, which integrates heart rate monitoring and arrhythmia detection functions. Thanks to the proposed hardware efficient R-peak detector and the lightweight classification engine based on feedforward ANN, this design achieves a prediction accuracy of 96.69% with only 4.5 kB of memory overhead. The proposed algorithm model with low computation complexity, combined with the hardware reuse strategy applied to the ECG pre-processing engine and classification engine, significantly reduces the chip area overhead and improves energy efficiency. By utilizing a configurable parameter buffer, this ASIC can easily update the NN model to adapt to application differences. The implementation results indicate that the proposed design has a comparable performance with state-of-the-art ECG processors, achieving a good compromise between performance and cost. Thus, it can be stated that this ECG processor can be integrated in ultralow power healthcare devices for detecting arrhythmia efficiently.