Design and Optimization of a Petri Net-Based Concurrent Control System toward a Reduction in the Resources in a Field-Programmable Gate Array

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The proposed research method is strictly aimed at further practical applications. The authors present the design technique aimed at the effective implementation of the modeled concurrent control system within the FPGA device. The main goal is the reduction in the logic resources of the destination FPGA by adequate modeling and optimization of the system. The proposed idea is illustrated by a real-life application of the photovoltaic control system implemented in the FPGA device from Xilinx (Artix-7 family).

Abstract

A novel design technique of a Petri net-based concurrent control system is proposed in this paper. The idea is oriented on the effective implementation of the system within the FPGA device. In order to reduce the resources of the targeted device, the concurrent control system is optimized by the use of the authors’ techniques. The complete design flow is shown, including the modeling of the system by an interpreted Petri net, its further transformation to the hardware description language, adequate logic optimization, and final implementation within the destination FPGA. The presented method is explained by a case study example of the photovoltaic control system and compared with the already known technique. The performed experiments indicated a very high effectiveness of the proposed technique. It is shown that the photovoltaic control system designed according to the presented method reduces the logic resources of the destination FPGA device by up to 28%.

1. Introduction and Problem Formulation

Petri nets, a versatile and powerful formal modeling tool, have been instrumental in advancing the design process of control and complex systems [1]. Originally introduced by Carl Adam Petri in 1962, Petri nets provide an intuitive graphical representation for describing and analyzing the dynamics of concurrent systems [2]. Over the years, Petri nets have found widespread applications in various domains, including computer science [3], manufacturing [4,5,6], biology [7], and cyber-physical systems [8]. Recently, the Petri net-based modeling approach has become especially popular in the modeling of real-life industrial systems (e.g., they are applied by manufacturing companies) [9,10,11].

The main advantage of Petri nets lies in their simplicity and graphical formal representation, which can be constructed relatively very easily. In addition, a Petri net can also be considered as a mathematical modeling framework that reflects the behavior of systems through the directed bipartite graph. Such a graph consists of places and transitions that are connected by directed arcs [12]. A place is active (marked) if it contains a token. Places that are marked at the same time represent states (markings). Furthermore, transitions reflect actions in a system. In particular, a transition may fire, by removing tokens from all its input places and relocating them to all its output places. Consequently, such an action changes the state in the system [13]. Furthermore, tokens may be used to model resources of the system elements [14] or indicate a logical behavior of the system [13,15]. Finally, Petri nets are heavily supported by formal analysis techniques [1,16,17,18]. There exist methods that allow for verification (sometimes even validation) of the system at the early specification stage. Such a combination of graphical and mathematical approaches makes Petri nets an intuitive and comfortable tool for the modeling, analysis, and verification of systems that strongly utilize concurrency [19,20].

Moving on to the concurrency aspects, it should be emphasized that Petri nets reflect such a relation by their nature [21]. In particular, one or more places can be marked at the same time. It means that operations associated with those places are executed concurrently. This makes Petri nets applicable in many areas of human life, especially including industry applications [22]. For example, they can be found in modern industries, such as resilient manufacturing, where 3D printing techniques are applied [23]. It should also be noted that Petri nets provide a robust means of modeling the intricate interactions and dependencies in such systems, allowing for a detailed examination of their behavior [24].

On the other hand, the modeled concurrent system ought to be carefully examined against possible errors and designer mistakes. Systems that involve concurrency are exposed to serious risks, including deadlocks or an infinite number of states (if wrongly designed). There are two fundamental properties of Petri nets that are related to the above mentioned problems: liveness and boundedness [25]. The first one, liveness, guarantees that a system can reach any desirable state under certain conditions (formally after a final firing sequence), ensuring that the system remains responsive and operational at all times [26]. Furthermore, boundedness implies that the number of tokens in a Petri net does not exceed predefined limits in each place, preventing uncontrolled behavior or resource depletion [27]. An unbounded Petri net with those specification assumptions could lead to uncontrolled behavior [28]. Such a condition can be defined more strictly. There exist Petri net systems that are required to be 1-bounded (safe) [29]. This means that in each place, in any state, there can be at most only one token. This restriction is especially useful in the case of binary control systems, where safeness assures the accurate logical behavior of the system [30,31].

Let us move on to the interpreted Petri nets. Such a class is an extension of the ordinary Petri nets; however, they additionally contain input and output signals that permit communication with the environment [6,13,32]. These extensions can capture real-world phenomena, such as reading from sensors or activating tasks [33]. Input (logical) signals are associated with transitions while outputs are assigned to places [11]. In the interpreted Petri net, a transition must additionally fulfil a logical equation of its input signals to be fired. This is an extended rule of an ordinary Petri net, where the firing of a transition requires a token at all input places only. However, this rule can be considered as a great advantage of interpreted Petri nets, since input signals may be used to resolve conflicts in non-free choice nets [13]. In short, a conflict in a Petri net corresponds to a non-deterministic situation, where two or more transitions may be fired. Therefore, such input signals may resolve conflicts very easily and comfortably. Finally, output signals are associated with places. Usually, they represent operations executed by the Petri net-based system. Sometimes, such signals can also trigger (activate) associated tasks especially in management systems [5]. In conclusion, it should be noted that interpreted Petri nets are live and bounded (or safe) by their definition. This is a huge advantage of this class, since the described system is assured to be absent of deadlocks and to have a finite number of states. On the other hand, such an excessive demand requires a solid examination of the system at the early prototyping stage.

Finally, let us briefly introduce Field-Programmable Gate Arrays (FPGAs) and relate them to Petri nets. In general, an FPGA is a hardware device that can be reprogrammed in order to perform specific logic operations. A typical FPGA consists of logical blocks whose core is a look-up table (LUT) [34]. LUTs are in charge of the realization of combinational logic (usually up to 5–6 variables). Furthermore, FPGAs include flip-flops to perform sequential operations. Due to their flexibility, and high performance, FPGAs have found applications in a multitude of industries, including aerospace, automotive, and telecommunications [35,36]. It is worth noting that advanced FPGA platforms allow for dynamic partial reconfiguration [37,38,39]. This allows for changing the behavior of a part of the system without turning off the device. Thus, it has found application in special critical fields such as Mars missions [40]. Leveraging Petri nets to model control systems, especially when targeting FPGA implementation is beneficial also due to their concurrent nature [41]. It should be underlined that both—Petri nets and FPGAs—are concurrent by nature. Contrary to the sequential systems, where particular operations are performed in sequence, concurrent systems allow for simultaneous operations at the same time. Therefore, FPGAs seem to be an excellent destination for the implementation of Petri-net based systems [13,42,43].

In general, the implementation of the Petri net-based concurrent system within FPGA is a relatively easy process. The modeled system is transformed to the hardware description language (HDL), which is a base for further realization within the FPGA. In short, the functionality of particular places and transitions of a Petri net are translated into the set of equations that are written within the hardware language Verilog or VHDL (Very High Speed Integrated Circuit Hardware Description Language) [44]. Going into detail, each place of a Petri net is assigned to one flip-flop in a sequential circuit [13]. Thus, a set of flip-flops active at the same time reflect the current marking (state) of the system. Similarly, transitions are transformed into logical functions (combinational circuit) [43]. Those functions stimulate flip-flops associated with places. Finally, output signals are directly assigned to the particular places [13,43]. The technique described above is effective (the translated system reflects the model) and relatively easy to perform (the transformation can be conducted automatically), thus it seems to be the most popular nowadays. However, there is an important drawback that refers to the relatively high utilization of hardware resources of an FPGA. As already mentioned, an FPGA consists of LUTs and flip-flops (FFs). Although a single LUT allows for the implementation of any logic function, it is limited to a relatively small number of variables (usually 5–6). This means that larger functions ought to be divided (decomposed) into subfunctions with a small number of variables [45,46,47,48]. Obviously, such a decomposition heavily influences the number of logic blocks used to implement the modeled system. Therefore, the final implementation of the Petri net-based design may drastically increase. Let us now briefly overview the most popular logical function decomposition techniques of systems implemented within an FPGA.

The first decomposition algorithms were developed in the 1990s and they were initially oriented on the optimization of the gate structures (with further adoption to FPGAs). These methods include the MIS-PGA, ASYL, Chortle, and Xmap algorithms. Their essence was to optimize the multi-level implementation of logical functions. Later, as a result of the development of decomposition methods, tools such as Demain [49], FGsyn [50], and Decomp [51] were developed. Those techniques are based on the classical decomposition model [52], and they provide efficient solutions (in terms of the number of logic blocks or the number of layers), but their main drawback is high computational complexity. Therefore, the optimization possibilities of complex circuits were highly limited, since the long synthesis time made them difficult to use in practical approaches. In the 2000s, plenty of academic tools appeared, together with the representation of logic functions in the form of And-Inverter Graphs (AIGs). Such a graph can be found, for example, in the ABC [53] and DAOmap [54] systems. Meanwhile, the re-synthesis techniques were developed [55,56], benefiting systems such as the Delay-Driven BDD (DDBDD) [57] and BDS-PGA 2.0 [58], which use Binary Decision Diagrams (BDDs) to represent logical functions. Furthermore, development of technology and the expansion of logic blocks in the programmable circuits resulted in the appearance of tools that permit the configuration of logic blocks, e.g., ALMmap [59].

Getting back to the current times, there is no doubt about the importance of decomposition in logical synthesis. Such a process is a subject of extensive research in the context of synthesis dedicated to FPGAs and Programmable Array Logic (PAL)-based systems [60]. Decomposition is also used in the synthesis process oriented to Complex Programmable Logic Devices (CPLDs) [61,62,63]. In logical synthesis algorithms, the way in which a logical function is represented is especially important. Functions can be represented in the form of a table description [52], cube description, and graph description. Nevertheless, methods that utilize BDDs [57,64] are of great interest. The achievements of Ashenhurst and Curtis laid the foundations for subsequent types of decomposition, but memory-inefficient decomposition tables (Karnaugh tables) were used to represent the logical functions. Looking from the terms of memory consumption, a much better solution is the BDD representation [57,58,65]. The description of logical functions in the form of BDD leads to the significant reduction in computer memory and better speed performance of operations on these functions. Moreover, a dozen standard libraries for manipulating BDDs are available. To be precise, the reduced and ordered form of BDD (ROBDD) is used. These advantages have led to the development of tools such as BDS or DDBDD and MultiDec [66] that lead to effective solutions. Good solutions are also provided by mentioned tools such as DAOmap or ABC [67], which use AIGs. The newest academic synthesis tools of industry-standard strength are coupled with HDL compilers [67,68,69]. The latest algorithms also combine the advantages of AIG manipulation [69] and the representation of functions in the form of BDD [70]. There are also many approaches to the use of BDD that allow for multiple output functions to be represented. The most popular forms of describing multi-output functions are shared BDD (SBDD) and multi-terminal binary decision diagram (MTBDD) [71]. In conclusion, it should be pointed out that there exist plenty of decomposition methods, aimed at various goals to be achieved. One of them is the minimization of the number of blocks [45,46,47,71,72], while others are focused on the optimization of the number of logical layers [66,73] or the reduction in the dissipated power [74,75,76,77]. Moreover, proper optimization strategies may target both combinational and sequential circuits [78,79]. Finally, the most important aspect lies in the adequate division of the system and effective decomposition of logic functions in order to reduce the number of utilized logic blocks (LUTs and FFs) of an FPGA.

To summarize the discussion above, the following research gaps can be noticed in the design and optimization of a Petri net-based concurrent control system oriented toward implementation within FPGA devices. Firstly, as designs become complex, using adequate effective modeling techniques becomes extremely important. The method proposed in this paper involves Petri nets, which are intuitive and comfortable modeling tools, joining the graphical and mathematical representation of the system. Another serious bottleneck in the design of concurrent control systems refers to the scalability of the concurrent systems. Therefore, this paper focuses on the reduction of logic resources to ensure efficient FPGA utilization. Such an optimization involves effective decomposition techniques which are crucial in the proposed techniques. In conclusion, in this work, a novel technique oriented toward the adequate modeling and design optimization of the Petri net-based concurrent control system is proposed. The main aim of the presented method is to reduce the number of utilized logic blocks (LUTs and flip-flops) of the destination FPGA device.

The main contributions are summarized as follows:

• Proposition of a novel design technique of a Petri net-based concurrent control system oriented toward the reduction in the resources (logic blocks) of an FPGA. The presented prototyping flow applies an interpreted Petri net, and additionally permits conflict resolution in the modeled system;
• Proposition of a novel optimization technique of the Petri net-based design. The method includes both the functional decomposition of the combinational part of the system and the optimization of the sequential part of the system;
• Proposition of a photovoltaic control system as a case study of the presented prototyping flow. The applied system reflects the real-life concurrent control system further optimized and implemented within the FPGA device.
• Experimental verification of the proposed technique and comparison to the existing functional decomposition methods from the literature.

2. The Proposed Design Method of Petri Net-Based Concurrent Control System Oriented toward a Reduction in FPGA Resources

This section presents the novel designing technique of Petri net-based concurrent systems aimed at the reduction in the resources of the destination device. The description is divided into four main parts and the whole process is shown in the form of flowchart in Figure 1. Firstly, the modeling rules of Petri net-based concurrent systems are presented. This subsection is supplemented by the main definitions and preliminaries related to the presented method. Subsequently, a transformation method of the Petri net-based model to the Verilog hardware language is explained. Such a description is an input for the proposed reduction (decomposition) technique. Finally, the implementation aspects of the modeled system within an FPGA are explained.

2.1. Modeling of the Petri Net-Based Concurrent Control System

The first step in the presented design refers to the modeling of a system by an interpreted Petri net. Based on the informal description of the concurrent control system, a Petri net-based specification is created. In order to present the proposed Petri net-based modeling technique, let us firstly define the main notations related to the discussed topic [1,12,13,27,80,81].

Definition 1.

A Petri net is a 4-tuple  $N=\left(P,T,F,M_0\right)$  with  $P=\left\{p_1,\dots ,p_n\right\}$  as the finite set of places,  $T=\left\{t_1,\dots ,t_m\right\}$  as the finite set of transitions,  $F\subseteq \left(P\times T\right)\cup \left(T\times P\right)$  as the finite set of arcs, and  $M_0$  is the initial marking.

Definition 2.

A marking of a Petri net  $N=\left(P,T,F,M_0\right)$  assigns to each place a nonnegative integer  $M:P\to \mathbb{N}$. A marking can be considered as a distribution of tokens in the Petri net places. A marked place contains at least one token.

Definition 3.

A transition  $t\in T$  is enabled in marking  $M$  if each of its input places contains at least one token. An enabled transition  $t$  is fired (with exception of Definition 7, which is valid for interpreted Petri nets). The firing of a transition  $t$  changes the marking from  $M$  to  $M^{\prime }$  by removing a token from each of the input places of  $t$, and it adds a token to each output place of  $t$. A marking  $M$  is reachable if it can be obtained from the initial marking  $M_0$  by a sequence of transition firings.

Definition 4.

A Petri net  $N$  is safe if for every reachable marking  $M$  and every place  $p\in P$ :  $M\left(p\right)\le 1$.

Definition 5.

A Petri net is live if from any marking of a Petri net it is possible to fire any transition in the net by a sequence of firings of other transitions.

Definition 6.

An interpreted Petri net is a live and safe Petri net  $\mathcal{N}=\left( P,T,F,M_0, X, Y\right)$, where  $X=\left\{x_1,\dots , x_o\right\}$  is a finite set of input signals and  $Y=\left\{y_1,\dots , y_p\right\}$  is a finite set of output signals. Such a net is required to be safe and live to fulfil the implementation assumptions in FPGAs (see the next subsection for more details and examples).

Definition 7.

A transition  $t\in T$  of interpreted Petri net  $\mathcal{N}=\left( P,T,F,M_0, X, Y\right)$  is fired when and only when it is enabled, and all its input signals (from the set X) are fulfilled. The firing of a transition changes the marking in the same way as it is shown in Definition 3.

The main benefit of Petri nets is the possibility of easy representation of concurrency, but sequential processes can be expressed naturally and intuitively. Let us explain it by an example. Consider a concurrent control system shown in Figure 2. There are  $\left|P\right|=$  10 places and  $\left|T\right|=10$ transitions in the system specified by an interpreted Petri net  ${\mathcal{N}}_1$. Moreover, there are  $\left|X\right|=6$ input binary signals,  $X=\left\{s,e_1,e_2, x_1,x_2,x_3\right\}$, and  $\left|Y\right|=5$ output binary signals assigned to transitions and places, respectively. Let us briefly describe the behaviour of the system. At the beginning, three places are initially marked:  $p_3, p_5,p_6.$  This means that three processes are performed concurrently. In particular, operations  $y_2$  and  $y_3$  are executed (related to places  $p_5$  and  $p_6$, respectively), while the third process waits until those operations are finished. The first one ( $y_2$) is dependent on input signal  $e_1$. Once this signal becomes active, transition  $t_2$  is fired and the token is moved from  $p_5$  to  $p_2$. Similarly, input signal  $e_2$  allows for firing  $t_4$  and moving a token from  $p_6$  to  $p_4$. Note that both operations ( $y_2$,  $y_3$) are typically concurrent, while they may (but not have to) occur at the same time. Once the system reaches a state with marked places  $p_2, p_3, p_4$, transition  $t_3$  is fired. Note that there are no input signals assigned to  $t_3$, thus it is fired once all its input places contain a token. As the consequence, tokens from all input places of  $t_3$  (that is, from places  $p_2, p_3, p_4$) are consumed and added to each of its output places:  $p_5, p_6$, and  $p_7$. In such a resulting state, three tasks are executed concurrently. Two of them refer to operations  $y_2$  and  $y_3$, as it was already described (during the initial marking). The remaining process is related to place  $p_7$. Depending on the combination of input signals  $x_1, x_2, x_3$, three possible places can be reached by this particular process:  $p_1$  (upon firing of  $t_5$),  $p_8$  (when  $t_6$  is fired), or  $p_9$  (upon firing of  $t_7$). Note that the input signals here play an essential role and allow for enabling the particular transition. In general, Petri nets are not deterministic, and such a situation is called a conflict [41,43,82]. Such a problem can be easily resolved by application of the input binary signals—this is one of the additional (and huge) benefits of interpreted Petri nets. Finally, the system executes operation  $y_1$  (if  $t_5$  is fired),  $y_4$  ( $t_6$), or  $\overline{y_1}$  ( $t_7$). The first possibility returns to  $p_7$  (once input signal  $s$  becomes active and transition  $t_1$  is fired), while the remaining two eventually lead to the initial state, where place  $p_3$  is marked.

The concurrent control system presented in Figure 2 illustrates the power of Petri net-based specification. There are several tools that support the modeling of Petri net-based systems. A graphical specification of a model can be prepared for instance within Input Output Place Transition-Tools v 1.2 (IOPT-Tools) [83] or Platform Independent Petri net Editor 2.5 (PIPE) [84]. Moreover, the model of the system can be easily examined [20] (initial verification) and even validated (simulated). The concurrent control system described by interpreted Petri net  ${\mathcal{N}}_1$  is live and safe. This means that each transition of the net can be reached (by a sequence of firing of other transitions). Moreover, there is at most one token at any place (in each reachable state) in the system. Such a verification (of liveness and safeness) can be performed within the modeling tools (e.g., PIPE). However, in the case of more complex concurrent control systems, advanced methods and tools can be applied, such as Hippo [19,20,29,31], GreatSPN [85], and IOPT-Tools [19,83,86,87].

2.2. Transformation of the Petri Net-Based Description into Verilog HDL Code

In order to implement the Petri net-based system within an FPGA, the model ought to be transformed from the graphical notion into the hardware description language. There exist several techniques that allow for such a transformation. In this paper, we follow the technique shown in previous authors’ works [13,41,43], while as a hardware language, Verilog HDL is applied. Note that such a description is essential for further functional reduction (described in the next subsection).

In general, the method is based on the description of the behavior of the system. The Verilog model consists of three main blocks. The first one refers to the transitions; the second represents the states (concurrently marked places); while the remaining one is related to the binary outputs of the Petri net-based concurrent control system. Let us describe each of them in detail.

The behavior of transitions is described by logical equations. Each equation is formulated as a logical conjunction of input places and conditions of a particular transition. From the technical point of view, continuous assignments (assign statements) are applied. Listing 1 shows the equations for the concurrent control system specified by  ${\mathcal{N}}_1$. There are ten transitions in the presented interpreted Petri net. Each assignment corresponds to the logical condition that enables a particular transition. For example, the first line continuously assigns a logical expression: p[1]&s to transition  $t_1$. This means that transition  $t_1$  is enabled if two conditions are fulfilled: (1)  $p_1$  is marked (contains a token), and (2) the input signal  $s$  is active (high value). Another line (3) assigns a logical condition p[2]&p[3]&p[4] to t[3], which means that transition  $t_3$  is enabled when all three of its input places ( $p_2$,  $p_3$,  $p_4$) contain tokens.

Listing 1. Transition equations for the concurrent control system modeled by  ${\mathcal{N}}_1$.

States (markings) of the system are represented by the procedural assignments, within the always block. Such a description involves equations for places of the interpreted Petri net. In the proposed solution, each place is represented by a single register. Therefore, markings simply refer to the set of active registers (places), in exactly the same manner as in the case of the Petri net-based model. The switching of markings depends on the active transitions (that are fired); thus, the equation for each place includes a function of its input transitions.

The Verilog description of states (places) for the concurrent control system specified by  ${\mathcal{N}}_1$  is shown in Listing 2. It is assumed that the system is oscillated by a clock signal (denoted as clk). Moreover, there is an asynchronous reset signal that zeroes the system (that is, resets to the initial marking). There are ten places in the presented interpreted Petri net. The first statement (line 3) in the presented listing refers to zeroing the system to the initial state. Simply, if the reset signal is active, the binary value 0010110000 corresponding to the initial marking is assigned to the vector p. Note that reset is asynchronous, therefore it is activated despite the clock signal. Otherwise (that is, if reset is not active), each entry of the vector p is assigned by an equation according to the token distribution in particular places. For example, place  $p_3$  (line 8) is active (holds a token) if its output transition  $t_3$  is not enabled (by holding up the current state), or, if its input transition  $t_{10}$  is executed. Similarly, the description for place  $p_7$  involves the following: p[7]&~t[5]&~t [6]&~t[7]|t[1]|t[3]. This means that  $p_7$  becomes active if one of three conditions is fulfilled if either all its output transitions ( $t_5,t_6,t_7$) are not enabled or one of its input transitions ( $t_1$  or  $t_3)$  is executed. Note that in the above descriptions, procedural assignments are used; thus, the values of particular places are registered. Such place registers strictly refer to the current state of the system.

Listing 2. Place equations for the concurrent control system modeled by  ${\mathcal{N}}_1$.

The third block refers to the binary outputs of the system. The proposed description mixes continuous and procedural assignments, according to the designer’s needs. Typically, continuous assignments are used. Such a situation is more common when the modeled system controls objects by sending signals. However, outputs can be also registered in order to maintain the value. This can be especially useful if the particular output should be activated in the particular state and deactivated with the other marking. Recall Petri net  ${\mathcal{N}}_1$. Output  $y_1$ is activated by place  $p_1$  and deactivated by  $p_9$. Therefore, this particular signal is described by procedural assignment, as shown in Listing 3 (lines 1–7). All the remaining outputs are described by continuous assignments [41,43].

Listing 3. Output equations for the concurrent control system modeled by  ${\mathcal{N}}_1$.

It should be noted that the transformation process can be automated. There exist tools that permit the conversion of a Petri net-based description to hardware description languages, either VHDL (e.g., IOPT-Tools [83]) or Verilog (e.g., Hippo tool [19,20,88]). Therefore, the designer is not forced to know technical details nor advanced mechanisms in regard to the particular hardware language.

To conclude the discussion presented above, let us underline that the HDL model is essential for the further functional reduction (described in the next subsection). All three blocks included within Verilog code are based on the logic equations. Therefore, the adequate realization (implementation) of such functions within an FPGA is extremely important in the context of utilized logic blocks. The next subsection proposes a novel decomposition technique of logic equations. The main aim of the presented solution is the reduction in the FPGA resources.

2.3. Optimization of the Verilog HDL Code of the Concurrent Control System

This step consists of two main operations. The first one is related to the optimization of the sequential part of the system, while the second refers to the decomposition of logic functions (combinational part). Note that the presented technique is strictly tied with the presented modeling process and it assumes that the system utilizes the single clock domain (all the registers are oscillated by the same clock signal).

2.3.1. Optimization of the Sequential Part of the System (Redundant Sequential Logic Optimization)

Firstly, the logical equations written in Verilog ought to be transformed into a form that can be efficiently applied in the optimization process. In the proposed approach, the reduced ordered binary decision diagram is utilized (ROBDD, for simplicity called BDD) [89]. Such a graph permits the storage of logical functions in a memory-efficient manner.

Once the logical equations are transformed to a BDD, the optimization of the redundant sequential logic is performed. This process refers to searching for the equivalent parts of the design that can be reduced in order to minimize the amount of resources required for the implementation of the system within the FPGA device. Let us explain this by an example. Assume that there are two functions:  $f_1=x_1+x_2$  and  $f_2=x_1{\overline{x}}_2+x_1{x}_2+{\overline{x}}_1{x}_2$. Those functions are equivalent, and  $f_1=f_2$. Therefore, the design can be optimized and only one of those functions is implemented in the hardware. In the case of the BDD, checking whether two functions are equivalent is relatively easy, and it just requires comparison of whether two pointers are equal. However, reduction of the number of flip-flops can be much more complicated. Consider an obvious example. Assume there are two flip-flops, controlled by the following functions:

$$\begin{array}{l}{D}_1=Q_3 x_1+\overline{Q_3} x_2\hfill \\ D_2=Q_3 x_1+\overline{Q_3} x_2+x_1{x}_2\hfill \end{array}$$

(1)

Both functions are equivalent:  $D_1=D_2$. What can be proved by algebraic transformations is as follows:

$$\begin{array}{ll}\hfill D_1& =Q_3 x_1+\overline{Q_3} x_2\\ & =Q_3 x_1 1+\overline{Q_3} x_2 1\\ & =Q_3 x_1\left(1+x_2\right)+\overline{Q_3} x_2 \left(1+x_1\right)\\ & =Q_3 x_1+Q_3 x_1{x}_2+\overline{Q_3} x_2+\overline{Q_3} x_2{x}_1\\ & =Q_3 x_1+\overline{Q_3} x_2+\left(Q_3+\overline{Q_3} \right)x_1{x}_2\\ & =Q_3 x_1+\overline{Q_3} x_2+1 x_1{x}_2 = D_2\end{array}$$

(2)

The same is immediately visible when using the BDD representation of Boolean functions (Figure 3a). In the computer implementation of libraries for operating on BDD (or more precisely ROBDD), the logical function is a pointer to a structure in the memory (representing a graph node) [89]. The structure contains two pointers to two descendants for the values of the variable 0 and 1. When performing any operation on a BDD, it is checked using a hash table to see if the node already exists in memory, so as not to duplicate it. BDD libraries ensure the canonicity of logical functions, i.e., unambiguity and uniqueness of representation. Checking if two functions are equal is limited to checking if two pointers are equal to each other.

Nevertheless, replacing the mentioned two flip-flops with a single one requires two conditions to be fulfilled. Firstly, their excitation functions ought to be the same. Furthermore, the initial values of both flip-flops must be the same:  $Q_1^{t=0}=Q_2^{t=0}$  (which can be easily checked). The replacement of two flip-flops by a single one is shown in Figure 4a.

Another possibility refers to a hidden equivalence, where the excitation functions are not the same (Figure 4b), but the flip-flops could be reduced. Let us underline that commercial tools are not always able to optimize the number of registers. Therefore, in this paper, a novel reduction technique is proposed. Assume there are two flip-flops with the following excitation functions:

$$\begin{array}{l}{D}_3=Q_3 x_1+\overline{Q_3} x_2\hfill \\ D_4=Q_4 x_1+\overline{Q_4} x_2\hfill \end{array}$$

(3)

Clearly, the above functions are not equal. Moreover, they correspond to the different pointers in the BDD (Figure 3b). Finally, both functions  $D_3=f(Q_3, x_1, x_2)$  and  $D_4=f(Q_4, x_1, x_2)$  have different arguments. However, due to the fact that the system is oscillated by the same clock signal, they can be transformed into the equivalent form.

Let us explain this with an example. Assume that at time  $t=0$  both flip-flops are initialized with the same value, e.g.,  $Q_3^{t=0}=Q_4^{t=0}=0$. Then, after inserting that into expression (2), we obtain the same functions  $D_3^{t=0}=D_4^{t=0}=x_2$. Since at the moment  $t=0$  the excitation functions of the flip-flops are equal, at the next moment  $t=1$, the Q values remain the same:  $Q_3^{t=1}=Q_4^{t=1}$. Furthermore, if both flip-flops are initialized by value  $Q_3^{t=0}=Q_4^{t=0}=1$, we obtain  $D_3^{t=0}=D_4^{t=0}=x_1$, and thus  $Q_3^{t=1}=Q_4^{t=1}$. By repeating the above for every time moment t, it can be noticed that both flip-flops are equivalent.

For the general case, we formulated Theorem 1.

Theorem 1.

Two synchronous flip-flops  $D_k$  and  $D_l$  are described by Shannon expansion:

$$\begin{array}{c}{D}_k=Q_k f_{1k}+\overline{Q_k} f_{0k}\\ D_l=Q_l f_{1l} +\overline{Q_l} f_{0l}\end{array}$$

(4)

where  $f_{1k}=f\left(Q_1,\dots , Q_k=1, \dots ,Q_n, x_1,\dots ,x_m\right)$  and  $f_{0k}=f\left(Q_1,\dots , Q_k=0 ,\dots , Q_n, x_1,\dots ,x_m\right)$  are equivalent if

(a) 

cofactor functions are equivalent,  $f_{1k}=f_{1l}$  and  $f_{0k}=f_{0l}$  ,

(b) 

initial values for both flip-flops are identical  $Q_k^{t=0}=Q_l^{t=0}$.

Proof of Theorem 1.

We show that for any time moment t, if  $Q_k^t=Q_l^t$  holds, then it implies that  $Q_k^{t+1}=Q_l^{t+1}$. Since the operation of D flip-flops can be described by  $Q_k^{t+1}=D_k^t$  and  $Q_l^{t+1}=D_l^t$, Equation (4) can be rewritten in the following form:

$$\begin{array}{l}{Q}_k^{t+1}=Q_k^t f_{1k}+\overline{Q_k^t} f_{0k}\hfill \\ Q_l^{t+1}=Q_l^t f_{1l} +\overline{Q_l^t} f_{0l}\hfill \end{array}$$

(5)

Inserting condition (a)  $f_{1k}=f_{1l}$  and  $f_{0k}=f_{0l}$  into Equation (5), we obtain the following:

$$\begin{array}{l}{Q}_k^{t+1}=Q_k^t f_{1l}+\overline{Q_k^t} f_{0l}\hfill \\ Q_l^{t+1}=Q_l^t f_{1l} +\overline{Q_l^t} f_{0l}\hfill \end{array}$$

(6)

If  $Q_k^t=Q_l^t$, we obtain  $Q_k^{t+1}=Q_l^t{f}_{1l}+\overline{Q_l^t}{f}_{0l}=Q_l^{t+1}$. Hence, if at time t = 0 (b)  $Q_k^{t=0}=Q_l^{t=0}$  holds, it implies that  $Q_k^{t=1}=Q_l^{t=1}$. Similarly, if  $Q_k^{t=1}=Q_l^{t=1}$  holds, it implies that  $Q_k^{t=2}=Q_l^{t=2}$, and so on, for every time moment t. □

Cofactors of a function can be obtained in a very efficient way from the BDD. For the flip-flops considered in our example, the BDD cofactors of  $D_3$  (versus  $Q_3$) and  $D_4$  (versus  $Q_4$) are shown in Figure 3b (corresponding schema in Figure 4c). If the order of variables in a BDD diagram is arranged in such a way that the root of the diagram is associated with the variable Q, then the child nodes constitute cofactors. To summarize, searching for equal cofactors can be conducted relatively easily with the BDD, effectively reducing the number of flip-flops.

Once the sequential part of the system is optimized, the decomposition of logic functions is executed. Such a process is a perfect supplement for the redundant sequential logic optimization and may strongly influence the utilized resources of an FPGA.

2.3.2. Optimization of the Combinational Part of the System (Decomposition of Logic Functions)

The main aim of the logic function decomposition is to reduce the number of LUT blocks of the destination device. Realization of the system within an FPGA imposes a limit on the number of variables of a single function. Therefore, if a function contains more variables than the number of inputs of the LUT block, it ought to be decomposed to make the implementation possible.

In general, the essence of the decomposition refers to the proper division of the system into blocks with a given number of inputs. The function of n-variables  $f\left(X\right), X=x_1,x_2,\dots ,x_n$  can be represented as  $h\left(g_1\left(X_b\right),\dots , g_m\left(X_b\right), X_f\right)$, where  $X_b$  is the bound set and  $X_f$  is a free set ( $X=X_b\cup X_f$), when the number of column patterns of the partition matrix is less than or equal to  $2^m$  [52]. The division of variables involves searching for the sets  $X_b$  and  $X_f$. If the common part of the sets  $X_b$  and  $X_f$  is empty, we say that the decomposition is disjoint.

Splitting the variables into two subsets is equivalent to making a cut in a binary decision diagram. The nodes above the cut line form a bound set, and those below are a free set. The nodes below the cut line that are pointed by the cut edges are called cut nodes. The number of cut nodes corresponds to the number of column patterns in the Ashenhurst–Curtis decomposition or the number of equivalence classes in the Roth–Karp decomposition [52]. In the general case, for n cut nodes,  ${\log }_2\left(n\right)$  bits are needed to distinguish them. Several functions g_i are then created,  $i=1,\dots ,{\log }_2\left(n\right)$. The number of cut nodes depends on the choice of variables that create the free and bound set, i.e., on the order of variables in the graph and on the level at which the cut will take place. When looking for a decomposition allowing the implementation of the circuit using k-input LUT blocks, the cutting level is usually set to k, counting from the root of the diagram.

Let us explain the decomposition by an example. Assume a function of four variables  $f\left(x_1,x_2,x_3,x_4\right)$  to be realized within a LUT3 block (k = 3). Since the number of variables (four) exceeds the number of available inputs of the LUT (three), the function ought to be decomposed. Figure 5 illustrates the decomposition process. Firstly, the BDD is cut off below the third level of nodes counting from the root (Figure 5a). The bound set is formed by variables  $\{x_1, x_2, x_3\}$, and free set by  $\left\{x_4\right\}$. There are four cut nodes a, b, c, and d. To encode four patterns,  ${\log }_2\left(4\right)=2$  bits are required (two g functions:  $g_1$  and $g_2$). The encoding of cut nodes by  $g_1,g_2$  functions is shown in Figure 5b,  $g_1,g_2$  = 00-a, 01-b, 10-c, 11-d, which means that two new functions  $g_i\left(x_1,x_2,x_3\right)$  are created. Replacing the upper part of the BDD for function f (variables marked in green in Figure 5a) with newly created  $g_i$  functions gives diagram  $h\left(x_4,g_1,g_2\right)$, which is presented in Figure 5c (h is functionally equivalent to f).

Furthermore, the  $g_i$  functions define the bound block of the partitioned circuit (Figure 5d), and the free block is defined by h. The number of inputs of both obtained blocks does not exceed three; thus, the system can be implemented within a three-input LUT block. This means that the aim of the decomposition has been achieved.

The above example shows the general idea of the decomposition technique applied in this work. However, in practice, the number of variables very often significantly exceeds the number of LUT inputs. In such a case, the decomposition steps are iteratively repeated.

Figure 6 illustrates such a situation. There are six arguments in the initial function that are going to be realized with three-input LUTs. The first step of the decomposition is similar to the previous example. The diagram of function f is cut off below the third level of nodes, as shown by green dashed line in Figure 6a.

Four cut nodes a, b, c, and d are encoded with two functions  $g_1,g_2$. The upper part of the diagram with variables  $\{x_1, x_2, x_3\}$  is replaced with nodes associated with  $g_1,g_2$, and it forms a new diagram  $h_1\left(g_1,g_2,x_4,x_5,x_6\right)$  (Figure 6c). The  $h_1$  function still has too many variables to implement with LUT3 blocks; thus, another round of decomposition is performed. This time, the diagram is cut below nodes associated with  $x_4$  (Figure 6c). Below the magenta dashed line, there are only two cut nodes a and c, and just a single  $g_3$  function is necessary to distinguish them (Figure 6d). By replacing the upper part of diagram  $h_1$  (variables  $\{g_1, g_2, x_4\}$) with  $g_3$  once more, the  $h_2$  diagram is obtained (Figure 6e). The resulted decomposition is suitable for hardware implementation with LUT3 blocks. The partitioned system is presented in Figure 6f.

Another important task that involves the functional decomposition is related to the multi-output functions that are more commonly used instead of single functions. In order to perform the optimization, the synthesis tools try to optimize the number of LUT blocks by sharing resources between functions. The essence of the problem is to find bound functions g which, by assigning the appropriate codes, are used in several functions of the entire group. The idea of sharing bound functions is explained by an example shown in Figure 7. It is assumed that multi-output function  $f_1{f}_2$  is going to be implemented within LUT3 blocks. The cutting line of the diagrams is drawn below the third level of the nodes. In the case of a separate implementation of both functions, four LUT3 blocks are required (Figure 7a,b).

Another possibility is merging  $f_1$  and  $f_2$  diagrams into the single multiterminal diagram, allowing for a common bound block (Figure 7c). There are six cut nodes (1, …, 6), and thus  ${\log }_2\left(6\right)=3$  functions  $g_1,g_2,g_3$  are required to encode the patterns. Before the decomposition, each of the functions  $f_1$  and  $f_2$  consist of four arguments. After the decomposition, the free blocks still include four variables ( $g_1,g_2,g_3,x_4$) (Figure 7c). This means that in such a case, the decomposition is useless, since no reduction in the number of inputs is achieved.

The above example clearly shows that the sharing of all bound functions is not always effective. Indeed, the crucial aspect refers to the determination of if an effective bound function common to  $f_1$  and  $f_2$  could be found. Figure 6d shows a table of cut nodes and paths leading from the root node to the cut nodes. Note that node c can be reached from the root  $f_1$, traversing the path  $x_1{x}_2{x}_3$  = 000 or 100 (Figure 7a) as indicated in columns 000 and 100 in the node table. Based on the node table, a graph of compliance is created, as shown in Figure 7e. Individual nodes are associated with paths of bound variables (columns of the node table). If the nodes of the graph (or columns of the table) are assigned with the same symbol (e.g., c for 000 and 100), then they are connected by an edge (e.g., red edge for c). Nodes connected by edges divide the vertices into two groups (two cliques). This division imposes an appropriate encoding which is equal to the bound function  $g{\text{'}}_1$  common for  $f_1$  and  $f_2$. This finally leads to resource sharing, as shown in Figure 7f. Due to the partial sharing of bound functions, only three LUT blocks are used to implement the bound block ( $g{\text{'}}_1,g_2,g_3$, Figure 7f), opposite to the previous version, where four LUT blocks ( $g_1,g_2,g_3,g_4$, Figure 7a,b) are used.

Concluding the presented techniques, let us underline that the decomposition of the system is crucial in terms of implementation of the concurrent system within an FPGA device. There are several possibilities and strategies related to the selection of appropriate and well-decomposable sets of functions, as well as the direction of the decomposition and the usage of the appropriate complex decomposition models. Usually, a strategy is a combination of various techniques that are used in the appropriate selection of various parameters with respect to the implementation details. The techniques that are applied in this work follow the authors’ coherent synthesis strategy that is implemented within our tool called PdekBDD 1.0 (an extension of the DekBDD [66]).

2.4. Realization of the Concurrent Control System within FPGA

Finally, the designed Petri net-based concurrent control system is implemented within an FPGA device. This process can be divided into two main steps. Firstly, the HDL code is synthesized logically independent of the internal device structure (logic synthesis), while the second step refers to the physical implementation of the system within the FPGA (translate, map, and place and route process). The whole process is strictly executed according to the vendor rules of the destination FPGA device. In this paper, guidelines for Xilinx devices are applied; however, the technique is similar for different FPGA vendors.

Initially, the optimized Verilog code of the designed concurrent control system is logically synthesized. Such a code is achieved as the result of the previous step of the presented design flow (c.f. Section 2.3), where logic equations are decomposed and optimized. Logical synthesis transforms the Verilog code into the low-level (also called “gate-level”) representation. Such a description is further implemented, that is, mapped, placed, and routed to the particular FPGA internal structure. As the result of the implementation, a programming bitstream file is produced. This file is used for the final configuration (physical implementation) of the FPGA. Since the presented technique is aimed at the reduction in the logic blocks of the programmable device, the most important values are obtained during the logical implementation step. Those results are essential and fundamental in the comparison with the traditional design flow (without applying the proposed functional decomposition method). The utilization of the device resources clearly indicates the usefulness of the introduced technique. Let us explain it in detail by a real-life example of the photovoltaic control system shown in the subsequent section.

3. Case Study: Design and Implementation of the Photovoltaic Control System

The modeling and design technique proposed in this paper is explained by a real-life case study example. Figure 8 shows the concept of a smart photovoltaic control system. The main aim of the presented concurrent system is to control the solar panels depending on their temperature and current power production in order to prevent the overloading of the electricity grid. As photovoltaic systems become more popular nowadays, the risk of grid overloading increases [90,91]. Therefore, the presented concurrent control system permits the control of the production and allows for the reduction in the production by the dynamical switching on/off of particular solar cells.

In the realm of renewable energy, smart photovoltaic (PV) control systems represent a significant leap forward in managing and optimizing energy production. However, the current landscape of these systems is characterized by a reliance on traditional control methodologies that are often rigid and unable to capitalize on the dynamic nature of solar energy fully. These conventional systems are limited by their rule-based algorithms which cannot adequately handle the variability and unpredictability inherent in solar irradiance and weather conditions. As a result, a substantial gap exists between the potential and actual performance of PV systems, leading to inefficiencies and energy losses [92]. The proposed hybrid approach seeks to bridge this gap by introducing a sophisticated layer of machine learning algorithms that can learn from data, predict future conditions, and make intelligent decisions in real time [92]. This approach is inspired by recent advancements in subsurface engineering environments, where intelligent decision-making strategies have been successfully applied to predict fire intensity and rockburst events. By adopting similar machine learning techniques, such as t-SNE for dimensionality reduction, K-Means Clustering for pattern recognition, and XGBoost for predictive modeling, the hybrid system aims to overcome the limitations of existing PV control methodologies [93]. This integration of machine learning not only enhances the adaptability and efficiency of the control system but also paves the way for a more resilient and responsive energy grid. Thus, the novelty of the hybrid approach lies in its potential to transform the smart PV control landscape, offering a solution that is both innovative and imperative for the advancement of sustainable energy systems [94].

Going into the details of the proposed photovoltaic system, each panel of the presented photovoltaic system is composed of eight solar cells (modules), denoted by  $m_1, m_2, \dots , m_8$. Furthermore, each module contains built-in sensors that allow for the measurement of its temperature and current power production. The measured data are sent to the operational center. Depending on the needs, the operational center dynamically configures the system by adjusting the number of enabled solar cells. The system works as follows. Firstly, the system examines whether the particular solar cell is enabled or disabled. The measurement is performed only for the enabled modules. If such a condition is fulfilled, the current temperature and power production are read from the sensors. The obtained data are analyzed by the modeled concurrent control system according to the over-high temperature and overload of the power. Finally, the result is sent to the operational center, which makes a decision about switching on or off the particular panels to prevent the overloading of the electricity grid. To avoid improper measurements (e.g., in the case where the particular module is disabled), particular sensors are active only if the referred module is enabled. Let us formally specify the discussed smart photovoltaic system by an interpreted Petri net.

3.1. Modeling of the Photovoltaic Control System

The Petri net-based model of the proposed photovoltaic control system is shown in Figure 9. The discussed Petri net consists of 109 places and 108 transitions.

Looking from the general point of view, the presented model consists of eight block modules that strictly refer to the particular photovoltaic modules (solar cells). Since the whole specification is large, a single module (a part of the system) is shown in Figure 10.

The specification has been initially prepared in the IOPT-Tools v 1.2 software and further exported to the Hippo system [19]. Note that the presented figures are directly taken from Hippo, and they show the general overview of the system (without input/output signals associated with places/transitions).

Table 1. Association between transitions and input signals of the interpreted Petri net.

Input Signal	Transition	Description
$e1$	$t_5$	1st module is enabled
$!e1$	$t_6$	1st module is disabled
$pw1$	$t_{108}$	Power from 1st module is correct
$!pw1$	$t_{10}$	Power from 1st module is not correct
$tp1$	$t_{14}$	Temperature of 1st module is correct
$!tp1$	$t_{13}$	Temperature of 1st module is not correct

shows the associations between the input signals and transitions. Note that there are values for the first module presented, while the associations for the remaining modules are similar. For example, signal  $e1$  (1st module is enabled) is assigned to the transition  $t_5$, etc.

Similarly, output signals are associated with places of the interpreted Petri net. There are 12 outputs in total grouped into three 4-bit vectors, as shown in

Table 2. Association between output signals and places of the interpreted Petri net.

Output Signal/Variable	Place	Description
$\left[3:0\right]statu{s}_e$	$p_{18}$	Number of enabled modules counted
$\left[3:0\right]statu{s}_p$	$p_{19}$	Number of panels with correct power
$\left[3:0\right]statu{s}_t$	$p_{20}$	Number of panels with correct temperature

. The outputs contain the values determined by the system (status of the system): the number of enabled (working) modules, the number of panels with correct power (e.g., within the assumed ranges), and the number of panels with the correct temperature.

Once the system was modeled within IOPT-Tools, it was verified and validated. The validation was conducted within IOPT-Tools by simulating the behavior of the system. However, IOPT-Tools was not able to perform the verification of the system due to the state explosion problem. Moreover, the application of another popular tool PIPE [84] was also not successful. Therefore, the modeled system was converted to the Hippo system and analyzed with the use of the authors’ methods and techniques (see [20,23,88] for more details). The verification was successful, and the system was ready for further steps of the proposed prototyping flow.

3.2. Transformation of the Petri Net-Based Description into Verilog HDL Code

The transformation of the modeled photovoltaic system to the Verilog code was performed strictly according to the rules presented in Section 2.2. Listing 4 shows the declaration of the main module and input/output signals of the system.

Listing 4. Declaration of the module of the photovoltaic system.

There are 12 registered outputs that strictly refer to the output signals described in the previous section. Moreover, there are 26 input signals in total, and 24 of them correspond to the input signals associated with photovoltaic modules, while the 2 remaining refer to the clock and reset signals. Listing 5 shows the sample equations for transitions and places. According to the rules described in Section 2.2, transitions are declared as wires and utilize continuous assignments, while places are declared as registers and involve procedural assignments. Since the system is synchronous, the states (markings) are changed with the rising edge of the clock signal. Furthermore, the asynchronous reset signal zeroes the system by returning to the initial marking. It can be noticed that there are equations that include six input variables and more. For example, the equation for transition t2 (line 04) involves eight input signals (logical conjunction of eight variables). According to the discussion shown in Section 3.3, such equations can be a good basis for the functional decomposition and reduction in the FPGA resources. However, in the presented photovoltaic system, other equations are going to be optimized.

Listing 5. Equations for transitions and places.

Listing 6 presents sample equations for the outputs. The particular values (status_e, status_p, and status_t) are computed based on the current status of sensors. The computation is performed by combinational logic. Each of the resulting equations is formulated by the disjunctive normal form (DNF) as a sum of products (minterms). Let us underline that equations for the three lower bits of each output (that is, status_e[0], status_e[1], status_e[2], status_p[0], status_p[1], status_p[2], and status_t[0], status_t[1], status_t[2]) include multiple products (even over one hundred). Therefore, the code shown in Listing 6 presents the sample values (products). The complete equations for the output status_e can be found in Appendix A (the remaining two outputs status_p and status_t are computed in a similar way). Obviously, such a huge number of minterms can be an excellent object for further optimization. The next subsection presents the functional decomposition of the discussed photovoltaic system.

Listing 6. Equations for outputs.

3.3. Optimization of the Photovoltaic Control System

According to the proposed prototyping flow, both the sequential and combinational parts of the concurrent control system are the subject of optimization. Firstly, the redundant expressions and possible number of flip-flops are minimized and reduced. The minimization process is presented for the registers representing places  $p_{99}$,  $p_{100}$, and  $p_{101}$. The original equations that describe the concurrent control system are as follows:

$$\begin{array}{l}{t}_{98}=p_{99}\hfill \\ p_{99}\leftarrow p_{99} \overline{t_{98}} +t_{95}\hfill \end{array}$$

(7)

However, inserting  $t_{98}$  into the equation of  $p_{99},$ we obtain the following:

$$\begin{array}{l}{p}_{99}\leftarrow p_{99} \overline{p_{99}} +t_{95}\hfill \\ p_{99}\leftarrow t_{95}\hfill \end{array}$$

(8)

Furthermore, the original equations are the following:

$$\begin{array}{l}{t}_{100}=p_{100} p{w}_8\hfill \\ t_{101}=p_{100} \overline{p{w}_8}\hfill \\ p_{100}\leftarrow p_{100} \overline{t_{100}} \overline{t_{101}} +t_{95}\hfill \end{array}$$

(9)

Inserting  $t_{100}$  and  $t_{101}$  into  $p_{100}$, we obtain the following:

$$\begin{array}{l}{p}_{100}\leftarrow p_{100}\left(\overline{p_{100}}+\overline{p{w}_8}\right)\left(\overline{p_{100}}+\overline{p{w}_8}\right)+t_{95}\hfill \\ p_{100}\leftarrow p_{100} \left(\overline{p_{100}}+\overline{p_{100}} p{w}_8+\overline{p{w}_8} \overline{p_{100}}+0\right)+ t_{95}\hfill \\ p_{100}\leftarrow t_{95}\hfill \end{array}$$

(10)

Finally, the original equations of  $p_{101}$  are the following:

$$\begin{array}{l}{t}_{104}=p_{101} t{p}_8\hfill \\ t_{105}=p_{101} \overline{t{p}_8}\hfill \\ p_{101}\leftarrow p_{101} \overline{t_{104}} \overline{t_{105}} +t_{95}\hfill \end{array}$$

(11)

Inserting  $t_{104}$  and  $t_{105}$  into  $p_{101}$, we obtain the following:

$$\begin{array}{l}{p}_{101}\leftarrow p_{101} \left(\overline{p_{101}}+\overline{t{p}_8} \right) \left(\overline{p_{101}}+t{p}_8\right) +t_{95}\hfill \\ p_{101}\leftarrow p_{101} \left(\overline{p_{101}}+\overline{p_{101}} t{p}_8+\overline{t{p}_8} \overline{p_{101}}+0\right)+t_{95}\hfill \\ p_{101}\leftarrow t_{95}\hfill \end{array}$$

(12)

As it is shown, places  $p_{99}$,  $p_{100}$, and  $p_{101}$  can be merged and replaced by the single flip-flop. The final result is achieved by algebraic transformations. However, the algorithm applies BDDs, where the function representation is canonical, and the equivalence of the presented flip-flops can be immediately checked.

Moving on to the optimization of the combinational part, we will follow the status_e signals, while the complete description of the whole system is presented in Appendix A (Listings A1–A4). Firstly, the logical equation is decomposed according to the procedure shown in Section 2.3 and combined with finding common subfunctions. The resulting description is shown in Listing 7. There are bound functions g₀, …, g₅ which are arguments of the logic function status_e[0], …, status_e[3]. Let us underline that the number of arguments of each decomposed function does not exceed 5. This means that they can be implemented in the single LUT 5 (a five-input LUT) blocks.

Figure 11 shows a schematic of the decomposed functions. Note that functions g₂, ..., g₅ are used only once, which means that their outputs are connected only to one input of another LUT. However, g₀ and g₁ functions are arguments of several other functions. This means that they are shared among the other functions. Such sharing is essential in the decomposition process and may lead to the significant reduction in the utilized FPGA resources.

Listing 7. Equation for output after decomposition.

3.4. Realization of the Photovoltaic System within FPGA

Finally, the designed photovoltaic Petri net-based system is implemented within the FPGA. As a destination, the XC7A100T device from the Artix-7 family is selected. The implementation process is performed within the dedicated Xilinx tool, Vivado ver. 2023.1.

To perform the final implementation, the system ought to be firstly logically synthesized. This process is executed within the Vivado 2023.1 tool, exactly according to the Xilinx requirements [95]. Logical synthesis returns no errors, which confirms the proper description of the system in the Verilog hardware description language. At the next step, the logical implementation is executed. As shown in Figure 12, this process does not return errors in the designed photovoltaic system, as well. This means that the designed system is properly prepared in accordance with the device structure and can be physically implemented within the selected FPGA.

However, in order to validate the functionality before the physical implementation, the designed system is simulated within the Vivado environment. Figure 13 shows the results of validation. Based on the stimulated input signals, adequate output signals are obtained. Let us underline that the achieved results confirm the assumptions and thus the proper functionality of the photovoltaic system. Let us now evaluate the proposed optimization technique by the analysis of the utilization of the FPGA resources.

Finally, the system is physically implemented and validated within the real FPGA device. To perform this, the Nexys4 DDR prototyping board was used. The presented concurrent control system was implemented with XC7A100T FPGA. This board contains switches and a 7-segment display, that are used to stimulate remaining input and output values, respectively. Due to the limited number of switches, there is a possibility of controlling the first five panels (it is just assumed that the remaining three are working properly). Additionally, the seven-segment display is used to indicate the number of panels successfully powered on, with correct power and optimal temperature. The count of panels with proper power or temperature is visible on the display after pressing the corresponding momentary button.

Figure 14 shows the experimental setup of the discussed system. Note that the presented figure corresponds to the results of simulation shown in Figure 13. At the illustrated state (marking) of the system, six panels are enabled (which is signalized by the seven-segment display). Indeed, two panels are turned off since switches that correspond to signals  $e1$  and  $e3$  are in a low state.

4. Discussion on the Proposed Technique and Results Obtained during the Experiments

This section discusses and evaluates the prototyping method proposed in the paper. To carefully evaluate the efficiency of the presented technique, the proposed ideas are examined and compared to the existing prototyping and optimization methods. Firstly, the results achieved during the implementation of the photovoltaic system are presented and compared to the traditional design technique. Subsequently, the proposed decomposition method is evaluated and compared to the other optimization ideas.

4.1. Discussion on the Results Achieved during Implementation of the Photovoltaic System

In order to evaluate the optimization technique presented in the paper, the results achieved in the previous section are compared with the values obtained in the traditional design flow. As a reference method (denoted as “traditional technique”), the prototyping idea shown in previous authors’ works is selected [13,41,43]. In particular, the presented photovoltaic system is designed without the application of the proposed functional decomposition. The whole procedure is the same, except for the optimization shown in Section 3.3.

To examine the proper functionality, the validation of both systems (that is, the one achieved by the proposed technique and the traditional one) is executed. To perform this, results of the simulation of both systems are compared. It should be noted that validation returns exactly the same results, which means that the applied optimizations do not interfere with the functionality of the system.

Finally, the evaluation of the presented optimization technique is performed.

Table 3. Comparison of the utilized FPGA resources.

Resources	Proposed Technique	Traditional Technique [13,41,43]
Number of utilized LUTs	91	126
Number of utilized FFs	114	114
Number of utilized IOs	38	38
Number of utilized BUFGs	1	1

shows the implementation results obtained for both techniques. The first column contains the analyzed resources: look-up tables (LUTs), flip-flops (FFs), input/output blocks (IOs), and buffers (BUFGs). The second and third columns present the utilized resources obtained with the proposed and traditional design technique, respectively.

From the values shown in Table 3, it can be noticed that the proposed technique permits dropping the number of utilized look-up tables. The traditional design flow consumes 126 LUTs, while the presented optimizations allow for the reduction in utilized logic blocks by 28%.

Furthermore, let us compare the impact of the sequential optimization—a novel technique proposed in this paper. The obtained synthesis results are as follows:

• initial system (without any optimization):         126 LUTs, 114 FFs,
• system with combinational optimization only:      95 LUTs, 122 FFs,
• system with combinational and sequential optimizations: 91 LUTs, 114 FFs.

It can be noticed that the innovative optimization of the sequential areas of the concurrent control system benefited a significant reduction in the resources. However, the application of the functional decomposition is not enough in this particular case. Although the number of LUTs decreases, the number of registers becomes much larger. Nevertheless, optimization of the redundant flip-flops proposed in this work drops down the number of utilized registers and additionally decreases the number of LUTs.

To summarize the above discussion, let us underline that in the context of FPGA resource utilization, the obtained values should be considered as a very good result. The “saved” resources can be, for example, effectively utilized by other blocks of the prototyped concurrent control system. Moreover, such a reduction is essential in the case of farms of photovoltaic panels. Assume a system that consists of hundreds or even thousands of such solar cells. The initial estimation shows that the traditional design technique allows for the implementation of up to 503 solar panels. Conversely, the application of the proposed optimization method increases the possible utilized panels up to 696. Of course, those are just initial estimations (although the implementation of photovoltaic farms is planned in our further papers); nevertheless, it shows the practical benefit of the proposed technique.

4.2. Discussion on the Efficiency of the Applied Decomposition Technique

Let us now discuss the applied optimization technique in detail. The proposed method is based on the decomposition of logic functions represented by the BDD form and extensively searching for common subexpressions. In order to evaluate the efficiency of the presented optimization idea, let us compare it with the others that are already known in the literature: Decomp [51], ABC [53], DAOmap [54], DDBDD [57], BDS-PGA 2.0 [58], and MultiDec [66].

The Decomp system uses a classic decomposition theory by Ashenhurst–Curtis, effectively coping with multi-output functions and incompletely specified functions. The ABC technique is based on the And-Inverter Graph representation of circuit and structural transformations. The DAOmap method also cuts AIGs but under mapping depth constraints. The three remaining tools apply BDDs to represent the logic functions. The DDBDD technique uses a technique called linear expansion for BDD decomposition, which, in turn, enables a dynamic programming algorithm to efficiently search through the optimization space. The BDS-PGA method heuristically manipulates BDDs with resynthesis elements. The MultiDec tool is also based on cutting BDDs but uses multiple cutting to achieve parallel decomposition and the results are evaluated with triangle tables. Finally, the MultiDec tool and the PdekBDD are able to use blocks which could be configured to five inputs and one output or four inputs and two outputs.

Table 4. Comparison of synthesis results with academic tools.

Benchmarks			Number of Blocks
Name	In	Out	Decomp	ABC	DAOmap	DDBDD	BDS–PGA 2.0	MultiDec	PdekBDD
5xp1	7	10	13	23		19	14	14	10
9sym	9	1		62		8	7	5	5
alu2	10	8		22		70	41	22	18
alu4	14	8		413	1065	1244	190		324
apex4	9	19		697	931	1314			362
apex6	135	99		181		249	186		188
apex7	49	37		98		113	71		50
b12	15	9		19				23	14
b9	16	5		36		55	40		38
clip	9	5	16	49		32	30	19	16
cm162a	14	5	18	11				11	7
cm85a	11	3		11				15	7
cht	47	36		37				23	23
count	35	16		50		50	26		37
duke2	22	29		177		208	173		189
ex1010	10	10		734	3567	4456			523
f51m	8	8	14	26				16	7
inc	7	9	24	27				21	15
misex1	8	7	14	16		14	14	11	8
misex3	14	14		699	980	1224			308
pcle	19	9		16				16	16
pdc	16	40		156	3222	4042			184
rd73	7	3	6	17				5	4
rd84	8	4	10	45		16	13	8	7
sao2			24	36					21
spla	16	46		237	2734	3243			265
sqrt8	8	4		11				6	7
t481	16	1		13		5	5	4	5
x2	10	7	17	13				13	10
			156						105
				3235					2306
Sum of blocks					11,568				1966
						15,048			2537
							810		895
								232	179
Ratio of blocks sum			1.49	1.40	5.88	5.93	0.91	1.30	1.00

shows the results of experiments where the proposed decomposition method is compared to the existing ones. The set of benchmarks is taken from [96]. The first three columns show the name and the number of inputs and outputs of the benchmark circuit. The remaining columns show the number of five-input blocks. There are gaps in the table since not all results are available. At the bottom of Table 1 is the sum of the number of blocks. In the last row, the ratio of the sum of blocks by number for a given tool to the corresponding sum of blocks for PdekBDD is presented. For all tools except BDS-PGA, the ratio is greater than 1, which means that PdekBDD gives better results. In one extreme case (ex1010 benchmark), PdekBDD gives eight times better results than DDBDD and seven times better results than DAOmap, but these tools are delay constrained. Only for BDS-PGA is the total result of PdekBDD worse by about 9%. This is mainly due to the alu4 benchmark where BDS-PGA achieves 190 blocks and PdekBDD 324. The authors’ tool gives a very low number of blocks for symmetric functions (9sym) or multi-output functions with symmetric functions (rd73 and rd84). PdekBDD achieves good results when it comes to minimizing chip area occupancy. The main disadvantage of PdekBDD is that it does not support the do not care state and the delay in the chip can only indirectly be reduced by reducing the number of blocks—there is no way to impose restrictions on the propagation time in the target system.

5. Conclusions

A novel design approach of a Petri net-based concurrent control system is proposed in this paper. The method is oriented toward effective realization of the system in an FPGA device. To achieve this, the system is optimized by authors’ techniques. In particular, the sequential and combinational parts of the system are reduced and optimized. The proposed design flow includes all the necessary steps that are required to implement the concurrent control system within the programmable device. Firstly, the system is modeled by an interpreted Petri net, which is transformed into the Verilog hardware description language. The optimization of the design is performed by reducing the redundant sequential logic and further functional decomposition. Finally, the system is implemented within an FPGA.

The efficiency of the proposed technique was verified experimentally. To perform this, a real-life example of a photovoltaic concurrent control system was designed and optimized. The obtained results indicate a high reduction in the number of utilized logic blocks compared to the traditional solutions. A photovoltaic system designed and optimized with the presented method requires 91 LUTs and 114 flip-flops, while the classical approach utilized 126 LUTs and 114 FFs. This means that the number of LUTs was decreased by 28%, which is a very good result. It should be underlined that thanks to the introduced sequential reduction in the system, the number of logic blocks significantly decreased, while the number of flip-flops remained unchanged.

Although the experimental results confirm the high efficiency of the proposed technique, there are also limitations of the presented method. First of all, the introduced sequential optimization idea can be applied only to the systems operating in a single-clock domain. This means that all registers of the design ought to be oscillated by the same clock. Nevertheless, let us point out that such a situation is usual in the case of FPGA-oriented systems. Furthermore, the presented method involves Petri net theory. Although the modeling of the system with Petri net is relatively easy and comfortable, it requires specific knowledge from the designer, especially in terms of concurrent systems oriented toward implementation within FPGA devices. Finally, the proposed method assumes the transformation of the system to the Verilog code and further optimization of the sequential and combinational parts. At this moment, the above mechanisms are semi-automated. There exists the transformation of the Petri net-based system to the Verilog code (within the authors’ Hippo system), but it ought to be supplemented by adequate input and output signals. Similarly, there is a tool for functional decomposition, PdekBDD (developed by the authors). Nevertheless, the authors of this paper plan to extend their tools, especially with such optimistic experimental results.

Plans for the future include further development of the proposed idea. In particular, it is planned to apply the verification of the system at the early prototyping stage. Such an examination may help avoid mistakes caused by the designer that are usually detected during the synthesis process. Furthermore, the presented photovoltaic system is going to be extended to the farms of panels. As shown by the preliminary research results, the traditional realization permits the implementation of 503 controllers of solar panels, while the presented technique allows for the realization of 696 cells within the single FPGA. Therefore, it is planned to perform more complex research in order to confirm such a high efficiency of the proposed technique.