Optimized Sequential State Encoding Methods for Finite-State Machines in Field-Programmable Gate Array Implementations

Abstract

A Finite-State Machine (FSM) model is frequently employed to represent the behavior of sequential circuits. In the optimal design of these circuits, it is crucial to enhance FSM characteristics such as area (implementation cost), performance (operating frequency), and power consumption. This paper proposes sequential state encoding methods that aim to reduce the area and enhance the performance of FSMs. The methods involve sequentially selecting FSM states for encoding and determining the most appropriate code for each selected state. Several state and code selection modes are introduced, allowing for consideration of the relationships between states, the number of incoming and outgoing transitions, and the number of input variables initiating transitions to each state. The code selection process takes into account the architectural features of the electronic device in which the FSM is implemented, while some code selection modes are introduced to optimize both the area and performance of the FSM. The experimental results demonstrate that the proposed approach yields, on average, a reduction in the FSM area by 19.7% (in some instances, up to twofold reduction), along with an average performance increase of 21.2% (in certain cases, up to 69.3%), compared to the Sequential mode of the Quartus system.

1. Introduction

Finite-State Machines (FSMs) are fundamental components in digital systems, extensively used in control applications, communication protocols, and various other areas requiring predictable and structured behavior. The efficiency of an FSM significantly impacts the overall performance and resource utilization of digital systems, particularly when implemented in hardware platforms such as Field-Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), and Application-Specific Integrated Circuits (ASICs).

Given the ubiquity of control devices in digital systems, FSMs are pivotal in digital hardware design. Many digital systems and devices are distinctly defined by their control logic, making the synthesis of FSMs a critical concern in every new project.

State encoding is a crucial step in FSM design, influencing the resulting implementation’s area and performance. Traditional methods for state encoding often do not fully exploit the potential optimizations available through modern hardware platforms, leaving room for improvement. The need for more advanced encoding techniques that consider the architectural nuances of contemporary electronic components is evident. The state encoding task involves addressing a complex logical combinatorial problem classified as NP-hard.

The complexity and significance of FSM state encoding have been a focal point for scientists and engineers since the inception of FSM theory. This subject garnered particular attention in the late 1980s, leading to the proposal of several methods such as two-level [1] and multi-level synthesis [2] of FSMs, directly addressing FSM state encoding. Two-level synthesis methods target the implementation of FSMs in devices equipped with two programmable matrix structures, notably CPLDs. Conversely, multi-level synthesis methods are tailored for implementing FSMs in FPGAs utilizing look-up tables (LUTs).

Given that the FSM state encoding problem is NP-hard, exact solutions are only feasible for small or specific FSMs, such as counters. As a result, numerous algorithms have been developed to address this challenge, typically categorized as heuristic (deterministic) or genetic (evolutionary) algorithms. Heuristic algorithms aim to identify local minima or maxima within a specific FSM parameter in a reasonably practical timeframe. While heuristic algorithms often produce solutions that closely approach the optimal, there are instances where their outcomes significantly diverge from the optimal result. The main drawback of heuristic algorithms stems from their tendency to become trapped in local minima or maxima.

The conventional method for addressing NP-hard tasks involves employing genetic (evolutionary) algorithms. Genetic algorithms offer the advantage of escaping local minima, thereby broadening the search space for solutions. Nonetheless, genetic algorithms are computationally intensive, require lengthy execution times, and do not consistently yield optimal solutions. Consequently, in practical applications, genetic algorithms are primarily employed to encode the states for critical FSM parameters, as the success of extensive and intricate projects hinges on the optimization of these parameters.

The challenge lies in the fact that achieving an optimal solution for the state encoding task does not ensure an optimal solution for the FSM synthesis task. This is because FSM synthesis methods employed in design tools encompass various other tasks besides state encoding. These tasks include mapping the design logic to the physical structure of electronic devices (such as FPGA, CPLD, or ASIC), meeting the time constraints of the design, and more. While state encoding primarily impacts the realization of the transition functions of FSMs, synthesis methods may integrate the implementation of both transition functions and output functions. Such integration often necessitates the use of an entirely different state encoding method.

A review of algorithms and methods for FSM state encoding is provided in [3]. Here, we focus on publications from the past few decades.

In [4], the cuckoo search optimization method is compared with the binary particle swarm optimization algorithm, the genetic algorithm, and the deterministic algorithms NOVA [5] and JEDI [6]. In [7], traditional Boolean algebra and Reed–Muller logic are proposed for minimizing the FSM area. In [8], the evolutionary algorithm called GP-ES is discussed, demonstrating good results in the design of small- and medium-sized FSMs. In [9], probabilities for each pair of code substitutions are proposed. In [10], the multi-population evolution strategy, denoted as MPES, is introduced, utilizing inner-ES and outer-ES evolution to address the problem.

In [11], a method is proposed to minimize the area of Moore FSMs by representing state codes as concatenations of codes from pseudo-equivalent state classes and collections of output functions. A similar approach for state encoding in Mealy FSMs is suggested in [12].

In [13], state encoding utilizes the values of output variables, while in [14], the input variables of FSMs are used for this purpose. In [15], multiplexers are added to the FSM circuit to use the values of output variables as state codes. In [16], anti-race state encoding is proposed for designing robust FSMs.

Several works focus on FSM state encoding for protection against unwanted attacks. In [17], a secure state encoding method for FSMs is presented to protect against power analysis attacks. In [18], a state encoding method to defend against Laser Fault Injection (LFI) attacks is introduced. In [19], a CAD tool for state encoding of FSMs robust to multiple LFI models is presented. In [20], differential power analysis (DPA) and fault injection attacks (FIAs) on FSMs are considered.

Numerous studies are dedicated to FSM state encoding for power consumption reduction. A comprehensive review of these methods is provided in [21]. In [22], a sequential algorithm, and in [23], an iterative algorithm for FSM state encoding are proposed to minimize dynamic power consumption. In [24], varying the length of state codes is suggested for the same purpose. Additionally, the authors of [25] present a state encoding method aimed at minimizing power consumption using binary particle swarm optimization and flip-flop selection.

Several studies focus on designing fault-tolerant FSMs. In [26], a heuristic algorithm for state encoding is proposed to mitigate the effects of transient faults. In [27], a method for FSM state encoding using stochastic numbers is introduced.

However, despite the extensive research on FSM state encoding, there is a lack of studies focused on methods tailored for modern electronic devices such as CPLDs, FPGAs, and ASICs.

This paper introduces a heuristic approach for FSM state encoding that sequentially selects states and assigns the most appropriate codes based on a combination of state selection and code selection modes. Our method aims to optimize both the area and performance of FSM implementations by leveraging the internal relationships between states and the specific architectural characteristics of the target hardware.

We propose several state selection modes (P, C, P_C, max_C, and max_X) to account for the intricate interconnections between FSM states. Additionally, we introduce code selection modes (FPGA, CPLD, diff_w, and max_w) that align with the architectural features and optimization goals of various hardware platforms. By combining these modes, we construct a diverse set of sequential state encoding methods tailored to different optimization objectives. The proposed approach is intended for practical use in FSM implementations not only in FPGAs but also in CPLDs and ASICs.

The proposed state encoding methods differ from existing methods in several key ways:

• They consider the internal relationships between FSM states, including both already encoded and not yet encoded states;
• They account for the number of input variables influencing the transitions to each state;
• They consider the architectural features of the electronic device in which the FSM is implemented.

2. Materials and Methods

2.1. Sequential Methods for FSM State Encoding

The core principle of the sequential state encoding methods involves selecting FSM states in a specific order and assigning a unique code to each state. We put forward the following hypotheses to guide our research.

Hypothesis 1.

The outcome of FSM state encoding is influenced by the sequence in which codes are allocated to the states.

Hypothesis 2.

States that are most interconnected with already encoded states should be encoded first.

Let S = {s₀, …, s_M−1} represent the set of FSM states, and K = {k₀, …, k_Q−1} represent the set of all available codes, where M is the number of FSM states and Q is the number of available codes, with s₀ being the FSM’s start state. Let $Q=2^R$, where $R=\lceil {log}_{2}M\rceil$, and let ⌈A⌉ denote the smallest integer greater than or equal to A.

Sequential FSM state encoding can be represented by the following algorithm.

Algorithm 1 begins by assigning the zero code k₀ to the initial state s₀ and updates the sets of states (S) and codes (K) by removing s₀ and k₀, respectively. The main encoding process is carried out in a while loop, which continues until all states have been encoded. Within the loop, the next state s_i is selected from S according to a specified state selection mode. Then, using Algorithm 2, the appropriate code k_j is assigned to s_i. After assigning the code, both s_i and k_j are removed from their respective sets.

Algorithm 1. State encoding procedure.

1. Assign s0 <= k0 (zero code k0 to the start state s0);  2. Update S := S \ { s0 }, K := K \ {k0}.  3. While (S ≠ Ø) do  4.   Select the state si from S according to the specified state selection mode.  5.   Select the code kj from K to assign to si using Algorithm 2.  6.   Assign si <= kj, (code kj to state si).   Update S := S \ { si }, K := K \ {kj}.  7. end while.

Algorithm 2. Code selection procedure.

1. Set min_cost := 100,000.  2. For (each kt in K) do  3.   Perform a trial assignment of kt to si:si <= kt.  4.   Compute cost(kt) for the FSM area resulting from assigning kt to si.  5.   if (cost(kt) < min_cost) then min_cost := cost(kt); kj := kt; end if.  6.   Unassign kt from si:si => kt.  7. end for.  8. return (kj).

The key steps in Algorithm 1 are selecting the state s_i for encoding (step 3) and finding the code k_j that is optimal for assignment to the state s_i (step 4). When choosing k_j, it is crucial to calculate the increase in FSM area resulting from this assignment.

2.2. State Selection for Encoding

Let A(s_i) be the set of states where transitions from s_i end, B(s_i) be the set of states with transitions ending in s_i, and t(s_i,s_j) be the transition from the state s_i to the state s_j (s_i, s_j ∈ S). The set of transitions P(s_i) from the state s_i is defined by:

$$P\left(s_i\right)=\left\{t\left(s_i,s_j\right) | s_j\in A\left(s_i\right)\right\}.$$

(1)

The set C(s_i) of transitions to the state s_i is defined by:

$$C\left(s_i\right)=\left\{t\left(s_j,s_i\right) | s_j\in B\left(s_i\right)\right\}.$$

(2)

Let ES be the set of already encoded states. Then, the set of transitions P_ES(s_i) from s_i to states in ES is:

$$P_{ES}\left(s_i\right)=\left\{t\left(s_i,s_j\right) | s_j\in ES\right\},$$

(3)

and the set of transitions C_ES(s_i) from states in ES to s_i is:

$$C_{ES}\left(s_i\right)=\left\{t\left(s_i,s_j\right) | s_j\in ES\right\}.$$

(4)

Let X(s_j,s_i) be the set of FSM input variables that initiate the transition t(s_j,s_i). Then, the set X(s_i) of input variables influencing transitions to the state is defined as the union of all such input variables across all states s_j that transition to s_i. Formally, this can be expressed as:

$$X\left(s_i\right)=\bigcup _{s_j\in B\left(s_i\right)}X\left(s_j,s_i\right).$$

(5)

We introduce the following modes, which determine the strategy for selecting the next state s_i for encoding:

• max_P: select the state s_i with the maximum number of outgoing transitions $\left|P\left(s_i\right)\right|$(Figure 1a);
• max_C: select the state s_i with the maximum number of incoming transitions $\left|C\left(s_i\right)\right|$ (Figure 1b);
• P: select the state s_i from which the maximum number of transitions $\left|P_{ES}\left(s_i\right)\right|$ lead to already encoded states (Figure 1c);
• C: select the state s_i in which the maximum number of transitions $\left|C_{ES}\left(s_i\right)\right|$ originate from already encoded states (Figure 1d);
• P_C: select the state s_i with the maximum number of connections to already encoded states $\left|P_{ES}\left(s_i\right)\right|+\left|C_{ES}\left(s_i\right)\right|$ (Figure 1e);
• max_X: select the state s_i whose transitions are influenced by the highest number of input variables $\left|X\left(s_i\right)\right|$ (Figure 1f).

The modes P, C, and P_C take into account the relationship of the selected state s_i with the already encoded states, whereas the modes max_C, max_P, and max_X are independent of the order in which states are encoded. This distinction allows for flexible encoding strategies that can adapt to different optimization goals.

2.3. Code Selection for Encoding

Algorithm 2 is responsible for selecting the most suitable code k_j for a given state s_i. The algorithm starts by initializing the minimum cost to a very high value. It then iterates through each code k_t in the set K. For each code, a trial assignment is made to s_i and the resulting cost in terms of FSM area is computed. If the computed cost is lower than the current minimum cost, the minimum cost is updated, and k_j is set to k_t. After evaluating all codes, the algorithm returns the code k_j that resulted in the lowest cost.

In Algorithm 2, step 4 is crucial as it calculates the FSM area when k_t is assigned to s_i. It has been experimentally found that FSM state encoding primarily affects the area of transition functions, not output functions. Therefore, in step 4 of Algorithm 2, the area is calculated only for FSM transition functions.

2.4. Calculating FSM Area

Step 4 of Algorithm 2 suggests different area calculation modes for transition functions: CPLD, FPGA, ASIC, diff_w, and max_w. For example, in LUT-based FPGAs, the area of a transition function d_r is calculated as:

$$C_{FPGA}(d_r)=\left\{\begin{array}{c} 1, \mathrm{w}\mathrm{h}\mathrm{e}\mathrm{n} q\le n\\ ⌈\frac{q-n}{n-1}⌉+1, \mathrm{w}\mathrm{h}\mathrm{e}\mathrm{n} q>n\end{array}\right. ,$$

(6)

where q is the rank (number of arguments) of d_r, and n is the number of LUT inputs.

When implemented in CPLDs, the area C_CPLD(d_r) of the transition function d_r is equal to the number of product terms in the Sum-of-Products (SOP) representation of d_r:

$$C_{CPLD}\left(d_r\right)=H\left(d_r\right),$$

(7)

where H(d_r) is the number of product terms in the SOP of the function d_r.

When the FSM is implemented in an ASIC, the area C_ASIC(d_r) of the function d_r is determined by the number of literals in the SOP of d_r:

$$C_{ASIC}\left(d_r\right)=\sum _{i=1}^{H\left(d_r\right)}\left(X_i\left(d_r\right)+R_i\right)+H\left(d_r\right),$$

(8)

where X_i(d_r) is the number of input variables in the i-th product term in the SOP of the function d_r, and R_i is the number of feedback variables in the i-th product term.

The total area of the FSM implemented in an FPGA is defined as:

$$C_{FSM}=\sum _{r=1}^R{C}_{FPGA}\left(d_r\right).$$

(9)

It is important to note that the actual area occupied by a function is influenced by various factors such as the techniques and algorithms employed in the design tool. These include methods for logical synthesis, the optimization of both logical and physical synthesis, mapping the design logic to the physical structure of the electronic component, and ensuring compliance with time constraints during the design process. Consequently, the area estimated using Equations (6) to (9) may frequently diverge from the actual area occupied by the implemented FSM.

2.5. Other Code Selection Modes

Two additional modes are proposed apart from the considered area estimators tailored to the implementation of FSMs on specific types of electronic components: diff_w and max_w. In the diff_w mode, the objective is to minimize the difference in weights, W(d_r), of transition functions (Figure 2a), while in the max_w mode, the aim is to minimize the maximum weight, W(d_r), of transition functions (Figure 2b). Here, the weight, W(d_r), of each function d_r corresponds to the number of product terms in the SOP representation of that function. The diff_w mode aims to balance the cost of realizing all transition functions, thereby reducing the disparity between the most complex and simplest functions. On the other hand, the max_w mode seeks to minimize the area occupied by the most complex function, thereby enhancing FSM performance.

The following hypotheses are suggested for further investigation and validation, aiming to provide insights into the effectiveness and applicability of the proposed methods.

Hypothesis 3.

The diff_w mode contributes to minimizing the area of FSM.

Hypothesis 4.

The max_w mode contributes to enhancing FSM performance.

2.6. Constructing Sequential State Encoding Methods

Drawing upon Algorithms 1 and 2, along with the array of state selection modes (totaling 6) and code selection modes (totaling 5), a total of 30 (6 × 5) distinct methods for sequential FSM state encoding can be devised (Figure 3).

The state selection modes (P, C, P_C, max_C, max_P, and max_X) enable the consideration of intricate relationships among FSM states. Meanwhile, the code selection modes (FPGA, CPLD, and ASIC) incorporate the architectural features of electronic devices, as well as optimization objectives such as area (mode diff_w) or performance (mode max_w) minimization.

The methods resulting from this combination will be labeled using a single term, connecting the state selection mode and the area calculation mode with an underscore. For instance, in the P_FPGA method, state selection for encoding follows the P mode, while the cost of transition function implementation adheres to the FPGA mode.

3. Results

A study of sequential techniques for encoding FSM states was conducted using benchmarks from the Microelectronics Center of North Carolina (MCNC) [28], with FSM implementation on the Cyclone 10 LP FPGA family utilizing the Quartus design tool version 23.1. Initial experimental investigations revealed that methods constructed using the max_P mode did not yield satisfactory solutions; hence, they will not be further explored.

The MCNC benchmarks are described in the KISS2 format [22,28], a standardized textual representation that is easily parsed by software tools. This format offers a clear and concise way to represent FSMs, consisting of a header section and detailed transition descriptions. The header section provides essential information about the FSM, including the number of inputs, outputs, states, and transitions. Following the header, the KISS2 format outlines the state transitions in a structured manner. Each transition is described on a new line, specifying the input combination, current state, next state, and output combination.

Table 1. FSM area using sequential methods of state encoding.

SS_mode	P	P	P	P	C	C	C	C	P_C	P_C	P_C	P_C	max_C	max_C	max_C	max_C	max_X	Ls	Lmin	Ls/Lmin
CS_mode	FPGA	CPLD	diff_w	max_w	FPGA	CPLD	diff_w	max_w	FPGA	CPLD	diff_w	max_w	FPGA	CPLD	diff_w	max_w	FPGA
bbara	31	31	33	24	30	27	37	29	31	22	36	28	26	23	29	30	28	24	22	1.091
bbsse	58	60	65	62	58	64	62	57	61	62	65	55	61	64	57	62	68	60	55	1.091
beecount	16	22	19	22	16	22	19	22	16	22	19	22	17	16	16	16	16	16	16	1
dk14	51	41	40	43	37	44	46	43	47	42	56	43	41	45	42	42	45	36	36	1
dk16	90	82	120	87	80	88	88	88	87	85	93	104	83	100	87	86	100	92	80	1.15
dk512	22	16	15	16	16	18	15	15	15	15	17	18	14	15	17	17	15	15	14	1.071
ex2	67	75	71	76	58	72	74	67	74	61	81	71	56	62	62	64	62	35	35	1
ex3	26	28	32	29	27	23	30	26	23	23	34	28	28	23	23	26	23	22	22	1
ex5	20	24	24	26	21	21	27	20	18	19	22	23	22	23	23	22	23	21	18	1.167
ex7	25	34	27	33	22	28	33	31	20	24	41	26	20	25	25	27	25	18	18	1
lion9	11	15	15	18	11	15	15	18	11	15	15	18	11	15	18	18	15	19	11	1.727
pma	161	159	154	157	161	166	167	172	163	159	152	152	181	167	139	151	173	141	139	1.014
s1	156	179	183	175	149	150	180	152	190	148	183	149	149	148	153	148	147	150	147	1.02
s208	69	73	75	71	57	73	61	57	73	69	72	72	64	64	74	49	64	35	35	1
s27	19	15	19	14	9	22	16	21	9	22	16	21	20	11	12	12	11	16	9	1.778
s298	1024	1022	1063	969	969	965	1074	1000	938	958	1073	995	965	950	973	1008	943	1006	938	1.072
s386	58	60	55	53	59	56	59	57	57	50	53	53	58	56	57	55	58	26	26	1
s420	39	46	39	29	28	39	31	19	39	40	34	34	33	38	46	31	38	37	19	1.947
s820	144	133	141	130	132	125	138	126	127	127	147	134	127	127	124	132	134	138	124	1.113
shiftreg	2	4	3	4	4	4	4	4	4	2	4	2	2	4	4	4	4	4	2	2
sse	58	60	65	62	58	64	62	57	61	62	65	55	61	64	57	62	68	60	55	1.091
styr	182	184	193	186	179	194	188	190	186	187	187	189	179	185	177	190	184	213	177	1.203
train11	28	28	29	27	28	25	26	31	28	25	26	31	28	25	31	31	25	25	25	1
Best	3				4	1		1	5	3		3	3	2	4	1	3	8
Unique					1			1	1	1		2	1		3		1	6
Avg																				1.197
Max																				2

presents the basic parameters of the FSM test examples sourced from the MCNC benchmark dataset which were utilized in our research.

This research involved the development a specialized application called sequential_state_encoding, which is part of the ZUBR university package for digital device design [29]. This application was engineered to encode the FSM states based on various state and code selection modes. The application accepts an FSM description as input in the form of a text file in the KISS2 format, allowing users to select from different state and code selection modes tailored to specific optimization goals and hardware architectures.

The state encoding process within the application involves several selection modes, which determine the order in which states are encoded:

• In max_P mode, the state with the highest number of outgoing transitions is selected;
• In max_C mode, the state with the highest number of incoming transitions is selected;
• In P mode, the state from which the maximum number of transitions leading to already encoded states is chosen;
• In C mode, the state with the maximum number of transitions starting from already encoded states is selected;
• In P_C mode, the state with the maximum number of links to already encoded states is chosen;
• In max_X mode, the state affected by the highest number of input variables in its transitions is selected.

Additionally, the code selection modes were designed to optimize the FSM for different hardware architectures (FPGA, CPLD, or ASIC) where the FSM is implemented. This is reflected in the computation of the area of the FSM transition functions:

• In FPGA mode, the area is computed using Equation (9);
• In CPLD mode, the area is determined using Equation (7);
• In ASIC mode, the area is calculated using Equation (8).

Furthermore, the max_w code selection mode aims to minimize the maximum weight of the transition functions, whereas the diff_w mode seeks to minimize the disparity between the maximum and minimum weights of these functions. Consequently, while the max_w mode focuses on enhancing the performance of the FSM, the diff_w mode strives to optimize both the performance and the area of the FSM.

For each FSM benchmark, the application sequentially selected states and assigned appropriate codes based on the chosen modes, generating various encoding configurations. The application produces a KISS2 file containing state encoding, which is then processed using a ZUBR package converter. This converter translates the state-encoded KISS2 file into an FSM description in a selected Hardware Description Language (HDL). The ZUBR package converters facilitate the conversion of KISS2 files into Verilog, SystemVerilog, or VHDL, and allow for the selection of different FSM description styles [21]. In Appendix A, we include a sample Verilog description of the FSM for the shiftreg test example, generated using the P_C_max_w state encoding mode.

The FSM synthesis is continued using Quartus software version 23.1, which utilizes the Verilog description generated previously. This Verilog file is then synthesized using Quartus with the User Encoded mode selected to ensure that the state encoding adheres to the specified Verilog code. During the synthesis process, Quartus Prime compiles the Verilog code, optimizes the logic, and maps it onto the FPGA architecture. The software generates detailed reports covering various aspects of the synthesized design, including area utilization and performance metrics. The area utilization report indicates the number of logic elements, registers, and other FPGA resources used by the FSM implementation, providing insights into resource efficiency. The timing analysis report includes the maximum operating frequency of the synthesized FSM, highlighting the performance capabilities of the design.

This research involved comparing the synthesis results obtained using the custom state encoding application with those achieved using the built-in Sequential encoding mode offered by Quartus. The comparison focused on key parameters, highlighting the differences in area and performance, demonstrating the effectiveness of the proposed methods in optimizing FSM implementations.

The experimental results are summarized in Table 1 and

Table 2. FSM performance using sequential methods of state encoding.

SS_mode	P	P	P	P	C	C	C	C	P_C	P_C	P_C	P_C	max_C	max_C	max_C	max_C	max_X	Fs	Fmax	Fmax/Fs
CS_mode	FPGA	CPLD	diff_w	max_w	FPGA	CPLD	diff_w	max_w	FPGA	CPLD	diff_w	max_w	FPGA	CPLD	diff_w	max_w	FPGA
bbara	266	292	226	350	262	396	262	366	281	313	228	239	296	339	282	325	235	293	396	1.352
bbsse	215	184	199	217	221	186	185	195	182	168	187	208	184	213	236	218	190	212	236	1.113
beecount	326	273	318	273	326	273	318	273	326	273	318	273	346	344	344	344	344	317	346	1.091
dk14	251	222	232	249	217	261	248	268	246	220	212	278	225	235	262	262	235	249	278	1.116
dk16	179	196	162	212	197	191	177	202	188	192	197	164	195	194	202	204	194	201	212	1.055
dk512	201	314	324	337	321	313	328	347	320	350	282	369	325	339	330	310	339	329	369	1.122
ex2	160	183	169	190	206	209	172	177	179	184	172	181	172	215	208	164	215	152	215	1.414
ex3	269	250	165	172	199	181	199	191	226	253	191	185	159	212	179	305	212	200	305	1.525
ex5	310	244	280	193	214	242	228	282	256	300	244	303	232	220	323	209	220	249	323	1.297
ex7	260	210	288	163	236	212	202	238	259	201	188	242	275	252	221	208	252	248	288	1.161
lion9	389	467	428	373	389	467	428	373	389	467	428	373	389	467	373	373	467	294	467	1.588
pma	189	168	147	150	173	131	155	162	163	170	247	276	151	157	168	165	157	163	276	1.693
s1	154	153	149	156	143	148	151	156	139	163	152	148	164	163	150	176	165	161	176	1.093
s208	222	218	169	172	253	213	191	254	219	200	191	213	230	238	222	259	238	253	259	1.024
s27	227	312	245	273	389	275	276	247	389	275	276	247	257	301	324	324	301	363	389	1.072
s298	109	105	111	109	105	111	104	109	110	108	107	110	108	104	107	110	109	113	113	1
s386	196	189	192	211	215	205	217	221	185	203	226	248	197	223	226	212	167	185	248	1.341
s420	258	226	221	242	368	294	264	373	243	225	287	216	334	324	283	274	324	280	373	1.332
s820	170	167	160	174	166	184	141	161	156	160	159	164	178	166	162	159	156	165	184	1.115
shiftreg	847	935	611	935	924	926	938	926	926	847	943	847	847	935	935	935	935	935	943	1.009
sse	215	184	199	217	221	186	185	195	182	168	187	208	184	213	236	218	190	212	236	1.113
styr	151	153	158	157	141	137	142	138	159	170	164	158	152	158	160	152	147	160	170	1.063
train11	212	206	179	287	184	216	260	241	184	216	260	241	184	216	241	241	216	244	287	1.176
Best		1	1	2	1	3		1	1	2	1	4	1	2	3	3	1	1
Unique		1	1	2		2		1		1	1	4	1	1	3	3		1
Avg																				1.212
Max																				1.693

. Both tables include columns corresponding to different encoding modes, determined by combinations of SS_mode, which refers to the state selection mode (P, C, P_C, max_C, or max_X), and CS_mode, indicating the code selection mode (FPGA, CPLD, diff_w, max_w). The results in both tables summarize the following rows: Best, which denotes the number of best solutions; Unique, which counts the number of unique best solutions not achieved by other encoding methods; Avg, representing the mean value of the parameter; and Max, the maximum value of the parameter.

Table 1 is dedicated to evaluating area efficiency. It includes metrics such as Ls, which represents the area value (number of FPGA logic elements) for Quartus Sequential mode encoding, and Lmin, the minimum area value for the given example. The ratio Ls/Lmin indicates the area efficiency compared to the Sequential mode. Table 2 focuses on performance metrics. The specific columns in Table 2 are Fs, which represents the performance value (maximum operating frequency in megahertz) using the Sequential mode of Quartus, and Fmax, the maximum performance value for the example. The ratio Fmax/Fs indicates the performance improvement compared to the Sequential mode.

The Sequential mode is the state encoding method provided by Quartus. In this mode, the FSM states are sequentially encoded using binary codes of minimum length. This mode serves as a baseline for comparing the results obtained by the proposed state encoding methods. It should be noted that the max_P_FPGA method yielded unsatisfactory results and has therefore been omitted from the experimental findings.

For the FSM examples considered, the results were identical for the CPLD and ASIC modes. Therefore, Table 1 and Table 2 solely showcase the outcomes for the FPGA and CPLD modes. Furthermore, the state selection mode max_X was exclusively explored in conjunction with the FPGA code selection mode.

4. Discussion

The results of the study indicate the effectiveness of the proposed sequential state encoding methods in optimizing FSM implementations. Through a systematic evaluation of each state and code selection mode across various FSM benchmarks, the research demonstrated that tailored encoding strategies could lead to notable improvements. Comparing the synthesis results with those obtained using Quartus’s built-in Sequential encoding mode, this study highlighted the benefits of the new encoding methods.

An analysis of Table 1 and Table 2 reveals that, compared to the Sequential mode, the proposed FSM state encoding methods significantly improve both area and performance. In Table 1 and Table 2, the columns provide detailed insights into the metrics used for evaluation. Specifically, the column Ls represents the area value, measured as the number of FPGA logic elements used when applying Quartus’s Sequential mode encoding. The column Fs indicates the performance value, measured as the maximum operating frequency in megahertz (MHz), achieved with the Sequential mode of Quartus. Meanwhile, Lmin denotes the minimum area value, representing the lowest number of logic elements used among all tested methods for a given FSM example, while Fmax signifies the maximum performance value, representing the highest operating frequency achieved among all tested methods.

The ratios Ls/Lmin and Fmax/Fs are crucial for assessing the efficiency of the proposed methods. These ratios compare the outcomes of the proposed FSM state encoding methods against the Sequential mode of Quartus. A higher Ls/Lmin ratio suggests a greater reduction in area utilization, highlighting the effectiveness of the proposed encoding methods in minimizing FPGA resources. Similarly, a higher Fmax/Fs ratio indicates an improvement in performance, showcasing how the proposed methods enhance the maximum achievable operating frequency compared to the Sequential mode.

On average, these methods reduce the area by 19.7%, and in some cases, such as the shiftreg example, the reduction can be as much as twofold. Additionally, the performance of FSMs is enhanced by an average of 21.2%, with certain examples like pma experiencing performance increases of up to 69.3%.

In Table 1 and Table 2, the best solutions are highlighted in bold. It is important to note that the best solution can be achieved using multiple encoding methods. For some methods, the best solution is unique in comparison to other methods, meaning it cannot be obtained using alternative encoding methods.

Figure 4 presents graphs depicting the state selection modes based on the number of best and unique solutions in terms of both area and performance. These graphs illustrate the effectiveness of different state selection modes in achieving optimal results.

As shown in Figure 4a, the P_C mode is the most effective state selection mode in terms of area, with the max_C mode following closely. In contrast, Figure 4b indicates that the max_C mode excels in performance, with P_C as the second-best option. Therefore, the optimal solutions for both area and performance are most likely to be found using the P_C and max_C modes.

Figure 5 presents graphs illustrating the effectiveness of various code selection modes based on the number of best and unique solutions in terms of area and performance.

Figure 5a indicates that the FPGA mode is the most effective code selection mode for minimizing area, followed by the CPLD mode. However, Figure 5b shows that the FPGA mode is the least effective for optimizing performance. As expected, the max_w mode excels in performance optimization, with the CPLD mode being the second-best, similarly to its performance in area optimization.

Therefore, to optimize area, the FPGA and CPLD code selection modes are recommended; for optimizing performance, the max_w and CPLD modes should be used. When both area and performance need optimization, the CPLD mode is the best choice.

Figure 6 illustrates the number of best and unique solutions in terms of FSM area achieved by the sequential encoding methods developed.

As shown in Figure 6, the methods are ranked in the following order in terms of area efficiency:

P_C_FPGA;

max_C_diff_w;

C_FPGA;

P_C_max_w;

max_C_FPGA;

max_X_FPGA;

P_FPGA;

max_C_CPLD;

C_max_w;

C_CPLD;

max_C_max_w.

The ranking was determined by the number of Best results each method achieved in terms of area efficiency. Methods were ranked according to how often they produced the most optimal area outcomes. When multiple methods had the same number of Best results, the Unique value was used to differentiate them. This ranking effectively highlights the methods that are most successful in minimizing FPGA resource utilization, providing valuable insights into the best techniques for area optimization.

Notably, among the best area methods, the state selection modes P_C and max_C are prominent, but the C, max_X, and P modes also appear. Similarly, besides the FPGA and CPLD modes for code selection, the diff_w and max_w modes are also present.

Therefore, to identify the best area solutions, it is advisable to consider not only the recommended P_C, max_C, FPGA, and CPLD modes but also the state selection modes C, max_X, and P, along with the code selection modes diff_w and max_w.

Figure 7 illustrates the number of best and unique solutions in terms of FSM performance achieved by the developed sequential encoding methods.

Based on Figure 7, the methods are ranked in terms of performance efficiency as follows:

P_C_max;

max_C_diff_w;

max_C_max_w;

C_CPLD;

P_max_w;

P_C_CPLD;

max_C_CPLD;

P_CPLD;

P_diff_w;

C_max_w;

P_C_diff_w;

max_C_FPGA;

C_FPGA;

P_C_FPGA;

max_X_FPGA.

The performance ranking was established by counting how often each method achieved the Best results in terms of maximum operating frequency. Methods were ranked according to the number of top performance results they produced. In cases where methods had the same number of Best results, the Unique value was used to determine the ranking. This ranking highlights which methods are most effective in maximizing the FSM’s operating frequency, thus offering useful guidance for performance optimization.

It is important to note that among the top-performing methods, in terms of performance, the state selection modes P_C and max_C are not the only ones present. The C, P, and max_X modes are also found to be among the best. Similarly, for code selection modes, besides max_w and CPLD, the diff_w and FPGA modes also appear frequently.

Therefore, to achieve the best performance, one should consider not only the recommended P_C, max_C, max_w, and CPLD modes but also the C, P, and max_X state selection modes along with the diff_w and FPGA code selection modes.

Although the diff_w mode is not consistently among the top code selection modes for either area or performance, it is frequently found in state encoding methods that yield the best solutions.

5. Conclusions

This paper presented a heuristic approach for encoding states of FSMs by sequentially selecting states for encoding and assigning the most appropriate codes. The approach introduces several state selection modes (P, C, P_C, max_C, and max_X) and code selection modes (FPGA, CPLD, diff_w, and max_w). The state selection modes account for the internal relationships between the FSM states and input variables, while the code selection modes consider the architectural features of the electronic component (FPGA, CPLD, or ASIC) in which the FSM is implemented. Various sequential FSM state encoding methods were developed by combining state and code selection modes. The efficacy of these methods was evaluated using MCNC benchmarks with FSM implementations on FPGA.

This study put forward the following hypotheses: (1) the results of FSM state encoding depend on the order in which the codes are assigned to the states; (2) FSM states that are most linked to already encoded states should be encoded first; (3) the mode diff_w contributes to minimizing the implementation cost of FSMs; and (4) the mode max_w contributes to increasing the performance of FSMs. Hypotheses 1 and 4 are fully supported by the findings. Hypothesis 2 is only partially substantiated, as the mode max_C, which considers states not linked with already encoded states, also provides satisfactory outcomes. Although Hypothesis 3 is not entirely confirmed, it is worth noting that the diff_w mode frequently appears in state coding methods that deliver optimal solutions.

The experimental results demonstrated that the proposed FSM state encoding methods reduced the area by an average of 19.7%, with some examples showing a twofold reduction. Performance improvements averaged 21.2%, with some cases showing a 69.3% increase.

Future research in FSM state encoding will emphasize the development of parallel and iterative algorithms, alongside exploration into varying the number of bits in state codes. Additionally, there is potential in investigating the integration of output function realization with state encoding, marking a promising direction for further study.