Application of Surge Arrester in Limiting Voltage Stress at Direct Current Breaker

Abstract

Hybrid DC circuit breakers combine mechanical switches with a redirecting current path, typically controlled by power electronic devices, to prevent arcing during switch contact separation. The authors’ past work includes a bipolar hybrid DC circuit breaker that effectively redirects the fault current and returns it to the source. This reduces arcing between the mechanical breaker’s contacts and prevents large voltage overshoots across them. However, the breaker’s performance declines as the upstream line inductance increases, causing overvoltage. This work introduces a modification to the originally proposed hybrid DC breaker to make it suitable to use anywhere along DC grid lines. By using a switch-controlled surge arrester in parallel with the DC breaker, part of the arc energy is dissipated in the surge arrester, preventing an overvoltage across the mechanical switches. Based on the experimental results, the proposed method can effectively interrupt the fault current with minimal arcing and reduce the voltage stress across the mechanical switches. To address practical fault currents, tests at high fault currents (900 A) and voltage levels (500 V) are conducted and compared with simulation models and analytical studies. Furthermore, the application of the breaker for the protection of DC distribution grids is illustrated through simulations, and the procedure for designing the breaker components is explained.

1. Introduction

With the advances in renewable energy systems and DC mechanisms, the DC grid has attracted much attention. The availability of DC generation in low- and medium-voltage levels has led to the expansion of DC grids. DC grids possess many advantages such as the absence of reactive power, lower path impedance, compatibility with renewable sources, etc. However, fault clearance is one significant barrier in these systems due to the lack of a current zero-crossing and higher fault currents due to lower path impedance.

High-voltage DC (HVDC) systems have been utilized since the 1970s [1,2,3,4]. The advent of low-loss semiconductor technologies, rectifiers, inverters, and DC–DC converters made the integration of multi-terminal direct current (MTDC) systems possible, facilitating energy production using new generation units, such as wind farms, solar panels, and tidal-wave generators at different voltage levels. Furthermore, deploying direct current lines in AC power grids enhances power flow control, system voltage and frequency stability and has economic benefits [4,5]. Managing bidirectional power flow is achieved via DC microgrids at low and medium voltage levels. In addition, managing various DC distributed power sources and loads is detailed in references [6,7,8,9,10].

Despite the many advantages of DC grids, fault-current interruption and the safety of DC grids is still an ongoing challenge and a subject of research. DC grids have extremely low impedance compared to AC networks, leading to considerable short-circuit currents [4,5,6]. Hence, DC breakers must break the fault current at a much faster speed [7], ideally in the range of a few milliseconds [2].

Second, unlike in AC networks, there is no natural zero-crossing of the current in DC circuits. Therefore, one way to disrupt the fault current is to artificially generate a current zero-crossing via an oscillatory circuit in the DCCBs so that the current can be interrupted with a mechanical switch [5]. Currently, the available DC breakers fall into three categories, namely mechanical DCCBs, solid-state DCCBs, and hybrid DCCBs. The mechanical DCCBs have negligible series resistance due to their metal contacts and are ideal for steady-state high-current applications; however, current interruption causes significant arcing and heat generation in this type of DCCB. Solid-state DCCBs present rapid and arc-free current interruption; however, a significant amount of energy loss occurs in the steady-state operation due to the higher series path resistance. Hybrid DCCBs combine solid-state and mechanical switches, where mechanical contacts conduct the current in a steady state. Upon current interruption, the current is rerouted through a parallel solid-state switch until separation occurs between the mechanical contacts. Subsequently, the solid-state switch interrupts the current with no arc. Despite this advantage, most hybrid DCCBs involve a wait time for the mechanical contacts to separate, which delays the fault interruption, leading to significant fault-current generation unless complex rerouting circuits are used (including inductors, transformers, and/or high-current IGBTs).

Table 1. Comparison of different DCCB models [11].

	Solid-State Circuit Breaker	Mechanical Circuit Breaker	Hybrid Circuit Breaker
Response time	Very fast (A few microseconds)	Slow (Tens of milliseconds)	Fast (A few milliseconds)
Cost	High	Low	Very high
Size	Compact	Large	Large
Loss	Very high	Very low	Very low

presents various types of DCCBs.

In [11], a bipolar DC breaker was introduced that generates a current zero-crossing with a simple structure and rapid fault-interruption capability while restricting the switching voltage to that of the source voltage. The proposed topology [11] employs a bipolar configuration that uses both DC line polarities and can reroute the fault current back to the source using two mechanical switches and two diodes. In addition, the switches are equipped with bypassing capacitors to provide a zero-voltage switching (ZVS), as shown in Figure 1b (excluding the surge arrester). This combination causes a voltage rise across the mechanical switches up to the source voltage level. In addition, via rerouting the current through the diodes, a reverse supply voltage will help damp the fault current and return it to the source. Despite the simple and control-free structure (with only diodes and capacitors), the proposed breaker is only effective in reducing the arc across the mechanical switches when it is placed close to the source, where the upstream path impedance is negligible. When the proposed DCCB is used in the DC power line, the upstream-line parasitic inductance prevents the backflow of the fault current to the source, causing a voltage rise at the DC breaker’s input terminals and a delay in the operation of the redirecting diodes.

Surge protection devices (SPDs) [12,13,14,15,16,17], also known as surge arresters, are widely used in power systems to mitigate and absorb fault energies caused by transients, such as switching, lightning, and temporary overvoltage. Surge arresters are typically comprised of cylindrical variable resistors with various diameters and heights that are made of composites with non-linear voltage–current characteristics. These composites are made in grains with smaller interior resistivity than exterior resistivity. The nonlinear voltage–current characteristic is due to the phenomenon occurring mainly on the boundary of the grains [15]. Under low voltage across the surge arrester, voltage–current characteristics follow Ohm’s law. As the voltage goes beyond the surge arrester’s limit, the voltage–current characteristic becomes highly non-linear and the current increases sharply. Various reports [18,19] highlight the application of the surge arresters in mitigating high voltages (500 kV), particularly in transient arcs over the insulators. The authors of [20] introduced a novel zonal fault-detection scheme for DC wind farms that leverages the strategic disposition of surge arresters in multipurpose grounding systems. Surge arresters have been used in mechanical and hybrid DCCBs to absorb the fault energy after it is redirected to bypassing circuits that comprise inductors or solid-state switches such as IGBTs or thyristors [21].

In this paper, a modification to the hybrid DCCB introduced in [11] is proposed, utilizing surge arresters, so that the breaker can be used anywhere along the DC power line and alleviate the shortcoming of the original hybrid DCCB proposed in [11]. In this work, the surge arrester plays two important roles, namely up-/downstream fault energy absorption and providing a reverse voltage for faster current decay in part of the fault disruption period. High-current hardware tests (900 A) are performed to address practical issues pertaining to high-current disruption under voltages under 500 V. The hybrid DCCB mathematical model is also discussed, and detailed simulation studies are performed.

For low-voltage applications, this paper proposes a modified bipolar hybrid DC breaker based on the authors’ previous work [11,22], which is applicable to high-voltage DC line/load inductances, by using surge arresters. The proposed DC breaker can potentially be used at higher voltage levels such as in medium-voltage applications. The following is the organization of the rest of the paper: Section 2 proposes the hybrid DCCB mechanism. Section 3 presents the mathematical model. Section 4 includes the experimental results. Section 5 presents the conclusion and perspectives for future research.

2. The Proposed Mechanism

The two-switch bipolar hybrid DC breaker introduced in [11], depicted in Figure 1a (excluding the surge arrester), uses capacitors to bypass the fault current and facilitate the opening of the mechanical switches minimizing the arc. The capacitors must have very small resistance and inductance for the scheme to operate. They undergo an overvoltage along with the connecting parallel mechanical switches. The use of the redirecting diodes [11] prevents the overvoltage while imposing a negative voltage on the path inductance and sends part of the fault current back to the supply. Consequently, an improved current zero-crossing time is achieved, and the arc energy is reduced when the proposed breaker is used close to the DC source. With the presence of parasitic path inductance upstream of the breaker, this mechanism is disturbed, causing an overvoltage at the terminals of the DC breaker during fault current disruption.

This paper presents a modification to the two-switch hybrid bipolar DC breaker [11], as shown in Figure 1. A surge arrester is added to the input terminals of the DC breaker, providing a return path for the fault current that flows in the upstream path inductance. This still causes a voltage rise at the breaker’s input terminals, but it is much smaller than the case without the surge arrester. The surge arrester, however, is directly exposed to the source voltage, leading to relatively high values of leakage current, even in the breaker’s open state. To resolve this problem, a normally open mechanical switch is placed in series with the surge arrester to prevent the leakage current. The switch closes upon the opening of the circuit breaker to increase the reliability and lifetime of the surge arrester. The operation of the modified breaker is explained next.

As an overcurrent fault is detected, the mechanical switches start to separate contacts, followed by the generation of an arc between the contacts. Subsequently, the fault current is rerouted to the parallel capacitors, causing the arc to disappear and the capacitor voltages to rise. The capacitors’ voltage rise imposes a high voltage on the surge-arrester terminals, dropping its path resistance and allowing the reverse downstream current to flow. Concurrently, the upstream inductance is subject to a negative voltage and a decaying current due to the raised surge-arrester terminal voltage. Also, the capacitors’ voltage rise turns on the diodes, causing the capacitor voltages to be clamped at the surge-arrester voltage. At this stage, the downstream fault current partially returns to the surge arrester in a decaying fashion that generates a zero-crossing and fault-current interruption. The modified DC breaker operation comprises seven stages, which are subsequently explained and are depicted in Figure 2 and Figure 3.

Stage 1: This is a pre-operation of the proposed mechanism, where the fault current is established but the breaker has not operated. Both the mechanical switches (SW1 and SW2) are conducting, and the surge arrester is in its blocking state (see Figure 1b).

Stage 2: In this stage, a trip signal is issued to both the switches; however, due to their internal mechanical properties, one mechanical switch operates first (ex., SW2). The fault current redirects to the parallel capacitor path flowing through SW1 and C2, raising the C2 voltage in an RLC circuit, and thus rapidly decays. The surge arrester is in block mode initially due to its low terminal voltage, and $I_{upstream}=I_{downstream}$, with $I_{downstream}$ being the downstream inductor current. The fault current raises the C2 voltage, causing the surge-arrester terminal voltage to rise until it reaches the conduction mode at the end of this stage (See Figure 3a).

Stage 3: Upon the surge arrester conducting, a further increase in the C2 voltage will turn on diode D1, clamping the SW2 voltage (and $V_{C2}$) at the surge-arrester voltage. As SW1 is still closed, the fault current flows through SW1 and D1 forming and RL circuit. At the end of this stage, SW1 starts to separate its contacts and the Stage 4 operation starts. The upstream current flows in the surge arrester in this stage (See Figure 3b).

Stage 4: In this stage, switch SW1 opens, and parallel capacitor C1 starts to re-route the fault current. As the contacts separate, the voltage across capacitor C1 increases. The current flows through C1 and D1, forming an RLC circuit. The current continues to flow and decay until the voltage across capacitor C1 exceeds the surge-arrester voltage, turning diode D2 on. If $I_{downstream}$ significantly drops in Stage 3, the C1 voltage may not reach the surge-arrester voltage and a current zero-crossing may occur here, meaning Stage 5 is skipped (See Figure 3c).

Stage 5: Here, the fault current ($I_{downstream}$) flows through diodes D2 and D1 back to the surge arrester, returning part of the fault energy to the source. The reverse DC voltage applied across the downstream inductance helps with its faster current decay. Theoretically, we have a zero-crossing of the fault current at the end of this stage and thus a low-cost AC breaker (Figure 1) can isolate the faulty line at this point (see Figure 3d).

Stage 6: A low-cost contactor can be used to isolate the breaker from source ($I_{downstream}=0$) at the end of Stage 5. Otherwise, the Stage 6 operation takes place. Here, the direction of the current reverses after crossing zero, and D1 and D2 turn off. Because of the stored energy in the capacitors, a small oscillating current flows through C1, the RL load/fault, C2, and the surge arrester, partially discharging the capacitors.

Stage 7: Due to the termination of the upstream fault current, low capacitor voltages, and downstream fault current at this stage, the surge arrester switches back to the blocking mode, transferring the oscillating current to the DC source and causing the fault current to disappear.

Current breaking takes place in Stages 2 through 5 (shown next). Due to the capacitor charging in these stages (Stages 2 and 4), the voltages across switches can reach very high values. In order to overcome the voltage overshoots, the redirecting diodes are utilized to limit the voltage rise to that of the breaker terminal voltage, which is the surge arrester (SPD)’s voltage. In the absence of the surge arrester, the capacitor (switch) voltages can be excessively high due to the upstream-inductor fault energy.

The protection voltage level of the surge arrester is set according to system needs. In the steady-state condition, the surge arrester is disconnected. In the case of a short-circuit fault, as the surge arrester and breaker contacts start to separate, both the upstream inductor and the breaker capacitors’ rising voltages impose a high voltage on the surge-arrester terminals, forcing it to enter the conductive mode, with a small resistance, as explained. Thus, unlike [11], for faults away from the source, the switching overvoltage is controlled using both the diodes and surge arrester, instead of only diodes.

3. Calculation of the Current Zero-Crossing Time

It is possible to calculate the total current-interruption time based on the time duration of each stage explained in the previous section. For simplicity, the surge-arrester voltage is considered constant upon switching to conduction mode.

3.1. Stage 2 ($t_1$ through $t_2$)

An RLC circuit is formed, comprising line inductance and resistance, C2, and the voltage source, as

$${\displaystyle \frac{d^2{I}_{d2}}{d{t}^2}}+{\displaystyle \frac{R}{L}}{\displaystyle \frac{d{I}_{d2}}{dt}}+{\displaystyle \frac{I_{d2}}{L{C}_2}}=0;I_{d2}=I_{u2}$$

(1)

where $I_{u2}$ and $I_{d2}$ are the upstream and downstream currents at this stage, respectively, and $L$ and $R$ are the total line inductance and resistance. In case of an underdamped response, ${\displaystyle \frac{R}{2L}}\le \sqrt{{\displaystyle \frac{1}{L{C}_2}}}$; i.e., $C_2\le {\displaystyle \frac{4L}{R^2}}$. Equation (1) yields $I_2\left(t_{21}\right)=k_1{e}^{-\alpha t_{21}}\mathrm{c}\mathrm{o}\mathrm{s}\left({\omega }_d{t}_{21}+\phi \right)$, where $\alpha ={\displaystyle \frac{R}{2L}}$, ${\omega }_d=\sqrt{{\omega }_0^2-{\alpha }^2}$, and ${\omega }_0=\sqrt{{\displaystyle \frac{1}{L{C}_2}}}$. By using the initial conditions $I_2\left(0\right)=I_{fault}$ and $V_{C2}\left(0\right)=0$, it is possible to calculate $\phi$ and $k_1$ as $\phi =-{tan}^{-1}({\displaystyle \frac{V_s-R{I}_{fault}}{L{\omega }_d{I}_{fault}}}+{\displaystyle \frac{\alpha }{{\omega }_d}})$ and $k_1={\displaystyle \frac{I_{fault}}{\mathrm{c}\mathrm{o}\mathrm{s}\left(\phi \right)}}$. $t_{21}$ is the time when $V_{C2}=V_{SAB}$, where $V_{SAB}$ is the surge-arrester blocking voltage.

3.2. Stage 3 ($t_2$ through $t_3$)

Capacitor C2 stops conducting current during this period, while switch SW1 still conducts current, even though it has been triggered, due to the operational delay. As shown in Figure 3b, the stored energy in the downstream inductor is now discharged in an RL circuit. From the figure, the KVL yields

$$I_{d3}{R}_d+L_d{\displaystyle \frac{d{I}_{d3}}{dt}}=0$$

(2)

where $I_{d3}$ is the downstream current in Stage 3, and $L_d$ and $R_d$ are the downstream inductance and resistance, respectively. Thus,

$$I_{d3}\left(t_{32}\right)=I_0{e}^{-{\displaystyle \frac{R_d}{L_d}}{t}_{32}}$$

(3)

where $I_0$ is equal to the final current of the last stage $I_0=I_{d2}\left(t_2\right)$. $t_{32}$ is the SW1 operational delay.

In addition, the upstream circuit is another RL circuit, comprising the supply voltage, the surge-arrester blocking voltage ($V_{SAB}$), $L_u$, $R_u$, and the upstream inductance and resistance, respectively. Thus,

$$I_{3u}{R}_u+L_u{\displaystyle \frac{d{I}_{3u}}{dt}}=V_S-V_{SAB}$$

(4)

where $V_S$ is the supply voltage. Therefore, the upstream current decays according to

$$I_{u3}\left(t_{32}\right)={\displaystyle \frac{V_S-V_{SAB}}{R_u}}\left(1-e^{-{\displaystyle \frac{R_u}{L_u}}{t}_{32}}\right)+I_0{e}^{-{\displaystyle \frac{R_u}{L_u}}{t}_{32}}$$

(5)

Note that the surge-arrester voltage $V_{SAB}$ is greater than that of the source, and thus the upstream current decays.

3.3. Stage 4 ($t_3$ through $t_4$)

Capacitor C1 is charging in this stage. Writing KVL gives,

$${\displaystyle \frac{d^2{I}_{d4}}{d{t}^2}}+{\displaystyle \frac{R_d}{L_d}}{\displaystyle \frac{d{I}_{d4}}{dt}}+{\displaystyle \frac{I_{d4}}{L_d{C}_1}}=0$$

(6)

Similar to (1), one can obtain $I_{d4}\left(t_{43}\right)=k_2\cos \left({\omega }_d{t}_{43}+\phi \right)e^{-\alpha t_{43}}$ where $\alpha ={\displaystyle \frac{R_d}{{2L}_d}}$, ${\omega }_d=\sqrt{{\omega }_0^2-{\alpha }^2}$, and ${\omega }_0=\sqrt{{\displaystyle \frac{1}{L_d{C}_1}}}$.

We use the initial conditions $I_{d3}\left(t_3\right)$ and $V_{C1}\left(0\right)=0$ to calculate $\phi$, with $k_2$ as $\phi =-{tan}^{-1}({\displaystyle \frac{-R}{L_d{\omega }_d}}+{\displaystyle \frac{\alpha }{{\omega }_d}})$ and $k_2={\displaystyle \frac{I_{d3}\left(t_3\right)}{\mathrm{c}\mathrm{o}\mathrm{s}\left(\phi \right)}}$. By the end of Stage 4, the voltage of the capacitor $V_{C1}\left(t_4\right)=V_{SAB}$, where $V_{SAB}$ is surge-arrester blocking (protection) voltage.

The upstream current continues to decline according to (3).

3.4. Stage 5 ($t_4$ through $t_5$)

At this point, capacitor C1 has been charged enough to turn D2, leading to an RL circuit comprising the surge arrester, the downstream RL branch, D1, and D2, as shown in Figure 3d. Due to ${-V}_{SAB}$ being applied to the downstream inductance, a linear current decay occurs here and downstream current $I_5$ may reverse, discharging the downstream fault energy (inductance stored energy) into the surge arrester. The result of applying KVL is

$$I_{d5}{R}_d+L_d{\displaystyle \frac{d{I}_{d5}}{dt}}={-V}_{SAB}$$

(7)

where $I_5$ is the current in Stage 5. Thus,

$$I_{d5}\left(t_{54}\right)={\displaystyle \frac{-V_{SAB}}{R_d}}\left(1-e^{-{\displaystyle \frac{R_d}{L_d}}{t}_{52}}\right)+I_0{e}^{-{\displaystyle \frac{R_d}{L_d}}{t}_{52}}$$

(8)

where $I_0=I_{d4}\left(t_5\right)$. $t_{54}$ is the time where $I_{d5}=0$.

The total zero-crossing time can be calculated by

$$t_{zc}=t_{21}+t_{32}+t_{43}+t_{54}$$

(9)

4. Components Selection

Capacitors are selected based on the maximum allowed rate of change of voltage across the breaker contacts ${\displaystyle \frac{d{V}_C}{dt}}<80\mathrm{V}/\mathsf{\mu }\mathrm{s}$ that is needed for the air breakers to prevent restrikes and is an appropriate speed for typical fast breakers [23]. The maximum fault current $I_{fault}=C{\displaystyle \frac{d{V}_C}{dt}}$ is used to calculate the capacitors with ${\displaystyle \frac{d{V}_C}{dt}}<80\mathrm{V}/\mathsf{\mu }\mathrm{s}$, i.e., $C>{\displaystyle \frac{I_{fault}}{80\times {10}^6}}$. For example, a 1000 A fault current requires $\mathrm{C}\ge 12.5\mathsf{\mu }\mathrm{F}$. Slower mechanical breakers require larger capacitors. Capacitors must tolerate transient overvoltage beyond the nominal source voltage.

$I^{2}t$ curves are used to select diodes due to the short duration of the fault current. Diodes can be rated slightly higher than the supply voltage as they experience $V_{SAB}$ in the proposed topology.

Surge arresters are selected based on their leakage current and voltage for the target fault current via the surge arrester’s V-I characteristic. For example, for a 500 V, 10 kA fault scenario, one must choose a surge arrester that is capable of conducting 10 kA at slightly above 500 V. Such a surge arrestor may conduct a significant amount of current under 500 V (normal condition) and thus is disconnected by a controlled switch in the proposed breaker (see Figure 1).

5. Experimental and Simulation Results

A 500 V, 1500 A power supply is built to validate the performance of the proposed breaker when used in a circuit with upstream and downstream inductors. A 500 V, 0.12 F capacitor bank provides a maximum 500 VDC and is charged via a rectifier from a 480 V three-phase source. After being fully charged, the three-phase power is disconnected and the stored energy in the capacitor bank is utilized for the generation of the fault current. A 2.27 mH, 0.21 $\mathsf{\Omega }$ and a 2.72 mH, 0.25 $\mathsf{\Omega }$ air-core inductor represents the upstream and downstream DC line inductances. The hybrid DC breaker uses two contacts of a 15 A, 480 Vac, 240 VDC three-phase circuit breaker with 20 kA breaking capacity.

Two 1000 V, 150 A diodes with a 1.5 kA, 8 ms non-repetitive peak current rating as well as two 500 V, 1100 μF bypassing capacitors are used as redirecting and bypassing elements. The selection of the capacitors is based on experimental observations, as the smaller capacitors suggested in Section 4 lead to significant arcing, especially in 500 V tests, since the selected three-phase breaker is not a fast mechanical switch. Based on the experiment fault voltage level, a 240 V, 12 kA, 20 mm disc surge arrester was selected for the 260 V experiment. For the 480 V experiment, two surge arresters were connected in series to provide the required protection voltage. The circuit of Figure 1b was then established. Upon connecting the capacitor bank to the faulty circuit, a fault current is established in the circuit. A trip command is externally sent to the breaker through its shunt trip signal shortly after and when the fault current is at maximum in the resultant circuit. As soon as the fault current is established, the waveforms are captured via an oscilloscope. Figure 4 illustrates the experimental test setup and measurement circuits diagram. The performance of the surge arrester in limiting voltage overshoots is evaluated. Tests are conducted under two different voltage levels, i.e., 280 V and 500 V (with some variations). The tests scenarios are explained next.

• Case 1: Conventional Mechanical Breaker

First, the conventional mechanical DC breaker is tested for fault-current disruption performance. Two contacts of the AC breaker are used in series (recommended by the manufacturer) with the upstream and downstream inductors as shown in Figure 5. Measurements are taken for the SW1 and SW2 voltages, the breaker terminal voltage (see Figure 5), and the fault current. The tests results are depicted in Figure 6 for test voltages of 280 V and 500 V. Note that the breaker terminal voltage that initially experienced the supply voltage under open-circuit conditions immediately drops to almost half of the supply voltage due to a voltage split between the upstream and downstream inductors, and it continues to drop slightly thereafter due to the RLC response. Upon switch-contact separation, the breaker’s input-terminal voltage rapidly increases (see Figure 6), this time to a lower voltage than the original voltage due to the capacitor bank’s partial discharge. A significant arc is observed between the switches’ contacts, which is also confirmed by the noisy current waveforms, as all the fault energy (energy stored in the inductors) is released there in the form of an arc (heat). The measured fault clearing time is approximately 7.7 ms and 17.7 ms for 280 V and 500 V tests, respectively. The prolonged arcing indicates that significant contact erosion occurs in this scenario.

• Case 2: Original Hybrid DCCB

The original hybrid DCCB [11] has a similar structure to that shown in Figure 1, except no surge arrester is used. The original topology is efficient only if placed close to the source, where the upstream inductance is negligible. Figure 7 depicts the current and voltage waveforms for faults under both 280 V and 500 V tests. As soon as the trip command is issued, SW1 and SW2 start to open; however, due to the inherent mechanical differences, SW2 operates faster, and the current is bypassed via C2 increasing $V_{C2}$, which in turn causes D1 to turn on and clamp $V_{C2}$ at the breaker input-terminal voltage level. Due to the upstream line inductance the terminal voltage rises excessively in the absence of any other current path. Figure 7 shows 700 V and 1100 V switch voltages for 280 V and 500 V tests, respectively. Due to the presence of arc across SW1,$V_{C1}$ does not build up, and diode D2 cannot turn on until the fault current decays and the breaker terminal voltage decreases. However, it is noted that the arc has significantly reduced (from current waveform and visual inspection) in the hybrid DC breaker compared to Case 1 at the cost of excessively high capacitor (and switch) voltages. The current zero-crossing time is 5.5 ms and 8.5 ms for 280 V and 500 V tests, respectively, in this case. It is important to note that diodes D1 and D2 may not turn on in the absence of any voltage-restricting strategy at the breaker’s input terminals.

• Case 3: Hybrid DCCB with surge arrester

The proposed hybrid DCCB equipped with a surge arrester is used in this case (see Figure 1). As explained in Case 2, SW2 operates faster than SW1 upon the starting of the current disruption, leading to a voltage rise at C2 ($V_{C2}$) and the conduction of diode D1 (Stage 2). However, the surge arrester in this case provides a current path for the upstream current, leading to a reduced breaker terminal voltage at which the SW2 voltage is clamped; thus, $V_{C2}$ overvoltage is controlled. Next, the downstream current loops around the RL circuit comprising SW1, D1, and downstream inductance, since SW1 has not opened yet (Stage 3). Subsequently, SW1 opens, leading to a risen $V_{C1}$ and the turning of D2 (Stage 4), which in turn clamps $V_{C1}$ at the breaker input-terminal voltage (surge-arrester voltage), which has started to fall at this point. Thus, the downstream current flows back into the surge arrester via an RL circuit comprising D2, downstream inductance, D1, and the surge arrester (Stage 5). The peak capacitor voltages (switch voltages) in this case are 420 V and 805 V for 280 V and 500 V tests, respectively, compared to 700 V and 1100 V in Case 2. The current zero-crossing times are 4.5 ms and 9.6 ms for the 280 V and 500 V tests, respectively, which are comparable to those of Case 2 and are significantly improved compared to those in Case 1 (see Figure 8). A longer arc at SW1 causes a delay in the operation of the proposed breaker, as well as a longer disruption time in this case. Note that some overvoltage is still present due to the characteristics of the selected surge arrester, but it is significantly less than that in the original hybrid DCCB [11] and there is a significant arc reduction compared to the mechanical breaker alone.

In summary, the proposed hybrid DCCB has an improved downstream voltage and clearing time due to the bypassing capacitors, which provide soft switching in the mechanical switches, redirect diodes that restrict the capacitor voltages, and impose negative voltage on the downstream inductance, and the surge arrester, which prevents a voltage rise at the DCCB input terminals.

• Case 4. Simulation results

In the following, the hardware test results are compared with those from the simulation model using MATLAB/Simulink (R22b). A surge-arrester model is adopted that is described by

$${\displaystyle \frac{V_{SA}}{V_{ref}}}=K_i{\left({\displaystyle \frac{I_{SA}}{I_{ref}}}\right)}^{{\displaystyle \frac{1}{{\alpha }_i}}},i=1,2,\mathrm{a}\mathrm{n}\mathrm{d}3$$

(10)

where index $i$ corresponds to any of the three operating regions in the V-I characteristics of the surge arrester, as depicted by Figure 9 [24].

The surge arrester majorly operates in regions 2 and 3. The reference voltage $V_{ref}=300\mathrm{V}$ (the test voltage) and manufacturer value for reference current $I_{ref}=150\mathrm{A}$ are considered. From the experimental results of 280 V tests, parameters $K_1=0.95$, $K_2=1$, and $K_3=0.9915$ and ${\alpha }_1=50$, ${\alpha }_2=4$, and ${\alpha }_3=1.5$ are obtained. These parameters are then used to run the simulations for the 500 V test, where two surge arresters are put in a series similar to in the hardware tests. This, in turn, leads to $V_{ref}=600\mathrm{V}$ and $I_{ref}=150\mathrm{A}$.

Figure 10 depicts the simulated currents in the 280 V and 500 V tests. The upstream, downstream, and surge-arrester currents are illustrated. It is observed that the upstream current takes a longer time to diminish than the downstream current, i.e., 4.5 ms in the 280 V test and 9.6 ms in the 500 V test compared to 3.9 ms and 4.0 ms, respectively. Thus, the surge arrester alleviates the excessive voltage rise. Figure 10 also depicts the switch (and capacitor) and DCCB input-terminal voltages as well as the redirecting diode currents. Since SW2 operates faster (1.5 ms) than SW1 and the surge-arrester voltage drops meanwhile, diode D1 only turns on for a very short time. The surge-arrester blocking voltage and the diodes operation are in good agreement with the hardware results. Some discrepancy is natural due to the random behavior of the arc, as well as series resistances that could not be accurately modeled here. The actual series resistance seems to be slightly higher in the hardware experiment, providing better damping characteristics. This is in part due to the electromagnetic effects of the large coils on the coil resistances during the high fault currents (skin effect), as well as the diode and surge-arrester V-I characteristics.

Table 2. Current Zero-Crossing Time.

Voltage	Experimental	Simulation	Calculation
280 V	4.53 ms	4.37 ms	4.48 ms
500 V	9.54 ms	4.18 ms	4.83 ms

compares the current zero-crossing time of the experimental and simulation results with those calculated using Equation (9). By comparing the experimental, simulated and calculated results from Table 2, the average time for the current zero-crossing is 4.5 milliseconds. However, the zero-crossing time in the experimental results for the voltage level of 500 V is almost 9.5 milliseconds, due to the existence of an arc at the beginning of the contact separation of both switches (SW-1 and SW 2). Some of this time, which is around 8 milliseconds, relates to the arc that causes the hardware results to deviate from the calculated and simulated ones. Second, the selected breaker in the hardware test is recommended for 240 VDC and thus is overburdened when used at 500 V. Using a faster breaker will diminish the arc in a much shorter time, causing the experimental results to match those simulated and calculated.

• Case 5. Simulated distributed system

Next, the breaker is tested for a distribution system in MATLAB Simulink. A 10 km distribution line is considered, with an inductance of 3.33 mH and a resistance of 33 mΩ (0.33 mH/km and 3.3 mΩ/km [23]). A 13.8 KVDC supply is used with a nominal load current of 2000 A (Figure 11). Then, 300 µF bypassing capacitors are used parallel to the switches based on a fault current of 20,000 A and $C>{\displaystyle \frac{I_{fault}}{80\times {10}^6}}$ ($=250\mathrm{\mu }\mathrm{F}$), as explained earlier. The surge arrester is rated at 15 kV and $I_{ref}=20000A$. To test the effectiveness of the surge arrester, the breaker is placed at two different locations along the power line, namely at one-third and two-thirds of the distance from the source, with the fault occurring at the end of the line. We issue a trigger signal when the fault current reaches 20 kA. The delay between the operation of switches SW2 and SW1 is set at 500 µs.

When the breaker is placed at one-third of the distance from the source with the fault location at the end of the line, the proposed breaker has a smaller value of upstream impedance (1.11 mH and 11 mΩ). Figure 12 compares the current and voltage waveforms with and without the surge arrester.

As shown in Figure 12, the surge-arrester voltage, initially at 14 kV, drops to 9.4 kV when the fault starts. When the downstream current reaches 20 kA, the trip signal is issued and SW2 followed by SW1 operations occur. At this time, due to the voltage rise in the capacitors and the conduction of the redirecting diodes, the surge-arrester voltage reaches its blocking voltage of 15 kV and upstream current flows into the surge arrester, leading the surge-arrester voltage to rise to 18 kV based on its characteristic curve.

This, in turn, harnesses the capacitor (switch) voltages (at 23.2 kV). A low-cost breaker downstream isolates the downstream circuit upon reaching the downstream current zero-crossing. The downstream current zero-crossing is reached in 3 ms.

In contrast, in the absence of the surge arrester, the upstream current is forced to move downstream, excessively charge the bypassing capacitors, and cause a high overvoltage (52.8 kV). The high C1 voltage turns on D2 and pushes a reverse upstream current back into the source through the upstream inductance (29 kA peak reverse current). This potentially damaging current passes through the upstream inductance, C1, D2, and the source. Thus, an oscillatory behavior of upstream current is possible but can be prevented by using an additional (low-cost) breaker at the upstream branch. Nonetheless, the peak voltage at the DCCB input terminals reaches a very high voltage (53.8 kV).

When the breaker is placed at two-third of the distance from the source with the fault location at the end of the line, the proposed breaker has a larger value of upstream impedance (2.22 mH and 22 mΩ). Figure 13 compares the current and voltage waveforms with and without the surge arrester in this case. The capacitor (switch) voltages are clamped at 22.8 kV under the surge-arrester 18 kV blocking voltage. The downstream current zero-crossing is reached in 1.7 ms. Note that, in this case, the upstream current takes a longer time to decay. In contrast, the absence of the surge arrester causes a high overvoltage of 76 kV and an upstream peak reverse current of 22 kA. The surge arrester’s ability to consistently regulate voltage under different fault conditions, as demonstrated in this case, is essential for maintaining the overall performance of the proposed circuit breaker. This is especially crucial in scenarios with longer power lines or inductive loads where voltage spikes can be particularly harmful. Overall, the hardware and simulation results illustrate the effectiveness of the modified hybrid DC breaker equipped with a surge arrester.

The simple structure of the proposed DC breaker, where no bulky inductors are utilized in the DCCB, makes it an effective protective device in low- and medium-voltage DC circuits.

6. Conclusions

A hybrid DC breaker is proposed for low- and medium-voltage DC systems to effectively reduce arcing in the mechanical contacts using simple components. The proposed breaker utilizes a surge arrester, along with the bypassing capacitors used for the soft switching of mechanical contacts, to absorb the fault energy stored in the upstream and downstream line inductances of the faulty DC power line. The addition of the surge arrester in the proposed DC breaker restricts the excessive voltage rise in the bypassing capacitors while absorbing some of the fault energy. Hardware and simulation tests in various scenarios have shown significant improvements in fault-current interruption compared to the mechanical breaker and hybrid breaker without a surge arrester, especially when the DC breaker is placed far from the voltage source. Future work will explore the breaker’s performance for a wider range of applications, including high-voltage systems and networks with varying load dynamics. Additionally, further research is planned to achieve lower transient overvoltage with available surge arresters.