Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors

Abstract

It is shown that a serial-parallel processor, comparable in bit capacity to a 16-bit binary processor, can be implemented based on an algorithm built on the residue number system, a distinctive feature of which is the use of the first four quasi-Mersenne numbers, i.e., prime numbers representable as $p_k=2^k+1, k=1,2,3,4$. Such a set of prime numbers satisfies the criterion $2p_1{p}_2{p}_3{p}_4+1=P$, where $P$ is also a prime number. Fulfillment of this criterion ensures the possibility of convenient use of the considered RNS for calculating partial convolutions developed for the convenience of using convolutional neural networks. It is shown that the processor of the proposed type can be based on the use of a set of adders modulo a quasi-Mersenne number, each of which operates independently. A circuit of a modulo $2^k+1$ adder is proposed, which can be called a trigger circuit, since its peculiarity is the existence (at certain values of the summed quantities) of two stable states. The advantage of such a circuit, compared to known analogs, is the simplicity of the design. Possibilities for further development of the proposed approach related to the use of the digital logarithm operation, which allows reducing the operations of multiplication modulo $2^k+1$ to addition operations, are discussed.

1. Introduction

At present, there is considerable interest in increasing the productivity of computing equipment [1,2,3,4]. One approach to solving this problem is the use of parallel-sequential calculations [5,6], which are implemented, among other methods, using the residue number system (RNS) [7,8]. In this case, each integer x is represented as $\left(x_1,x_2,\dots ,x_n\right)$, where $x_i=x mod m_i$, $m_i;i=1,2,\dots n$ are integers that form the RNS [9]. The moduli $m_i$ are generally assumed to be pairwise coprime.

The advantage of RNS is its ability to independently operate with individual remainders $x_i$, in particular, $z_i=x_i+y_i$, if $z=x+y$ (similarly for multiplication). Such properties allow the move from sequential to parallel-sequential computations, since, when $x<M=m_1{m}_2\dots m_n$, each set of residues $\left(x_1,x_2,\dots ,x_n\right)$ represents exactly one integer $x$. Consequently, as long as this inequality is satisfied, computations using integers can be reduced to computations in RNS. From the perspective of computer technology, this limitation is not significant. In any case, the range within which standard processors operate is also limited (e.g., 16-bit adders).

The question of choosing a concrete set of moduli $m_i$ from the perspective of computer technology is not trivial. In particular, in the case that all numbers $m_i$ are prime, i.e., $m_i=p_i$, the computations corresponding to each component $x_i$ of the number $x$ are de facto performed in the Galois field $GF\left(p_i\right)$. Currently, numerous different types of electronic circuits are known that are designed to perform addition and multiplication operations in such fields, i.e., adders and multipliers modulo a prime number [10,11,12,13]. They differ significantly from one another in their design, which, moreover, significantly depends on the choice of the modulus, as is proven, in particular, by report [14]. Moreover, it was noted in [15] that different Galois fields have different specifics.

Consequently, there is every reason to assert that the choice of a set of moduli $m_i$ should be determined, first, by the specifics of the problems being solved. The technical implementation of this approach is facilitated by the widespread use of microcircuits with a reconfigurable logical structure [16,17,18]. Accordingly, it is permissible to raise the question of developing calculators oriented towards solving a certain range of problems.

In [19], it was shown that for calculating digital convolutions, it is convenient to use an RNS corresponding to a set of prime numbers $p_i$, such that $p_1{p}_2\dots p_n+1=P$, where $P$ is also a prime number. In this case, it becomes possible to reduce the discrete scale corresponding to the result of calculating the convolution to a discrete scale corresponding to the original function, without using fractional values.

This paper shows that a serial-parallel processor, comparable in bit depth to a 16-bit binary processor, can be implemented based on an algorithm built on the residue number system. The distinctive feature of this processor is the use of the first four quasi-Mersenne numbers, i.e., prime numbers representable as $p=2^k+1$.

The basis of such a processor is an adder modulo a quasi-Mersenne prime number. A specific electronic circuit of such an adder is presented, which can be called a trigger, since it can be in two different states. Its advantage over known analogs is the simplicity of the design.

It should be noted that Mersenne primes are currently widely used in information technology. In particular, these numbers are used to generate pseudorandom numbers [20]. Specifically, a pseudorandom number generator called the Mersenne Twister, developed in 1997 by Japanese scientists M. Matsumoto and T. Nishimura [21], is directly based on the use of Mersenne numbers.

Some reports demonstrating the expediency of using such numbers for data transmission are presented in the current literature [22,23], etc. Mersenne codes 3, 7, and 11 provide greater noise immunity and an increased probability of correct detection in radar channels, offering a potential alternative to Barker codes for noise-resistant data transmission in radio channels [24]. Modified RSA algorithm, using fixed Mersenne prime numbers, improves encryption in medical ultrasound imaging while maintaining adequate elapsed time for image transfer [25].

From the perspective of performing calculations modulo an integer, these numbers are particularly convenient because the multiplication of a number $a$ written in binary form by two modulo the Mersenne number is reduced to cyclic permutation of characters. For example, for calculations in the field $GF\left(7\right)$, the next equality is true

$$2·a_2{a}_1{a}_0{=}_{\left(7\right)}{a}_1{a}_0{a}_2$$

(1)

Relation (1) reflects the uniqueness of Mersenne primes. Quasi-Mersenne numbers are also unique, which is demonstrated in report [26]. Their uniqueness is due to the fact that the operation of digital logarithm, the study of which has recently received very serious attention [27,28,29], has a pronounced specificity in the case under consideration. Namely, the operation of digital logarithm allows us to reduce the operation of multiplication in a Galois field to the operation of addition. However, this operation is applicable only to non-zero elements of Galois fields. In Galois fields $GF\left(p\right)$, corresponding to quasi-Mersenne numbers $p=2^k+1$, the number of non-zero elements is obviously equal to $2^k$, i.e., the multiplication operation (after using the digital logarithm operation) is de facto reduced not simply to an addition operation, but to an addition operation in terms of ordinary binary logic, easily implemented on the existing element base (addition modulo $2^k$ is operationally reduced to discarding the most significant digits in the binary representation of a number).

It is appropriate to emphasize that the uniqueness of quasi-Mersenne numbers has not previously received the attention that they deserve. Evidence for this is provided in our recent report [26], where it was shown that it is possible to implement a simple and convenient method of digital logarithm specifically for such fields.

We also note that the approach using a specific Galois field (or varieties of such fields) is not fundamentally new. Modern binary computing technology is de facto built on the use of a specific field, GF(2). Consequently, the question of developing computing technology that uses the specifics of a particular type of Galois fields in a certain sense corresponds to the existing tradition.

2. Results

2.1. RNS Used

The RNS used is formed by the following quasi-Mersenne numbers (

Table 1. Quasi-Mersenne numbers used.

k	1	2	4	8
P = 2k + 1	3	5	17	257

) and the prime number 2.

Equality holds

$$2·3·5·17·257+1=\mathrm{131,071}$$

(2)

It is significant that the number 131,071 is prime. This means that this set of numbers satisfies the criterion formulated in [19], i.e.,

$$p_1{p}_2\dots p_n+1=P$$

(3)

where $P$ is also a prime number.

This criterion is very important, in particular, from the perspective of performing operations that are used by convolutional neural networks. As noted in [20], the following problem arises when digital convolutions are being used. The discretization scale of the convolution result may differ from the discretization scale of the original signal. To make the discretization step of these scales the same, one can use, for example, the operation of rounding to an integer. From a computational point of view, however, this is not convenient, since it is more convenient for any electronic devices to perform calculations in integers. As shown in [19], if criterion (1) is satisfied, then there is a simple and convenient way to reduce the above scales to a single format in which only calculations in integers are used. Thus, the fulfillment of criterion (1) for the first quasi-Mersenne numbers is additional evidence of their uniqueness.

In addition, ${\log }_2\mathrm{131,071}\approx 16.999978$. This means that the range of integers with which a processor built on the RNS under consideration can work with exceeds a typical 16-bit processor in terms of effective bit depth.

This fact also testifies in favor of the uniqueness of the set of prime numbers presented in Table 1. Calculations using the RNS corresponding to such a system correspond in their capabilities to one of the existing standards, but, as will become clear, there is an opportunity to move on to serial-parallel calculations. In this regard, it is appropriate to note that any existing technical standard (including those in the field of computer technology) is deliberately oriented towards specific quantitative indicators. The simplest example is the existing television standards, which fix the number of lines and the number of pixels in a line [30,31]. It is important that these standards can have a fairly large variety, as demonstrated by the standards corresponding to information display systems. Similarly, based on considerations of convenience and efficiency, a set of standards corresponding to computer technology can be implemented. In this regard, it is appropriate to note once again that the existing digital technology is de facto oriented towards a very specific standard associated with the choice of a specific Galois field $GF\left(2\right)$. It is precisely in this field that existing binary adders and other elements of binary logic are built.

This field has well-defined specifics, as well as well-defined advantages. This, however, does not exclude the possibility of using other Galois fields. Based on the analogy with existing processors, it seems advisable to begin by developing an adder modulo quasi-Mersenne numbers. For the processor under consideration, such an adder plays the same role as the classical binary adder in the most common processors. It is also important that the circuit for the developed adder be oriented toward the use of components that correspond to binary logic, since these are the ones that are produced industrially. Thus, this paper substantiates the possibility of using another standard of computer technology, one which has the same computing capabilities as existing 16-bit processors but allows for serial-parallel computations using a well-defined RNS. This approach is particularly convenient for computations corresponding to convolutional neural networks due to the fulfillment of criterion (2). In addition, as will become clear, it is the use of quasi-Mersenne numbers that allows us to propose fairly simple computing devices based on standard elements developed for binary logic.

2.2. Basic Scheme of Operation of the Calculators of the Proposed Type

The operational scheme of the proposed type of calculators is based on the following properties of algebraic rings, of which RNS is a special case, as emphasized in the report [19]. Such rings R decompose into a direct sum of ideals $r_i$

$$R=r_1+r_2+\cdots +r_n$$

(4)

Each of the ideals $r_i$ is generated by its complementary idempotent element $e_i$

$$r_i=R{e}_i,$$

(5)

The elements $e_i$ cancel each other out

$$e_i{e}_j=0, i\ne j; e_i{e}_i=e_i$$

(6)

The sum of these elements is equal to the unit of the ring $R$

$${\displaystyle {\sum }_i}{e}_i=1$$

(7)

Examples of such rings are given by rings of residue classes modulo a number $p$, representing the product of prime numbers $p=p_1{p}_2\dots p_n$. In this case, idempotent elements can be formed according to the rule used, in particular, in [20]

$$e_i={\alpha }_i{\displaystyle {\prod }_{j\ne i}}{p}_j$$

(8)

where ${\alpha }_i$ is an integer that is not a multiple of $p_i$. The choice of these numbers is based on the condition

$$e_i{e}_i=1$$

(9)

It is obvious that by construction we have

$$e_i{p}_i\equiv 0\left(P\right)$$

(10)

since any product of the form (10) contains the factor $p=p_1{p}_2\dots p_N$.

With the choice of integers ${\alpha }_i$ made, it also holds

$$e_1+e_2+\cdots +e_N\equiv 1\left(P\right)$$

(11)

In the case under consideration, an arbitrary element of the ring $R$ can be represented as

$$u=e_1{u}_1+e_2{u}_2+\cdots +e_N{u}_N$$

(12)

where $e_i$ are idempotent mutually canceling elements, and $u_i=0,1,2,\dots ,p_i$.

The convenience of representing (12) in calculations is that the elements $u_i$ are multiplied independently, and the multiplication is performed modulo $p_i$. Indeed, since $e_i$ are mutually annihilating idempotent elements, the product of two numbers $u^{\left(1\right)}$ and $u^{\left(2\right)}$ is expressed as

$$u^{\left(1\right)}{u}^{\left(2\right)}=e_1{u}_1^{\left(1\right)}{u}_1^{\left(2\right)}+e_2{u}_2^{\left(1\right)}{u}_2^{\left(2\right)}+\cdots +e_N{u}_N^{\left(1\right)}{u}_N^{\left(2\right)}$$

(13)

A similar formula is valid for the addition operation, which was also used in report [19]

$$u^{\left(1\right)}+u^{\left(2\right)}=e_1\left(u_1^{\left(1\right)}+u_1^{\left(2\right)}\right)+e_2\left(u_2^{\left(1\right)}+u_2^{\left(2\right)}\right)+\cdots +e_N\left(u_N^{\left(1\right)}+u_N^{\left(2\right)}\right)$$

(14)

Formulas (13) and (14) allow us to implement the following circuits of the multiplier and adder modulo the number $p=p_1{p}_2\dots p_N$, where $p_{\mathrm{i}}$ are prime numbers (Figure 1 and Figure 2, respectively). Common to these circuits are elements (1_i) and (2_i), which ensure the reduction of the original numbers to values modulo each of the prime numbers $p_i$. From the algebraic-theoretical perspective, such elements correspond to the transition to the use of calculations in Galois fields complementary to the ideals $r_i$. Blocks (3_i) perform multiplication or addition modulo prime numbers $p_i$, i.e., multiplication or addition in terms of Galois fields $GF\left(p_i\right)$. As follows from Formulas (13) and (14), the multiplication and addition of individual “components” of the original number can indeed be performed independently. Block (4) returns the calculation result to the number in the original representation in accordance with Formula (12).

Let us emphasize that formally the calculations using the presented schemes are performed modulo the integer $p$. However, if the result of addition and multiplication does not exceed $p$, it coincides with the result of calculations using ordinary arithmetic operations. For any physically implemented processor, the range in which the result of calculations fits is finite. This is particularly true for existing 16-bit processors. As follows from Table 1, the product $2·3·5·17·257=\mathrm{131,070}$ corresponds to approximately the same range. It is this fact that allows calculations to be performed in accordance with the proposed schemes without changing the result in the traditional “arithmetic” sense.

The circuits in Figure 1 and Figure 2 are applicable to any numbers $p=p_1{p}_2\dots p_N$, where $p_{\mathrm{i}}$ are prime numbers. However, there is a significant nuance. As will become clear, the degree of complexity of electronic circuits that perform calculations in different Galois fields varies. One of the simplest types of such calculators corresponds to the case where all the prime numbers in the above product are representable as $p_{\mathrm{i}}=2^{k_i}+1$, i.e., quasi-Mersenne numbers. For this reason, we focus on the use of such numbers in advanced processor technology, especially for that which ensures the implementation of convolutional neural networks.

2.3. Scheme of a Trigger Adder Modulo a Quasi-Mersenne Number

This section considers a specific design of adders, which have numbers (3_i) in the diagram in Figure 2. The proposed design is common to all adders modulo the quasi-Mersenne number.

The proposed adder circuit differs significantly from the modulo integer adder circuits reported in the current literature [32,33], including patents [34,35]. The adder circuits known in the literature are built entirely on direct logical operations, excluding the use of more than one stable state of the circuit. The paper [32] presents a modulo $2^n$ adder using the carry-save method. The circuit contains 48 logical elements and provides high performance for residual class systems. The paper [33] describes a unified modulo adder/subtractor designed for arbitrary modules. Its architecture uses 58 elements and a universal algorithm to improve hardware efficiency. Patent [34] describes a modular binary adder circuit that uses field-effect transistors to minimize computational delays. This patent includes 48 elements to ensure high-speed operation. Patent [35] describes a circuit that uses iterative calculations to obtain a residual value through multi-step addition, which significantly improves efficiency in systems that handle large numbers. This circuit uses 56 elements, including multiple operation units to improve accuracy and speed.

The fundamental difference between the proposed circuit and the known ones is that it is essentially an analog of a trigger, i.e., it is capable of being in two different stable states. This allows us to significantly reduce the number of logical elements used, as shown below. It is also significant that such circuits, which can be called trigger circuits, are quite simple to implement, especially when the addition is performed modulo a quasi-Mersenne number.

The circuit diagram of the proposed adder is shown in Figure 3. It includes two sets of conventional single-digit adders (1_i) and (2_i), where $i=1,2,\dots ,k+1$, logical AND elements (3) and (4), and a rectangular pulse generator (5).

The circuit is designed for summation modulo $2^k+1$ of numbers represented in binary form and lying in the range

$$0\le a\le 2^k$$

(15)

It is thus assumed that, before the summation operation, the original numbers have already been reduced to a value modulo the number over which the summation is performed. Thus, this circuit performs summation in the field $GF\left(2^k+1\right)$. In particular, this means that the largest number that this circuit operates, when represented in binary form, is written as

$$a_{max}=1\underset{k}{\underbrace{00\dots 0}}$$

(16)

In particular, this means that when summation is performed in the Galois field $GF\left(17\right)$, it is assumed that the inputs of the adder are fed signals corresponding to numbers in the range $0\le a\le 16$.

The circuit operates as follows. Binary signals corresponding to the representation of integers $a$ and $b$ in binary format are fed to the inputs $a_i and b_i$. The first line of adders (1_i) ensures the summation of these numbers in the usual binary representation. The second line of adders (2_i) is designed to reduce the sum to the sum modulo $2^k+1$.

Looking ahead, we note that the part of the circuit involving the second line of adders can also be used to calculate the components of the original numbers according to the rule $x_i=x mod m_i$. As noted above, it is assumed that before performing the operations implemented using the circuit in Figure 3, the numbers being summed have already been reduced to the format $x_i=x mod m_i$.

Let us consider the operation of the circuit in Figure 3 in more detail, taking into account that the nature of its functioning depends on the specific value of the summation result, which corresponds to the signals generated at the output of adders (1_i). In particular, the case when two numbers corresponding to the binary representation of the form (4) are summed is exceptional. The logical AND element (3) takes this exceptional case into account. When two numbers of the form (16) are summed, a logical one is formed at the output of the adder carry bit (1_k+1). Accordingly, a logical one is also formed at the output of element (3), which is transferred to the second gatherings of adders in the second line with numbers from 1 to $k$. The adder with number $k+2$ is absent in the second line. Consequently, transferring a logical one to the inputs of the adders indicated above effectively means that the number $2^{k+1}$ is subtracted from the number formed at the output of the first line of adders, and a number that contains exactly $k$ ones in binary representation is added.

We emphasize that the circuit in Figure 3 includes not $k$, but $k+1$ adders. This is necessary because there is an exceptional case when the output of the adder (2_k+1) differs from one. This case corresponds to the maximum number that can arise in calculations within the Galois field corresponding to a quasi-Mersenne number, i.e., a number that in binary representation has the form (16). Accordingly, when two numbers of the form (16) are summed modulo $2^k+1$, the number $2^k+1$ should be subtracted from the result of direct summation. This corresponds to subtracting the number $2^{k+1}$, which is achieved by the absence of an adder numbered $k+2$ in the circuit under consideration, followed by the addition of the number $2^{k+1}-2^k-1=2^k-1$. In binary representation, the last number is displayed as follows: The number $2^k$ in binary form is written similarly to Formula (16)

The difference $2^{k+1}-2^k=2^k$ is written as

$$2^k=1\underset{k}{\underbrace{00\dots 0}}$$

(17)

Therefore, the number $q=2^{k+1}-2^k-1$ is written as

$$q=2^{k+1}-2^k-1=0\underset{k}{\underbrace{11\dots 1}}$$

(18)

This formula shows that technically, bringing the summation result to a value modulo $2^k+1$ in the case under consideration essentially involves adding ones to all digits from the first to the digit with number $k$. This is the operation performed by the circuit in Figure 3, or more precisely, by the adders in the second line (2_i). It is appropriate to emphasize that in this circuit, additional ones are fed to the inputs of adders with numbers 1 through $k$, but are not fed to the adder numbered $k+1$.

As an example, let us consider the case when summation is performed modulo $2^2+1=5$. In this case, both lines (1_i) and (2_i) of the adder in Figure 3 contain three single-digit adders. The maximum value of the numbers being summed is 4, or 100 in binary representation. Note again that in this case, the most significant digit with the number $k+1$ (in this case, with the number 3), is used only to represent this special case. When calculating in the Galois field $GF\left(5\right)$, the two least significant digits are sufficient to represent the remaining elements. The sum of two numbers, 4, is equal to 8, or 1000 in binary representation. By discarding the most significant digit as a result of summation and adding the number 3 (written as 11 in binary representation), we exactly subtract the number 5, which gives the correct answer when summing modulo 5, i.e., 3.

Thus, element (3) allows us to obtain an adequate answer in the special case considered above. All other summation results can be classified as follows.

$$z:\left\{\begin{array}{c}0\le z<2^k\\ z=2^k\\ 2^k<z\le 2^{k+1}-1\end{array}\right.$$

(19)

In relation to the modulo 5 adder, this classification looks like this:

$$z:\left\{\begin{array}{c}0\le z<4\\ z=4\\ 4<z\le 7\end{array}\right.$$

(20)

In the cases corresponding to the first line of Formula (19), the second line of adders does not perform any actions. Integers lying in the range $0\le z<2^k$ do not require reduction to a value modulo $2^{k+1}$. In this case, the variable formed at the output of the adder (2_k+1) is zero. It is non-zero in the cases corresponding to the second and third lines of Formula (5). The difference between these cases is that the number $z=2^k$ does not require reduction modulo $2^{k+1}$, and the numbers corresponding to the range $2^k<z\le 2^{k+1}-1$—vice versa.

Reducing a number in the above range $2^k<z\le 2^{k+1}-1$ to a number modulo $2^{k+1}$ means that the number $2^{k+1}$ should be subtracted from the given number and, as in the case considered above, adding a number that in binary representation contains exactly $k$ ones, i.e., adding the number $q=2^{k+1}-2^k-1$.

Let us emphasize once again that for the binary representation of the number $2^{k+1}$, $k+2$ binary digits are required. For example, the number 8 in binary representation is 1000. The second line of adders in the circuit in Figure 3 contains $k+1$ single-digit adders. This means that the number $2^{k+1}$ will be automatically subtracted when it is used, even when a logical one is formed at the output of the carry bit of the adder with the number $k+1$.

The addition of the number $q=2^{k+1}-2^k-1$, composed in binary representation from $k$ ones, according to the circuit in Figure 3 is carried out in a manner similar to that discussed above.

The carry-out output of the single-digit adder (2_k+1) is connected by feedback to adders (2_i), $i=1,2..,k$ via the “logical AND” element (4). Consequently, the number $q$, given by Formula (16), will be added to the result of the primary summation (the first line of adders) if a logical one is formed at the output of the adder (2_k+1) or at the output of the generator (5).

The above feedback forms an analog of a trigger. Namely, if the result of the summation lies in the range $2^k<z\le 2^{k+1}-1$, then the circuit can be in two stable states. Indeed, adding the number $q$ results in the formation of a logical one at the carry-out output of the adder (2_k+1), which supports summation with the above number $q$. This represents one of the two stable states. The second stable state occurs when a logical zero is formed at the output of the adder carry bit (2_k+1). In this case, the number $q$ is not added to the result of the primary summation.

The generator (5) ensures switching between the two specified stable states. It transfers the circuit to the state “add the number $q$ to the primary summation result”. This reduces the result of the primary summation to the sum modulo $2^k+1$.

An exception arises when the result of the primary summation corresponds to Formula (16) or the second line in Formula (19). In these cases, it should also remain unchanged (for example, the number 4 does not require reduction modulo 5). This is also ensured by the circuit in Figure 3. To prove this, consider the following summation result

$$1\underset{k}{\underbrace{00\dots 0}}+0\underset{k}{\underbrace{11\dots 1}}=1\underset{k}{\underbrace{11\dots 1}}$$

(21)

This result does not lead to the formation of a logical unit at the input of the adder bit carry (2_k+1). Therefore, after switching off the generator (5), a return to the initial state corresponding to the number $1\underset{k}{\underbrace{00\dots 0}}$ will be performed.

Thus, in all three cases corresponding to Formula (19), the proposed circuit actually provides summation modulo $2^k+1$. Let us consider the results of testing the proposed circuit.

It should also be noted that the circuit in Figure 3 clearly demonstrates the advantages of using quasi-Mersenne numbers, as well as the possibility of generalizing the proposed approach to summation modulo other numbers. Namely, if we use the algebraic scheme for reducing the direct summation result to the summation result modulo, then depending on the value of the result, it is necessary to ensure that a certain value is subtracted from it, with a coefficient equal to 1 or 0. Taking into account the discarding of the most significant digit, this means that a number equal to the corresponding difference should be added to the summation result. With regard to quasi-Mersenne numbers, this is the number specified by Formula (18). With the same success, we can use other numbers whose binary representation contains k digits. The transition to using other numbers is reduced to changing the nature of the connections between the output of element (3) and the inputs of the adders in the second line in the circuit in Figure 3. However, when quasi-Mersenne numbers are used, this method corresponds to the possibility of feeding the same signal corresponding to a logical unit to the second inputs of the adders in the second line (Figure 3). While this may not be fundamentally important from the perspective of implementing electronic circuits, this does not diminish the convenience of using prime numbers of the type under consideration for building calculators designed to perform digital convolution operations and similar tasks. There is another significant argument in favor of using quasi-Mersenne numbers, considered in the Section 3. As shown in [26], for such numbers, it is quite simple to implement the digital logarithm operation, which allows us to reduce multiplier circuits in Galois fields to adder circuits in terms of ordinary binary logic.

2.4. Test Result of the Proposed Trigger Adder Circuit

Initial testing of the proposed schemes was carried out in the Proteus program. Figure 4 shows the results of testing the proposed adder circuit in Proteus for the case of the quasi-Mersenne number $2^2+1=5$. Figure 5 shows a similar result for a processor that provides summation modulo $2^4+1=17$. It is evident that the circuit operates in full accordance with the algorithm described above.

The circuits in Figure 4 and Figure 5 fully correspond to the circuit in Figure 3, or rather, are its specifications. These figures use standard notations for adders and logical AND elements. Figure 4a and Figure 5a correspond to the case when a logical zero is formed at the output of the rectangular pulse generator, which ensures the transition of the circuit from one stable state to another, and Figure 4b and Figure 5b correspond to the case when a logical one is formed at its output. The circuit shows that, when a logical one is formed at the output of the specified generator, the primary result of summation is reduced to the value of the sum modulo the number 5 (Figure 4) or 17 (Figure 5).

To test the functionality and correctness of the project written in VHDL, Testbench is used, which is a simulation environment.

To test the logic circuit, the input data consists of 5-bit binary numbers for the modulo 17 adder and 3-bit binary numbers for the modulo 5 adder. These adders were designed using Verilog. The program listing is attached in the Supplementary Materials.

The program for conducting testbench iterates over input binary 5-bit numbers from 0 to 31 (i, j) inside the program cycle. If the sum of the input binary numbers is greater than or equal to 17 (if sum_ij ≥ 17), the U14_Control input of the generator is activated. The results of the circuit’s operation are visible on the timing diagram of the ModelSim simulator (Figure 6).

3. Discussion

The proposed scheme for the adder modulo a quasi-Mersen number allows for the future to implementation of a processor that performs serial-parallel calculations due to the built in algorithm, built on a very specific RNS. As outlined in Section 2, the fact that this RNS is built on quasi-Mersen numbers allows to implement a relatively simple (compared with existing analogs) adder scheme. The basis of this processor is a set of adders in the fields $GF\left(2^k+1\right)$, each of which operates independently.

The simplest architecture of this processor can be implemented by analogy with existing processors, in which the basic operation is addition. The difference is that all numbers inputted into the calculator are initially converted into a format corresponding to the RNS of the proposed type. Consequently, further operations with each “component” of each number are carried out independently. Specifically, this means that the performance of such a processor is minimally affected by the units that provide the reduction of a number to a set of numbers modulo the first quasi-Mersenne numbers (the same applies to the inverse operation). Performance is determined solely by the adder itself, and the limiting factor (in terms of calculation speed, etc.) is associated with the adder containing the maximum number of elements (i.e., the adder modulo 257). This number corresponds to an 8-bit adder, while the adder as a whole corresponds to a 16-bit adder in terms of performance.

The prospects for the widespread use of a processor of this type may still be debatable; however, it is possible to indicate a very specific range of problems for which this processor is either optimal or close to optimal. For example, this applies to the calculation of partial convolutions, considered in [19].

There is no need to emphasize that the development of devices that calculate digital convolutions is becoming increasingly relevant. In particular, this is due to the increasingly widespread use of convolutional neural networks [36,37,38], which are used, among other things, for primary data processing by onboard computing systems installed on devices for various purposes. In particular, the development of onboard computing systems that perform primary image processing during remote sensing of the Earth is relevant. Specifically, it is necessary to exclude the transmission of images in cases where the surface is covered by cloud cover [39,40].

To solve such problems, it is advisable to use a processor of the proposed type precisely because it operates independently with different components of an integer. Consequently, it can be used both for standard calculations and for calculations oriented towards the use of partial convolutions, as described in [19], which is specially designed for the implementation of convolutional neural network algorithms.

Examples from other fields can also be provided, in which the proposed approach may be in demand. This applies, in particular, to the development of new measuring devices using the Fourier-Galois transform. An example of such a device (a viscometer), using the GF(31) field, was considered in [41]. Other devices of this type, in which the electronic unit is significantly modernized [42], could be oriented towards other fields. However, the most important thing is that, in this case, the range of numbers in which the calculations are performed remains limited. Another non-trivial field of application for the developed approach in the future may be electronics implemented on a non-standard element base. The search for such an element base is currently being pursued very actively (for example, this concerns the development of neuromorphic materials [43,44,45], optical computers [46,47], etc.). Promising neuromorphic materials are very diverse. In particular, it has been proposed to use organic electronics for this purpose [48,49], including those that use organic transistor [50] and optoelectronic elements [51]. A distinctive feature of such elements is ion-electron conductivity [52], which raises the question of developing an algorithmic basis complementary to the presence of charge carriers of several types. It should also be considered that developments in this area are focused on the use of non-trivial memory cells [53]. Moreover, the results reflected in [54,55] suggest that it is possible for materials representing a “hybrid” of neural networks and classical logical electronics to be implemented on the basis of polymeric materials that form memory cells due to their physical and chemical properties. This is due to the specificity of these environments, in which the manifestations of the phase transition [56] are accompanied by the so-called “multidimensional” hysteresis [57]. As emphasized in [54], the non-trivial element base of computing technology inevitably requires significant modernization of the algorithmic basis for performing calculations.

Furthermore, the use of quasi-Mersenne numbers as the basis for the RNS used in the processor algorithm offers another advantage. Namely, as shown in [26], for the Galois fields $GF\left(17\right)$ and $GF\left(257\right)$, a relatively simple algorithm for digital logarithm can be proposed, which allows the multiplication operation to be reduced to the addition operation.

This algorithm implements the mapping of any non-zero element of the Galois field, represented as

$$x={\theta }^n,$$

(22)

where $\theta$ is a primitive element of the field, on $n$: $x={\theta }^n\to n$. Recall that a primitive element exists in any Galois field $GF\left(p\right)$, and its powers from 1 to $p-1$ exhaust all elements of this field.

The number of non-zero elements of the Galois field $GF\left(p\right)$ is $p-1$, and the digital logarithm operation provides a mapping of the fields $GF\left(17\right)$ and $GF\left(257\right)$ onto the Galois fields $GF\left(2^4\right)$ and $GF\left(2^8\right)$, respectively [26]. This means that the multiplication operation, when using the digital logarithm operation, is reduced to standard addition operations, which can be performed using standard processors.

Thus, the combination of a processor of the proposed type, built on adders in the fields $GF\left(2^k+1\right)$, creates additional prospects for increasing the performance of computing equipment by transitioning to parallel-sequential calculations.

4. Conclusions

Thus, a purely mathematical fact—the existence of a unique prime number $\mathrm{131,071}$, representable as $P=p_1{p}_2{p}_3{p}_4{p}_5+1$, where $p_1=2$ and the remaining $p_i$ represent the first four quasi-Mersenne numbers, paves the way for the future implementation of a serial-parallel processor comparable in equivalent binary capacity to a classical 16-bit binary processor. This processor assumes independent operation with each component of an integer, representable in RNS, formed by the first four prime quasi-Mersenne numbers (3, 5, 17, and 257) and the number two. The architecture of such a processor, such as its classical analog, are adders, but for the proposed type of processor, these are adders modulo quasi-Mersenne numbers. The specificity of these numbers enables the implementation of a relatively simple circuit of a modulo adder. The simplicity of its design (compared to existing analogs) is ensured by the transition to a trigger circuit, where for certain values of the summed numbers, the circuit can be in two different stable states. Further development of the proposed approach can be based on the use of the digital logarithm operation. In this case, the multiplication operations in individual Galois fields corresponding to individual RNS components are reduced to addition operations, which are performed using conventional binary adders. The developed approach is applicable in cases where calculations are obviously carried out within a limited range of numerical values. In particular, for a processor built on the use of the first quasi-Mersenne numbers, the results obtained during calculations should not exceed 131,070. However, this is sufficient for many practical applications, particularly for the implementation of measuring devices built on the analysis of Fourier-Galois spectra.