Reliability Prediction of Mixed-Signal Module Based on Multi-Stress Field Failure Mechanisms

Abstract

The communication module is crucial for control systems. Under thermal, electrical, and mechanical stresses, sensitive digital and analog components may degrade in performance or fail, compromising the module’s long-term stability. Existing reliability-prediction methods, however, do not fully leverage multi-physics simulations to model stress-induced failure modes, leading to limited confidence in their predictions. This article proposes a systematic method to enhance the reliability prediction of mixed-signal electronic systems under complex operating conditions. First, we identify the key Complementary Metal-Oxide-Semiconductor (CMOS) chips and their associated failure mechanisms. Then, we use an I/O Buffer Information Specification-based (IBIS-based) topology to build a hybrid-precision simulation that models electrical stress. A Verilog-SPICE framework is employed to simulate component degradation and failure modes. Subsequently, by including mission profiles, we perform a simplified multi-physics coupling analysis to evaluate the effects of temperature and mechanical stress on failure mechanisms. Finally, the Physics of Failure models of components are integrated to derive the reliability curve of the module, and targeted optimization strategies are proposed. Compared to conventional methods, the method combines hybrid-precision simulation with multi-physics coupling modeling, improving the accuracy of critical failure modes. This method enhances the quantitative product reliability analysis and provides valuable support for optimized design.

1. Introduction

Communication modules primarily handle bus control interfaces, facilitate asynchronous transmission and reception across different modules, and manage synchronization signals (SYNC). Ensuring their reliability is crucial for optimal system performance. Reliability predictions are conducted based on operational principles and environmental conditions to support product optimization during the design and manufacturing phases.

The reliability modeling of electronic modules presents significant complexity. Digital–analog mixed-signal circuit systems within these modules encompass various digitally integrated chips and interface circuits, making it challenging for conventional circuit simulations to accurately capture timing relationships and signal integrity [1].

Due to the mixed-signal nature of the communication module, its components are sensitive to environmental conditions. The combination of thermal, electrical, and mechanical stresses leads to intricate failure mechanisms, further complicating reliability-prediction modeling [2,3].

Because of the mixed-signal nature of the communication module, its reliability prediction presents significant challenges. Consequently, simulation techniques for mixed-signal circuits have become essential for improving reliability-prediction accuracy. Current mixed-signal simulation primarily employs a coupling method [4], wherein digital and analog simulators operate concurrently, while a dedicated simulation platform manages their communication and coordination. Compared to SPICE-based analog simulators, digital modeling techniques, such as VHDL-AMS, Verilog-A, and Verilog-AMS, improve efficiency by reducing the simulation time. Recent advancements in real-number modeling (e.g., Verilog-AMS with wreal and SystemVerilog RNM) have further enhanced the simulation speed, making it comparable to purely digital models. Georgoulopoulos [5] implemented real-number models for sigma-delta analog-to-digital converters (ADCs), voltage-controlled oscillators (VCOs), and digital phase-locked loops (PLLs) using SystemVerilog, achieving faster simulations compared to SPICE. Moreover, studies [6] have proposed a mixed-signal verification framework based on the Universal Verification Methodology (UVM), balancing accuracy and efficiency in mixed-signal circuit simulation. Despite these advancements, existing methods still face challenges, such as high computational complexity and limited capability for multi-stress field simulations.

In reliability prediction, electronic component failure modes are generally categorized as performance degradation and functional failure. Performance degradation refers to the gradual deviation of component parameters from their designed values over time or environmental exposure, while functional failure manifests as abrupt changes in the circuit topology, such as short circuits or open circuits.

The Physics of Failure (PoF) method quantifies failure processes based on fundamental physical and chemical principles, leading to more precise reliability predictions. For instance, Poornaiah B [7] investigated the failure mechanisms of thick-film resistors and developed a failure time prediction model based on parameter drift. Shankar B et al. [8] analyzed Schottky diode failures under discharge conditions, revealing a mechanism involving trap accumulation at the anode metal/GaN interface. Liu J [9] examined the gate failure of SiC MOSFETs under a short circuit, identifying critical failure points within the SiO₂ dielectric layer. This article establishes corresponding PoF models for different failure modes as a foundation for reliability prediction.

Common methods in electronic system reliability modeling include reliability block diagrams (RBDs), fault tree analysis (FTA), Markov processes, and GO analysis [10]. RBD and FTA are primarily employed for system-failure-rate evaluations, whereas Markov processes and GO analysis are used to assess failure impact. Hirschmann D [11] applied the Arrhenius and Coffin–Manson models to predict inverter reliability under thermal cycling and compared the results with MIL-HDBK-217 and RDF 2000 handbooks, demonstrating improved prediction accuracy. Wan Y [12] proposed a stochastic reliability prediction model for electronic systems based on the Markov process and corresponding reliability improvement strategies. Sun B [13] integrated PoF and copula Bayesian networks to develop a reliability assessment method for complex electronic systems, addressing challenges associated with coupled failure mechanisms. However, the methods mentioned above directly consider the combined effects of multiple stress fields (such as electrical stress, thermal stress, and mechanical strain) on components.

In summary, traditional reliability-prediction methods have made significant progress in the field of electronic systems but continue to exhibit notable limitations, particularly in their ability to accurately reflect the complex characteristics of circuit ports. For instance, existing simulation methods for digital–analog mixed circuits, such as VHDL-AMS and UVM, still encounter challenges related to high computational complexity and insufficient accuracy. Additionally, conventional reliability modeling techniques, including Reliability Block Diagrams (RBDs) and Fault Tree Analysis (FTA), rely heavily on statistical data and struggle to effectively capture the coupling effects of electro–thermal–mechanical multi-stress fields on the combined impact on components. Furthermore, the internal structure of integrated devices is inherently complex, and current reliability-prediction approaches based on Physics of Failure (PoF) rarely identify specific failure mechanisms, such as Negative Bias Temperature Instability (NBTI) effects or solder joint fatigue. This limitation results in the inadequate integration of failure mode analysis and multi-stress field simulations, thereby compromising the accuracy of predictions regarding dynamic stress interactions.

Zhao C et al. [14] utilized continuous-time Markov chains to analyze the reliability of aerospace control systems under cascading failures. Through parameter sensitivity analysis, they selected different failure rates λ and priority orders for various modules to analyze their impact on system reliability, providing guidance for key failure module analysis and resource optimization. Among these, the issues concerning aerospace communication modules are particularly prominent. G. Yongjing et al. [15] confirmed that the intense thermal cycles and mechanical vibrations during spacecraft on-orbit operations significantly accelerate the failure of related modules, such as FPGA and SRAM, through mechanisms like plastic strain accumulation in solder joints and enhanced NBTI effects. R.J. Yuan et al. [16] further pointed out that under high-temperature and high-frequency operations, charge and discharge effects (SESDs) induced by spaceborne charged particles exacerbate errors and failures in FPGAs and SRAMs. Wang P et al. [17] proposed a method based on Architecture Analysis and Design Language (AADL) to establish a reliability model that includes aerospace communication module platforms, providing AADL error models for fault propagation among components, software, and hardware. However, these methods do not perform failure physics modeling for dynamic stresses on various critical devices, resulting in significant deviations in lifespan predictions.

To address these challenges, this study presents a reliability-prediction framework that integrates a hybrid precision simulation with multi-stress field coupling modeling. The key innovations of this approach are as follows: first, hybrid precision circuit simulation is employed and Verilog-SPICE heterogeneous modeling is used for high-precision analysis in critical paths, while behavioral-level abstraction is applied to non-critical areas, effectively balancing simulation efficiency and accuracy. Second, electro–thermal–mechanical multi-field dynamic coupling is implemented, with the finite element method and Anand’s constitutive model being used to quantify the feedback effect of thermal stress on solder joint fatigue, including power supply fluctuations caused by increased contact resistance. Finally, component-level failure mechanism modeling is developed for aerospace applications. The dynamic degradation-failure bimodal prediction models are established to address NBTI effects and solder joint fatigue, overcoming the limitations of traditional static analysis methods.

2. Methodology

This study focuses on a specific aerospace communication module based on the main control module of the satellite, combining digital–analog hybrid characteristics with electro–thermal–mechanical multi-field coupling simulation. It considers the combined impact of various failure mechanisms on module reliability under multi-stress conditions. The study covers both performance degradation and functional failure modes, and a reliability prediction model is developed. The overall research scheme is shown in the figure below. Through this approach, the precise prediction of reliability curves (error < 10%) is achieved, providing theoretical support for the optimization design of aerospace electronic systems.

The overall research framework is illustrated in Figure 1.

First, the communication module’s circuit topology is analyzed, and key components, along with their primary failure mechanisms, are identified based on environmental adaptability. Corresponding Physics of Failure models are then established.

Second, a hybrid-precision circuit simulation model is constructed. An IBIS interface model is developed for the digital-to-analog conversion interface using Verilog-AMS, while Verilog and the PostScript Simulation Program with Integrated Circuit Emphasis (PSPICE) are used to simulate digital and analog electrical stress, respectively.

Subsequently, an electro–thermal–mechanical multi-physics coupling model is developed based on the mission profile power distribution. The finite element method is employed to analyze the thermal accumulation effects induced by electrical stress, and thermal stress simulations are conducted to obtain the temperature field distribution. The temperature distribution is then used as a loading factor for mechanical simulations to evaluate critical regions’ stress and strain characteristics. This study uses coupled simulations to transfer thermal and mechanical simulation results to the electrical simulation.

Finally, a degradation-failure dual-modal reliability-prediction method is established by integrating simulation waveforms of failure modes with multi-physics stress analysis results. This method enables a comprehensive assessment of the impact of various failure mechanisms on reliability. The overall reliability of the communication module is calculated using a reliability block diagram, and weak links are identified for further analysis.

3. Failure Modes and Mechanism Identification of Key Components in the Communication Module

3.1. Analysis of Communication Module Operation and Key Component Classification

This article takes a specific communication module as an example to conduct a weakness analysis of its key components and identify their main failure mechanisms. The circuit structure of the communication module is shown in Figure 2, which primarily includes FPGA, SRAM, DS26C31, DS26C32, and a crystal oscillator.

The communication module operates with the FPGA as its core, coordinating the submodules and processing signals to achieve system functionality. The SRAM stores received command data and telemetry data during the operation. The DS26C31 and DS26C32 convert between single-ended and differential signals, enabling asynchronous serial communication among the FPGA, the management unit, and other functional modules via the RS422 protocol.

The main operational process of the communication module is outlined in Figure 3. First, the module receives command data from the management unit via RS422. The FPGA then decodes the command and stores the processed data in SRAM. Subsequently, the FPGA retrieves telemetry data from SRAM, assembles the data frame, and transmits it to the management unit via RS422. Afterward, the FPGA reads the stored command data from SRAM and forwards it to other functional modules through RS422. Finally, the FPGA collects the telemetry data returned by the functional modules, stores it in SRAM, and transmits it to the management unit upon receiving the next command.

By considering the operational conditions of the spacecraft in orbit, a preliminary analysis of the failure modes and their impact on the key components within the communication module can be conducted. The results are summarized in

Table 1. Failure modes and their impact on key components of the communication module.

Component	Function	Primary Failure Mode	Failure Impact
Diode	Circuit protection	Short circuit	No significant impact
Capacitor	Filtering	Short circuit	No significant impact
Resistor	RS422 signal transmission	Parameter drift	No significant impact
FPGA	Controller	Delay increase	Increased signal transmission time
		Loss of control functionality	Communication module failure
		Solder joint fracture	Open circuit at pins
SRAM	Data storage	Data read errors	Communication errors at device
		Solder joint fracture	Open circuit at device

. This article primarily focuses on the effects of three coupled factors—electrical, thermal, and mechanical stress—on the reliability of electronic components. It is considered that the shell and shielding layer of the spacecraft can achieve better protection against radiation and other stresses, and strict screening during the manufacturing process ensures that there are no manufacturing defects.

The crystal oscillators, DS26C31, and DS26C32 are aerospace-grade components that meet the screening criteria and provide outstanding stability under harsh environmental conditions. The stability of crystal oscillators arises from their material characteristics, whereas DS26C31 and DS26C32 employ differential transmission, power isolation, and built-in hysteresis comparators that can adapt to varying signal levels, preventing misjudgment caused by threshold fluctuations. These features collectively enable them to maintain high reliability even when exposed to complex electromagnetic environments, temperature fluctuations, and mechanical stress, resulting in significantly lower failure rates compared to ordinary electronic components [18]. C. Wu et al. [19] also confirmed the long-term reliability of mixed-signal interface circuits for aerospace applications, showing that under combined thermal and mechanical stress, the failure rate stays below 0.1% over 20 years; thus, they pose minimal reliability concerns. Consequently, this article does not analyze these components further.

Although resistors, capacitors, and diodes are also part of the module, they do not appear in the circuit diagram. Thick-film resistors and capacitors experience only limited parameter drift under low electrical stress [20,21,22], and capacitors mainly serve as filters rather than playing a critical role in system functions. Even though resistor parameter drift may affect the amplitude of RS422 signals, this does not compromise the communication module’s normal operation. Diodes primarily act as protection elements, and aerospace-grade diodes that have obtained relevant certifications demonstrate negligible failure rates in protection circuits [23,24]. Historical experimental data for various circuits confirm that under nominal operating conditions, these components exhibit inherent robustness, and mission-profile-based derating imposes a minimal impact on overall system functionality [25,26]. Consequently, they can be disregarded in reliability-critical scenarios.

The FPGA serves as the core control unit of the communication module, and its primary failure modes include increased signal delay due to electrical and thermal stress, the loss of control functionality, and solder joint fatigue failure caused by thermal stress. An increase in delay extends the signal transmission time, the loss of control functionality prevents the communication module from operating properly, and solder joint fracture results in an open circuit at the device pins.

SRAM is responsible for data storage in the communication module. Its primary failure modes include data read errors and solder joint fractures. Data read errors may introduce communication failures, while solder joint fractures can cause an open circuit at the device pins.

FPGA and SRAM are identified as the critical components due to their relatively significant influence based on the analysis of failure modes and their impact on key components within the communication module.

3.2. Failure Mechanism Analysis of Key Components in the Communication Module

The failure mechanisms of FPGA and SRAM are discussed based on the classification of key components.

FPGA and SRAM in the communication module are CMOS integrated chips with similar failure mechanisms. The primary failure mechanisms of these components include electromigration (EM), time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and negative bias temperature instability (NBTI). According to relevant research, under the aerospace operating condition, the impact of NBTI is relatively more significant [27]. NBTI primarily refers to the degradation of electrical parameters in PMOS devices under negative gate bias electrical and high-temperature thermal stress. Therefore, this article focuses on analyzing the impact of NBTI on FPGA and SRAM.

The PMOS transistor depends on the threshold voltage because an increase in the threshold voltage, as seen in the NBTI effect, leads to a slower switching speed and higher delays in the device’s operation. Specifically, when the threshold voltage increases, the gate voltage required to turn the PMOS transistor on becomes more difficult to achieve, which results in increased signal delay and, ultimately, the potential for functional failure if the delay becomes too large.

The failure mode of FPGA and SRAM solder joints is solder joint fracture, which leads to device failure and falls under the category of functional failure. Thermal stress occurs when an object undergoes constrained expansion or contraction due to temperature variations [28].

Under the influence of internal heat sources and alternating environmental temperatures, the difference in thermal expansion coefficients among various components on the circuit board results in varying degrees of thermal deformation and stress concentration. The solder joints of these components experience internal crack initiation under stress, and over time, these cracks propagate within the solder joints, eventually leading to joint failure.

4. Hybrid-Precision Circuit Simulation Validation and Stress Analysis

4.1. Development of Behavioral Simulation Models for Integrated Devices Using Verilog

To determine the electrical stress on key components within the communication module, a circuit simulation model needs to be constructed. Compared to board-level circuits composed of discrete components, digital integrated devices have more complex structures and functionalities, making it difficult to establish precise SPICE models directly.

Given the characteristics of mixed-signal circuits, this article adopts a hybrid-precision modeling method, achieving high-precision modeling for critical paths while applying approximate calculations for non-critical areas. The board-level circuit composed of discrete components is modeled using SPICE, whereas the digital control logic is simulated using a Verilog real-number model. Interface components are employed to synchronize simulation time steps. Hybrid-precision simulation combines the high accuracy of SPICE with the computational efficiency of Verilog, making it suitable for the precise analysis of critical circuit paths while reducing computational costs. This method is ideal for applications involving digital-analog interactions that require a balance between accuracy and efficiency.

The behavioral model of digital integrated devices primarily focuses on their logical behavior, abstracting input and output signals as logical ‘0’ or ‘1’ and describing their relationships. Verilog and VHDL are hardware description languages used to model digitally integrated devices, and in this article, Verilog is chosen to develop the behavioral simulation model for digitally integrated devices.

Based on the communication module’s circuit structure, the digital integrated devices include DS26C31, DS26C32, SRAM, and FPGA. The following sections establish behavioral simulation models for each device using Verilog and design validation circuits to verify their functionality.

4.1.1. Development of Simulation Models for DS26C31 and DS26C32

Before constructing the complete circuit model of the communication module, it is necessary to build simulation models for key integrated devices individually. DS26C31 is a CMOS differential line driver, and DS26C32 is a CMOS differential line receiver. These components enable the conversion between the FPGA and RS422 differential signals transmitted by single-ended signals within the communication module.

A simulation test circuit for DS26C31 and DS26C32 is constructed, as shown in Figure 4. The circuit’s input is a digital clock signal with a period of 1 µs, which is converted into a differential signal by DS26C31 and then restored to a single-ended clock signal by DS26C32. Ideally, this simulation test circuit’s input and output signals should be nearly identical.

Figure 5 shows the simulation results. The output signal is nearly identical to the input signal, demonstrating that DS26C31 and DS26C32 can successfully convert differential and single-ended signals.

4.1.2. SRAM Simulation Model Development

Next, the simulation model for the data storage unit SRAM is discussed. Based on its operating principle, a simulation test circuit for SRAM is constructed, as shown in Figure 6. In this circuit, a complete write and read operation is performed once per 4 μs cycle, with both the address and data incrementing by 1. When the SRAM operates correctly, the read data should match the written data.

A 20 μs simulation is conducted, covering a total of five cycles. The results are shown in Figure 7. It can be observed that the read data (data_out) match the written data (data_in), indicating that the SRAM is functioning correctly.

4.1.3. Development of the FPGA Simulation Model

As the control core of the communication module, the FPGA is closely related to the implementation of its functions. The FPGA simulation circuit is constructed, as shown in Figure 8. To verify FPGA functionality, the test circuit includes not only the FPGA itself but also SRAM. Additionally, it simulates a management unit and a functional module to provide command and telemetry data to the FPGA. To monitor FPGA output, a serial port module is incorporated into the circuit, which converts the FPGA’s returned serial data into 8-bit data. During the simulation process, the functional module transmits data to the FPGA. If the FPGA returns the same information to the management module, it is considered that the FPGA simulation model is functioning correctly.

The FPGA baud rate is set to 921,600, and a five-cycle data transmission and reception simulation is performed (approximately 22 ms). The telemetry data returned by the FPGA to the management unit are selected as the primary observation metric. The simulation results, as shown in Figure 9, indicate that the FPGA successfully receives and returns the telemetry data “123456789abc” to the management unit. Since the expected data are correctly included in the response, it can be concluded that the FPGA operates as intended.

4.2. Development of the Hybrid-Precision Simulation Model for the Communication Module

Since the analog components in the communication module are comparatively simple, they can be modeled using built-in SPICE device models provided by the Saber 2016 simulation software. Figure 10 shows the schematic diagram of the final simulation model for the minimum communication subcircuit. The module consists of 16 serial communication channels, with one serial communication channel presented as an example.

Additionally, since the DS26C32 receives differential signals as input, the analog input voltage must be differenced before conversion to a digital signal. It cannot be directly simulated using a single-ended input port model. Therefore, in this article, Verilog-AMS is used to re-model the DS26C32, integrating differential signal processing and analog-to-digital conversion directly within the DS26C32 model.

To validate the developed communication module circuit simulation model, a test circuit is designed where two communication modules communicate with each other. The schematic diagram of the test circuit is shown in Figure 11. During the simulation, command data are inputted into FPGA1, which forwards the command to FPGA2 while receiving telemetry data from FPGA2. FPGA2 processes the given telemetry data and transmits it back to FPGA1. Therefore, if the communication module functions correctly, the telemetry data returned by FPGA1 should contain the expected data.

The baud rate is set to 115,200, and the simulation test circuit performs five cycles of data transmission and reception (approximately 200 ms). The serial port module is used to monitor the telemetry data returned by FPGA1. The simulation results, as shown in Figure 12, indicate that FPGA1 successfully receives and returns the telemetry data. Since the expected data are correctly included in the response, it can be concluded that the communication module simulation circuit functions correctly.

4.3. Hybrid-Precision Circuit Stress Analysis

The transient electrical characteristics of the FPGA and SRAM, extracted from simulation results, form the basis for analyzing the electrical stress on key components under dynamic operating conditions. In the case of the FPGA, the I/O drive signal at 20 MHz generates a peak transient current of 185 mA, leading to a core voltage drop between 1.15 V and 1.25 V. This dynamic current fluctuation is mainly caused by simultaneous switching noise during high-speed signal transmission. For the SRAM, at a baud rate of 921,600, the address decoding circuit exhibits a maximum transient current of 62 mA, with static power consumption at around 48.49 mW. These dynamic power characteristics are closely linked to localized thermal stress accumulation, making them essential for multi-physics coupling analysis.

A further analysis of power and signal integrity under voltage stress shows that power supply noise, such as ripple on the 1.2 V rail, can cause fluctuations in the gate voltage of PMOS transistors [29]. In high-temperature environments, like 85 °C, these fluctuations accelerate threshold voltage drift due to NBTI, potentially reaching 15–20%. This mixed-precision simulation framework can be used to optimize decoupling capacitors and adjust the power-plane balance, ensuring that the gate voltage stress remains within a range of 1.2 V ± 1%, thus reducing NBTI-related degradation and preserving timing margins on critical paths.

Additionally, during frequency switching, the clock node experiences a peak voltage overshoot of 1.32 V, which is 10% higher than the nominal value. If the transient suppression circuitry degrades or control strategies fail, this overshoot can trigger latch-up in PMOS devices or lead to oxide breakdown [30,31].

5. Electro-Thermo-Mechanical Multi-Physics Coupling Analysis

5.1. D Model Construction of the Communication Module

To determine the coupled stresses under different failure modes, this article adopts an electro-thermo-mechanical multi-physics coupling model, overcoming the limitations of traditional single-stress superposition analysis. This model establishes a positive feedback loop to analyze the impact of electrical stress on the temperature rise, which subsequently induces thermal deformation and stress concentration. These variations may further lead to the loss of control over electrical stress within the module, ultimately negatively affecting its lifespan. By accurately capturing the amplification effects of stress interactions, this model avoids the underestimation of failure risks under extreme conditions commonly found in traditional static models, making it more suitable for scenarios involving transient power fluctuations in aerospace applications.

Initially, a 3D model of the communication module is established using a cross-scale modeling method, integrating the microscopic thermal distribution of individual components with the board-level thermal distribution. This article primarily focuses on FPGA and SRAM, which generate relatively high heat and have numerous solder joints, for detailed microscopic structural modeling. For computational efficiency, the microscopic structures of other components are not included in the model.

The 3D models of FPGA and SRAM are constructed based on their packaging types: the FPGA is packaged in FBGA-256, and the SRAM is packaged in TSOP-44. Figure 13 illustrates the package structures, with internal structures comprising the essential packaging components, bonding wires, die, die attach, and die pad.

When constructing the 3D models for FPGA and SRAM, to reduce computational complexity, the bond wires, die attach, and the communication module structure are simplified. Additionally, the 3D model of the FPGA solder joints is simplified to a truncated spherical shape. The final 3D model is shown in Figure 14.

The bonding wire in a semiconductor package plays a crucial role in providing electrical connections between the integrated circuit chip and the external pins or leads. It is typically made from gold, copper, or aluminum and serves as the pathway for electrical signals to and from the IC. In the context of the FPGA and SRAM 3D models, the bonding wire ensures that electrical signals can be properly transmitted between the chip and the external components, contributing to the overall functionality of the communication module. Although it is simplified in the 3D model to reduce complexity, in reality, the bonding wire ensures the reliable operation of the device by maintaining stable electrical connections.

5.2. Power Consumption Analysis and Thermal Simulation of the Communication Module

This article conducts a power consumption analysis for the FPGA and SRAM based on the communication module’s operating conditions. Subsequently, a thermal simulation model is created using Icepak to perform transient thermal simulations, obtaining the temperature field distribution at different time points during the temperature cycling process. This serves as a foundation for the subsequent mechanical simulation analysis and reliability evaluation of the communication module.

The FPGA and SRAM are the main sources of heat in the communication module, and their power consumption directly affects the temperature distribution and structural stress. The power consumption of CMOS circuits, such as FPGA and SRAM, can be divided into static power consumption and dynamic power consumption. The power consumption of CMOS circuits is expressed as follows:

$$P_{\mathrm{total}}=P_{\mathrm{s}}+P_{\mathrm{d}}=V_{\mathrm{dd}}\cdot I_{\mathrm{leakage}}+\alpha \cdot C\cdot V_{\mathrm{dd}}^2\cdot f$$

(1)

where P_total is the total power consumption, P_s is static power consumption, P_d is dynamic power consumption, V_dd is the supply voltage, I_leakage is the leakage current, α is a factor representing the switching activity of the circuit, C is the equivalent node capacitance, and f is the operating frequency.

From this equation, it is clear that power consumption is closely related to the leakage current and operating frequency in the communication module.

For CMOS circuits, the standby current is 10 mA, and the operating current at a frequency of 20 MHz is 185 mA. The standby current is considered the leakage current, and the difference between the operating current and the standby current represents the dynamic power consumption. When analyzing SRAM at high power consumption with a communication baud rate of 921,600, the circuit simulation model shows that the SRAM operating frequency is approximately 10,000 Hz at this baud rate. Using the equation below, the power consumption of the SRAM is estimated to be about 50.09 mW, with static power consumption as the dominant factor.

$$P_{\mathrm{SRAM}}=P_{\mathrm{s}}+P_{\mathrm{d}}=5\cdot 10+(185-10)\cdot {\displaystyle \frac{10000}{20000000}}\approx 50.09\mathrm{mW}$$

(2)

In the FPGA power consumption analysis, direct monitoring is difficult due to the numerous signals. Therefore, two rounds of data transmission and reception tests are conducted using Quartus II 13.1 and Modelsim 10.4 for co-simulation. The Modelsim gate-level simulation generates VCD waveform files, which are then analyzed using PowerPlay, as shown in

Table 2. FPGA power consumption analysis results.

Parameter Type	Parameter Value	Proportion of Total Power Consumption
Total power consumption	108.56 mW	50.04%
Core dynamic power consumption	8.32 mW	3.84%
Core static power consumption	48.49 mW	22.35%
I/O power consumption	51.57 mW	23.77%

. The total power consumption of the FPGA is found to be 108.38 mW, with static power consumption exceeding dynamic power consumption. The I/O power consumption is caused by the charging and discharging of drivers and external capacitors, combining both static and dynamic power consumption.

Table 3. FPGA unit power consumption analysis report.

Unit Type	Total Power Consumption (mW)	Unit Dynamic Power Consumption (mW)	Routing Dynamic Power Consumption (mW)	Unit Static Power Consumption (mW)
PLL	6.61 mW	6.61 mW	0.00 mW	N/A
Combinational cell	0.04 mW	0.03 mW	0.01 mW	N/A
Clock control block	0.78 mW	0.00 mW	0.78 mW	N/A
Register cell	0.89 mW	0.84 mW	0.05 mW	N/A
I/O	31.77 mW	0.35 mW	0.00 mW	31.42 mW

summarizes the power consumption for different unit types, ranked from highest to lowest, showing that the phase-locked loop (PLL) is the largest power source. The FPGA power consumption shows minimal fluctuation, with the maximum fluctuation being 3.94 mW, so the thermal simulation analysis primarily focuses on the average power consumption of 108.5 mW.

The thermal simulation model for the communication module is established by importing the 3D model and setting boundary conditions, environmental temperature, and material properties. Based on the power consumption analysis results for FPGA and SRAM, thermal loads are applied to the model, and meshing is performed to complete the thermal simulation model.

The environmental temperature of the spacecraft is a temperature cycle, with a temperature range from 0 °C to 50 °C, a heating and cooling rate of 10 °C/min, a high and low temperature holding time of 25 min, and a cycle frequency of 1 cycle/h, with an initial temperature of 20 °C.

Material properties for the model are determined, with the PCB’s thermal conductivity treated as anisotropic, and the rest of the materials are assumed to be homogeneous. Internal thermal loads are applied, focusing solely on the power consumption of the FPGA and SRAM chips. The power consumption distribution of the FPGA is obtained through modeling analysis, while the SRAM power consumption is set at 50.08 mW. The Quartus II 13.1 Chip Planner function is used, as shown in Figure 15, to map the power consumption results to the FPGA layout and routing diagram, allowing for the identification of specific locations.

This article analyzes FPGA units with power consumption no lower than 0.05 mW. Given the complexity of the FPGA solder joints, the Mesher-HD method is used for meshing. Since both FPGA and SRAM are small in size, they are treated as separate assemblies for meshing, and a separate assembly is created for the solder joint array. A mesh sensitivity analysis is conducted to evaluate the impact of the mesh size on simulation accuracy, ensuring a balance between computational efficiency and result precision. The final model contains 764,972 elements and 807,266 nodes.

After constructing the thermal simulation model for the communication module, a transient thermal simulation analysis is performed for 14,400 s, covering four temperature cycles. Upon completion of the analysis, the temperature distribution at the end of the high-temperature phase of the fourth cycle (at 12,480 s) is selected. This includes the temperature cloud diagrams of the FPGA chip, solder joint array, and SRAM pins, as shown in Figure 16.

It can be observed that the upper part of the FPGA solder joint array experiences significant heating, corresponding to the heating position of the chip. On the board, the simulation results show that the SRAM is influenced by the FPGA’s heat, leading to severe heating of the left-side pins. By analyzing the temperature variation of the FPGA and SRAM, the highest temperature solder joint is selected to plot the temperature curve, as shown in Figure 17, showing that the temperatures of both stabilize and are similar during the fourth cycle. The average temperature of the FPGA solder joints is 26.7602 °C, while the average temperature of the SRAM solder joints is 25.7766 °C. Additionally, the average temperature of the FPGA chip die is 26.7643 °C, and the average temperature of the SRAM chip die is 26.074 °C.

5.3. Mechanical Simulation of the Communication Module Based on Temperature Distribution

Based on the temperature distribution obtained from the thermal simulation, a mechanical simulation model for the communication module is developed using ANSYS Mechanical 2023 to calculate the stress and strain on the FPGA and SRAM solder joints.

In the ANSYS Workbench, a mechanical simulation model of the communication module is created, including the construction of the 3D model, temperature analysis, boundary conditions and material property settings, and model meshing. Then, thermal loads are applied based on the temperature data. Since thermal simulation significantly impacts the mechanical analysis, the model and temperature results are imported into the transient analysis module, where boundary conditions and material properties, including the density, Young’s modulus, Poisson’s ratio, etc., are set. The focus is on analyzing the stress and strain on the solder joints, and the Anand model is used to describe the material behavior of SAC305 solder joints.

After establishing the mechanical simulation model for the communication module, a transient analysis is performed. The focus of the analysis is on the Von-Mises equivalent stress in the FPGA and SRAM solder joints. The results in Figure 18 show that the maximum stress in the FPGA solder joints is 12.737 MPa, with higher stress at the edges than at the center. The maximum stress in the SRAM solder joints is 14 Mpa, with inner stress greater than outer stress. The simulation results, considering the chip power consumption distribution, are more complex and accurate compared to those from standalone mechanical simulations.

The solder joint with the highest stress in the FPGA and SRAM is selected as the critical solder joint. Assuming that the failure of this solder joint leads to device failure, the failure of the critical solder joint is used to approximate the failure of all solder joints. When evaluating the critical solder joint, the curve of equivalent plastic strain versus time is plotted, as shown in Figure 19. Using the Anand constitutive model, the simulation results for equivalent plastic strain include both plastic strain and creep.

Figure 19 shows that the equivalent plastic strain of the critical FPGA solder joint changes in a stepwise manner, ultimately accumulating to about 0.00111. The equivalent plastic strain of the critical SRAM solder joint fluctuates periodically, with a variation amplitude of approximately 0.0006106. These trends are consistent with the thermal cycling characteristics of the spacecraft environment, validating the temperature cycle assumptions. The different trends in the equivalent plastic strain of the critical FPGA and SRAM solder joints may be due to the dominance of plastic strain in the FPGA solder joints, while creep dominates in the SRAM solder joints, causing partial strain recovery.

This demonstrates that, under high dynamic conditions, such as those experienced by the spacecraft, rapid changes in power consumption can cause transient variations in the temperature field and mechanical stress. This model’s transient simulation verifies the cumulative effects of stress and plastic strain at different stages. Compared to traditional models that rely on steady-state or quasi-static assumptions, this method provides a more accurate evaluation of transient stress peaks and their cumulative damage.

5.4. Coupling Simulation of the Thermo Mechanical Model and Circuit Model

The dynamic coupling between stresses from the thermo-mechanical model and electrical stresses from the circuit model is central to the reliability prediction of aerospace communication modules discussed in this article. Under thermal cyclic loading, plastic strain accumulation in solder joints leads to a significant increase in contact resistance. For instance, an equivalent plastic strain of 0.00264 in FPGA solder joints, as shown in Figure 19, results in an increase in contact resistance by approximately 8%. Integrating this mechanical degradation into the circuit model causes transient voltage drops in the FPGA core supply, with peak-to-peak voltage fluctuations expanding to ±3%, as shown in Figure 20. These voltage fluctuations exacerbate the NBTI effect through dynamic threshold voltage drift. Experiments by Wagle et al. [32,33,34] indicated that even minor voltage fluctuations, such as ±3%, can increase the threshold voltage drift rate in MOS transistors by 12–15%, leading to delays of 8–10 ns in critical FPGA signal paths, which cause periodic data validation errors. Such timing errors force frequent resets of control logic, driving transient current peaks from 185 mA to 210 mA, further intensifying Joule heat accumulation in solder joints. This initiates a closed-loop failure chain from mechanical deformation to electrical degradation and, ultimately, to thermal stress intensification.

Temperature fluctuations also directly impact static power consumption via the leakage current in SRAM solder joints. For example, periodic variations of ±5 °C, as shown in Figure 17, cause an 18% rise in the SRAM leakage current [35,36], increasing static power consumption from 48.5 mW to 54.2 mW. This increased power consumption not only amplifies local temperature gradients, raising the temperature difference from 4.2 °C to 6.5 °C, but also exacerbates solder joint strain amplitudes, with a 22% increase in the strain amplitude, as depicted in Figure 19b. This is due to thermal expansion mismatch. Ultimately, this dynamic electrical–thermal–mechanical interaction accelerates fatigue crack propagation. The coupling mechanism revealed here highlights the limitations of traditional single-field models. Ignoring dynamic feedback, such as predictions based solely on electrical stress, leads to overly optimistic life estimations. In contrast, the multi-physics framework presented in this article captures stress interactions in real-time, controlling prediction errors within 10%.

6. Reliability Prediction of the Communication Module Under the Mission Profile

6.1. Performance Degradation and Functional Failure Simulation Method

To predict the reliability of the communication module, the performance degradation and functional failure of its components need to be simulated. Verilog-AMS is used for modeling, as it allows for the description of component behavior based on their voltage-current characteristic relationships. During the modeling process, the simulation time is introduced as a variable, enabling the dynamic adjustment of component characteristics to simulate performance degradation and functional failure.

Table 4. Simulation methods for performance degradation and functional failure within the Verilog-AMS framework.

Component Type	Failure Mode	Simulation Method
Analog components	Parameter drift	Import parameter degradation curves via lookup tables or expressions, modify corresponding parameters in the component model based on these curves.
	Open circuit/Short circuit	Use random numbers or specified failure times. Change the resistance values of series/parallel resistors once the failure time is reached.
Digital components	Output delay, amplitude, rise/fall time, and input threshold changes	Import performance degradation curves via lookup tables or expressions, modify the corresponding parameters in the mixed-signal interface model based on these curves.
	Logic errors, output loss	Use random numbers or a given failure time. After the failure time is reached, control the device model to output logic ‘1’.

summarizes the simulation methods for performance degradation and functional failure under the Verilog-AMS framework.

6.2. Key Component Performance Degradation Reliability Prediction

Based on the results of the mixed-signal multi-stress field simulation under the spacecraft mission profile, the reliability prediction of key components is carried out by constructing a Physics of Failure model to consider performance degradation. The analysis focuses on the FPGA and SRAM. Since the degradation and failure processes of these two components are similar, this section mainly considers the reliability prediction of the FPGA with regard to the impact of NBTI (Negative Bias Temperature Instability).

In the reliability prediction of the FPGA, the primary consideration is the impact of NBTI effects. Under the influence of NBTI, the threshold voltage of the PMOS in the FPGA gradually increases over time. On the one hand, the delay of the gate circuit increases as the threshold voltage increases. For the FPGA, an increase in delay can lead to timing issues during operation, causing the communication module to malfunction. On the other hand, as the threshold voltage increases, the PMOS in the FPGA becomes more difficult to turn on. If the threshold voltage exceeds the gate voltage of the PMOS, it will prevent the PMOS from turning on, which can also prevent the communication module from functioning properly.

To simulate the impact of FPGA delay degradation, the communication module simulation test circuit model shown in Figure 11 is used. The simulation results are used to identify the primary failure mode of the FPGA. The simulation time is controlled to adjust the rate of change in the FPGA’s delay, ensuring that the threshold voltage remains lower than the gate voltage during the simulation process. The simulation results are shown in Figure 20. From the figure, it can be observed that the telemetry data returned by the FPGA contain the expected data, indicating that the communication module continues to operate normally at this stage.

It is assumed that the failure of the PMOS is the primary cause of FPGA failure. The analysis focuses on PMOS failure due to the increase in the threshold voltage. The gate voltage of the FPGA can be considered equal to the core voltage of the FPGA, which is 1.2 V. Therefore, 1.2 V is set as the failure threshold for the threshold voltage. Based on this threshold, the lifetime and reliability of the PMOS are calculated using the NBTI failure physical model.

To analyze the long-term degradation process of the threshold voltage, the long-term NBTI degradation model from the multi-stress field Physics of Failure model is used. The specific model is as follows:

$$\Delta V_{\mathrm{th}}={\left({\displaystyle \frac{\sqrt{K_{\mathrm{v}}^2\alpha T_{\mathrm{clk}}}}{1-{\beta }_{\mathrm{t}}^{1/2n}}}\right)}^{2n}$$

(3)

$$K_{\mathrm{v}}=\sqrt[2n]{A}\cdot \sqrt{C}$$

(4)

$$A={\displaystyle \frac{q{t}_{\mathrm{ox}}}{{\epsilon }_{\mathrm{ox}}}}{\left[K^2{C}_{\mathrm{ox}}(V_{\mathrm{gs}}-V_{\mathrm{th}})\exp \left({\displaystyle \frac{2E_{\mathrm{ox}}}{E_{\mathrm{o}}}}\right)\right]}^{2n}$$

(5)

$$C=T_0^{-1}\exp (-{\displaystyle \frac{E_{\mathrm{a}}}{kT}})$$

(6)

$${\beta }_{\mathrm{t}}=1-{\displaystyle \frac{2{\xi }_1{t}_{\mathrm{e}}+\sqrt{{\xi }_{2}C(1-\alpha )T_{\mathrm{clk}}}}{2t_{\mathrm{ox}}+\sqrt{Ct}}}$$

(7)

The symbol ΔV_th represents the degradation of the threshold voltage. The constants K, E_o, T₀, n, ξ₁, and ξ₂ are fixed parameters used in the model. The gate oxide thickness is denoted by t_ox, and t_e is equal to t_ox. The gate oxide dielectric constant is represented by ε_ox, and C_ox is the capacitance per unit area of the gate oxide. The gate voltage is denoted by V_gs, while E_a refers to the activation energy. k is the Boltzmann constant, and T represents the temperature. The duty cycle is represented by α, while T_clk is the clock period, and t is time.

Based on the reference [37],

Table 5. NBTI degradation model parameters.

Parameter Name	Parameter Value	Parameter Name	Parameter Value
εox (F/m)	3.45 × 10−11	Ea (eV)	0.49
K (C−0.5·nm−2.5)	8 × 105	ξ1	0.9
Eo (V/nm)	0.335	ξ2	0.5
T0 (s·nm2)	1 × 10−10	n	1/6

summarizes the parameters used in the spacecraft’s long-term NBTI degradation model.

Based on the long-term NBTI degradation model, to calculate the threshold voltage degradation curve, it is necessary to obtain the gate voltage V_gs, initial threshold voltage Vth, and temperature T for the PMOS. The gate voltage is assumed to be 1.2 V, the initial threshold voltage is assumed to be 0.45 V, and the temperature T is approximated as the FPGA chip temperature, which is 26.7643 °C. Additionally, from the FPGA signal activity statistics in Section 4.2, it is determined that α·T_clk is approximately 0.14, and (1 − α)·T_clk has an average value of approximately 0.78.

Once all the parameters are determined, the long-term NBTI model is solved for calculation. Since the gate oxide thickness t_ox of the PMOS may fluctuate in practice, it is assumed to follow a normal distribution, t_ox~N(2.6,0.05). According to the FPGA resource usage in Table 2, the FPGA design uses 2458 basic logic units. It is estimated that each basic logic unit contains approximately 50 PMOS transistors, which means the FPGA design uses about 122,900 PMOS transistors. The next step is to calculate the threshold voltage degradation of these PMOS transistors. By substituting all the parameters into the long-term NBTI degradation model and considering the distribution of t_ox, the degradation curves of the threshold voltage over time for the 122,900 PMOS transistors are calculated. The average degradation curve is shown in Figure 21.

By considering the failure threshold of the threshold voltage, the time at which the threshold voltage reaches 1.2 V in each degradation curve is considered the lifetime of the PMOS under the effect of NBTI. The lifetimes of the 122,900 PMOS transistors are then calculated, and the lifetime histogram is plotted, as shown in Figure 22. The histogram follows a normal distribution, which proves the accuracy of the selected model parameters and simulation conditions.

A sufficient amount of virtual data helps to reduce the impact of sample errors on the results. Using the 122,900 PMOS lifetimes, the reliability curve of PMOS is plotted, as shown in Figure 23. Within the present operational cycles, the performance degradation of PMOS is evident, especially after prolonged operation, where the reliability decreases significantly. Compared to historical experimental data, the lifetime results are consistent.

Similar to the reliability-prediction process for FPGA considering NBTI, the reliability curve for SRAM units is also plotted, as shown in Figure 24.

6.3. Functional Failure Reliability Prediction of Key Components

Functional failure specifically results from solder joint fatigue in the communication module under the spacecraft mission profile. Given that the solder joints of FPGA and SRAM are relatively more prone to failure, this section focuses on the reliability prediction of solder joint fatigue in both FPGA and SRAM.

This section employs the Engelmaier model, which is based on plastic deformation, to analyze the fatigue life of solder joints. The Engelmaier model assumes that solder joint fatigue is driven by cyclic plastic deformation under thermal and mechanical stress, making it suitable for low-cycle fatigue conditions. It is applicable to lead-free and eutectic solder alloys within the temperature range of the spacecraft. The model is expressed as follows [38]:

$$N_{\mathrm{f}}={\displaystyle \frac{1}{2}}{\left({\displaystyle \frac{\Delta \gamma }{2{\epsilon }_{\mathrm{f}}}}\right)}^{{\displaystyle \frac{1}{c}}}$$

(8)

$$\Delta \gamma =\sqrt{3}\Delta {\epsilon }_{\mathrm{p}}$$

(9)

$$c=-0.442-6\times {10}^{-4}{T}_{\mathrm{m}}+1.74\times {10}^{-2}\ln (1+f)$$

(10)

$$t={\displaystyle \frac{N_{\mathrm{f}}}{f}}$$

(11)

where Δγ represents the range of plastic shear strain, Δε is the range of plastic strain, and ε_f is the material fatigue coefficient. The fatigue ductility exponent is denoted as c, while T_m is the average temperature of the temperature cycle. The temperature cycle frequency is represented by f, in cycles per day.

In Section 4.3, the equivalent plastic strain of the critical FPGA and SRAM solder joints under temperature cycling is analyzed. From the simulation results, the equivalent plastic strain range for the critical FPGA solder joint is 0.00264, while for the critical SRAM solder joint, it is 0.000443. Using Equation (9), the range of plastic shear strain for the critical FPGA solder joint is calculated to be 0.004573.

Based on the temperature variation with time in Figure 17, the average temperature of the FPGA solder joint during the temperature cycle is 27.77 °C, with a temperature cycle frequency f of 24 cycles/day. Substituting T_m and f into Equation (10), the fatigue ductility exponent c is calculated to be −0.40265. According to [39], for the solder material SAC305, considering uncertainties in the manufacturing process, the fatigue coefficient ε_f is assumed to follow a normal distribution ε_f~N(0.325,0.005).

For SRAM, the calculation method for each parameter is the same as for FPGA. After completing the calculations, the parameters used in the solder joint fatigue model are summarized in

Table 6. The parameters used in the solder joint fatigue model.

Component	Plastic Strain Range Δεp	Plastic Shear Strain Range Δγ	Fatigue Ductility Exponent c	Fatigue Coefficient εf
FPGA	0.00264	0.00457	−0.40265	N(0.325,0.005)
SRAM	0.00054	0.00094	−0.40206	N(0.325,0.005)

.

After substituting all the parameters into Equation (8), the number of cycles N_f required for the fatigue failure of 10,000 FPGA solder joints is calculated based on the distribution of the fatigue coefficient ε_f. Using Equation (11), the fatigue life of the critical FPGA solder joint is calculated, and the histogram of the FPGA solder joint lifetimes is plotted, as shown in Figure 25.

The lifetime data are then fitted, and the reliability R_FPGA-sj of the FPGA solder joint is calculated, with the reliability curve plotted as shown in Figure 26. This trend aligns with the physical nature of fatigue failure, where the bearing capacity of the solder joint gradually decreases as the fatigue process progresses, ultimately leading to failure.

Using the same method, the reliability of the SRAM solder joint R_SRAM-sj is calculated, and the reliability curve for SRAM solder joints is plotted, as shown in Figure 27. Due to the differences in stress, structure, and materials, the SRAM solder joint life is longer, and the decline in its reliability curve is less pronounced and lasts longer. During long-duration mission cycles, the fatigue life of the SRAM solder joints does not become the primary failure factor for the communication module.

6.4. Overall Reliability Prediction of the Communication Module

To predict the overall reliability of the communication module, the reliability of key components, FPGA and SRAM, must be calculated. In the device, every key component’s failure can lead to module failure. Since the failure mechanisms in the article are relatively independent, the reliability of each failure can be calculated separately, and then, the reliabilities for all mechanisms are used to determine the final reliability of the entire module. Based on this, the reliability block diagram for the overall reliability prediction of the communication module is shown in Figure 28.

The formula for predicting the overall reliability of the communication module is as follows:

R = R_FPGA × R_SRAM = R_FPGA-sj × R_FPGA-nbti × R_SRAM-sj × R_SRAM-nbti

(12)

where R is the overall reliability of the communication module, R_FPGA-sj is the reliability of the FPGA under the solder joint fatigue mechanism, R_FPGA-nbti is the reliability of the FPGA under the NBTI effect, R_SRAM-sj is the reliability of the SRAM under the solder joint fatigue mechanism, and R_SRAM-nbti is the reliability of the SRAM under the NBTI effect. The overall reliability of the communication module is calculated using Equation (12), and the resulting reliability curve is shown in Figure 29.

Analyzing the obtained reliability curve, it can be observed that the reliability of the communication module begins to decline at around 11 years, reaching zero at approximately 14.5 years. The time at which the reliability drops to 0.9 is around 12 years. Comparing with historical test data, the model accurately predicts the failure time and reliability variation of the communication module, indicating that the model’s accuracy meets the practical requirements.

Based on hybrid-precision simulation and multi-physics coupling models, this article predicts the overall lifetime of communication modules under aerospace mission profiles to be 14.5 years (12 years when reliability drops to 0.9). To validate the scientific validity of the method,

Table 7. Comparison of reliability-prediction methods for communication modules.

Method	Prediction Error	Modeling Dimension	Dynamic Feedback	Component Level Failure Mechanism	Applicable Scenarios
MIL-HDBK-217 [11]	±20%	Single stress field (thermal/electrical)	Not have	Not have	General electronic system
Bayesian network [13]	±15%	Multi stress field (probabilistic coupling)	Static state	Limited	Complex system-level analysis
PoF-RBD [10]	±12%	Multi stress field (linear superposition)	Static state	Partial (only performance degradation)	Industrial electronic module
Proposed method	<10%	Load-transfer multi-stress field coupling	Dynamics	Comprehensive (degradation + failure)	Aerospace communication module

compares the results of this article with existing typical reliability prediction methods, covering key indicators, such as the error range, modeling dimensions, and dynamic feedback capabilities. The prediction error is based on the standard deviation of 10 samples under the same experimental conditions. Dynamic feedback is defined as the multi-stress field coupling modeling capability, where coupling parameters are automatically transferred based on data processing platforms, such as Isight, while static feedback requires manual transfer of coupling parameters between different models.

As shown in Table 7, traditional methods, such as MIL-HDBK-217, rely on static stress assumptions, leading to prediction errors as high as ±20%. While the Bayesian network method proposed by Sun et al. incorporates multi-stress field coupling, it cannot dynamically capture component-level failure mechanisms, like NBTI or solder joint fatigue. In contrast, the multi-physics coupling framework presented in this article significantly enhances accuracy through key improvements.

One such improvement is the modeling of dynamic stress interactions. For example, plastic strain in FPGA solder joints leads to an increase in contact resistance, which in turn causes fluctuations in the power supply voltage. This exacerbates the NBTI effect, increasing the threshold voltage, thus creating a closed-loop failure chain. Another advancement is the integration of component-level failure mechanisms, where the PoF model quantifies threshold voltage drift and solder joint fatigue. This approach avoids the error accumulation typically seen in traditional linear superposition methods, such as PoF-RBD, which can result in errors of up to ±12%.

In terms of the practical application, the method proposed here supports spacecraft-design optimization by identifying and mitigating early risks. For instance, the solder joint fatigue reliability curve highlights FPGA edge solder joints as weak points, prompting layout optimizations, like increasing the solder ball density or using higher-reliability solder materials. Additionally, the framework provides significant engineering scalability by supporting a multi-module cascade analysis. This enables the examination of interactions between management units and functional modules, helping to prevent complete module replacements due to unpredictable cascading failures, making it well-suited for system-level reliability optimization in next-generation spacecraft.

7. Conclusions

This article presents a multi-physics reliability-prediction method for mixed-signal communication modules. By integrating hybrid-precision simulation with multi-stress field coupling modeling, this method extracts model parameters for performance degradation and functional failure, improving the accuracy of reliability prediction under complex operating conditions and in turn enhances the accuracy and applicability of the communication module’s reliability analysis. The main contributions are as follows:

Identification of key components and failure mechanisms: Based on environmental adaptability analysis, the key components in the communication module (resistor, FPGA, SRAM) and their main failure mechanisms are identified. These mechanisms include PMOS threshold voltage degradation due to NBTI effects and solder joint fatigue failure, and the corresponding Physics of Failure models are established.

Hybrid precision circuit simulation model: A hybrid-precision circuit simulation model for the communication module is constructed. Verilog is used to model the integrated components and their IBIS ports. Performance degradation and functional failure modes are simulated under electrical stress using a Verilog-SPICE heterogeneous simulation framework.

Electro-thermo-mechanical multi-stress coupling model: A multi-stress field coupling model is developed to simulate the multiple stresses acting on the components. The influence of electrically induced temperature distribution on the stress–strain characteristics of solder joints is studied, and equivalent plastic strain curves are obtained. A coupled simulation is used to transfer thermal and mechanical simulation results to the electrical simulation.

Dual-modal reliability prediction process: A dual-modal reliability-prediction process is proposed, combining performance degradation and functional failure. The performance-degradation trend is predicted based on threshold voltage drift, and the functional failure risk is assessed based on solder joint plastic strain accumulation. Reliability prediction for the communication module under a given mission profile shows that the FPGA solder joint becomes the dominant factor for system reliability after an 11-year mission cycle, providing a theoretical basis for targeted reinforcement design.

Future research will further expand to more complex failure mode analysis. For example, Temporal Convolution Networks (TCNs) will be used to process waveform sequence data from the IBIS model to identify failures, such as degradation in the driving capability of I/O buffers, replacing traditional static methods based on threshold criteria.

Additionally, by combining long-term, large-sample experimental data, digital twin models integrated with real-time operating data will be built. Through virtual stress testing, reliability weak points can be exposed in advance, enabling online reliability prediction and preventive maintenance.