Integrated DVB-X2 Receiver Architecture with Common Acceleration Engine

This paper proposes an integrated DVB-X2 receiver architecture to support multi-mode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The entire system consists of a tuner block, a H/W-based receiver engine, a frame processor, and an A/V decoder. Specifically, an integrated architecture to solve key design and technical issues such as reducing the complexity of the receiver, efficiently accessing the H/W-based receiver engine, and simplifying an OFDM demodulator is proposed. The H/W-based receiver engine for DVB-X2 demodulation and channel decoding functions is implemented in two FPGA devices. The frame processor is implemented with 256 MB memory and a DSP operating at a clock speed of 1.0 GHz. To verify functionalities of the proposed DVB-X2 receiver, various test scenarios were considered in the laboratory setting. In particular, the proposed system was tested under various operating modes, as specified in standards such as DVB-T2, DVB-C2, and DVB-S2, and demonstrated successful operations in all test scenarios.