A Thermopile Device with Subwavelength Structure by CMOS-MEMS Technology

Round 1

Reviewer 1 Report

This is an interesting and well written paper. In this paper several complementary metal-oxide-semiconductor (CMOS) compatible thermopiles with subwavelength structure (SWS) are proposed and simulated by the FDTD method. The proposed thermopiles are fabricated by the 0.35 μm 2P4M CMOS-MEMS process in TSMC (Taiwan Semiconductor Manufacturing Company). The measurement and simulation results show that the response of these devices with SWS is higher than the one without SWS. I have only one question regarding choosing the modulation frequencies. What with response at higher frequencies?

 

Author Response

The authors want to thank the unknown Reviewers and the Editor for their precious comments. We want to highlight that all the changes in the paper have been marked as follows: the green marked one represents all the adding.

 

Response to Reviewer 1 Comments

 

 

Point 1: I have only one question regarding choosing the modulation frequencies. What with response at higher frequencies?

Response 1:

Thank the reviewer for the question regarding choosing the modulation frequencies. Actually the frequency of measurement ranges from 1~150 Hz to investigate the bandwidth of the frequency response and the range is much higher than the bandwidth of proposed thermopile, 32 Hz. The explanations are supplemented in the article with green mark.

 

Author Response File: Author Response.docx

Reviewer 2 Report

Line 55: Please explain the contribution of your results, these are good, bad, poor, optimum with any propose...etc.

This manuscript presentation needs to be improved.

1.- Figures: place the same text size in all document figures.

2.- Figure 4a: resize the % axis in order to help the examination of data.

3.- Figure 5: difficult to understand.

4.- Figure 6b: Edit the figure, difficult to understand the text.

5.- Figure 9: resize the axis...

 

Author Response

The authors want to thank the unknown Reviewers and the Editor for their precious comments. We want to highlight that all the changes in the paper have been marked as follows: the green marked one represents all the adding.

 

Response to Reviewer 2 Comments

 

Point 1: Line 55: Please explain the contribution of your results, these are good, bad, poor, optimum with any propose...etc.

Response 1:

Thank the reviewer for the remind about comments on the contribution of results. More helpful explanations are supplemented in the article as follows.

Beyond the development of optimized structured absorbers for CMOS infrared detectors empirically, it was firstly proposed with theoretical analysis and investigation with experiments thoroughly. In this study, various CMOS compatible thermopiles with subwavelength structures are fabricated in the standard 0.35 mm CMOS-MEMS which are numerically and experimentally investigated and it meets highly agreement with response curves.

 

Point 2: 1.- Figures: place the same text size in all document figures.

Response 2:

Thank the reviewer for the remind on the text size in all document figures. We have modified the size of text in all figures.

 

Point 3: 2.-  Figure 4a: resize the % axis in order to help the examination of data.

Response 3:

Thank the reviewer for the remind on the % axis in Figure 4a. We have modified the % axis in the article.

 

Point 4: 3.- Figure 5: difficult to understand.

Response 4:

Thank the reviewer for the precious comments on Figure 5. The processes are indeed lack of clear explanations. More helpful explanations are supplemented in the article as follows.

The standard CMOS process in TSMC fabricates the array of thermocouples with CMOS materials of polysilicon and aluminum as the step 1.

In step. 2, the etching windows and active area are formed by some specific MEMS processes. There structures are fabricated with RLS and RLSSI processes which etch the Si3N4/SiO2 layers and silicon substrate subsequently. The patterns of the SWS are formed in the RLS process with RIE etching of the Si3N4/SiO2 layers on the active area. By using the RLSSI process, the RIE etching of silicon substrate is proceeded under the membrane. Therefore, the sensing area is floated and filled with arrays of etching hole as the periodic refractive index waveguide.

 

Point 5: 4.-  Figure 6b: Edit the figure, difficult to understand the text.

Response 5:

Thank the reviewer for the remind on the editing in Figure 6b. We have modified the figure and text in the article as follows.

Figure. 6(a) and 6(b) show SEM images of a CMOS compatible thermopile, which can be compared to Figure. 1 and 5.

 

Point 6: 5.- Figure 9: resize the axis.

Response 6:

Thank the reviewer for the remind on the size of axis in Figure 9. We have modified the size of axis in the article.

 

Author Response File: Author Response.docx

Round 2

Reviewer 2 Report

Just one observation: Figure 4, a,b, c. are similar, I think it will be best represented/summarized in only one figure. Same case for figure 9.

Author Response

The authors want to thank the unknown Reviewers and the Editor for their precious comments. We want to highlight that all the changes in the paper have been marked as follows: the green marked one represents all the adding.

Response to Reviewer  Comments

Point 1:

Just one observation: Figure 4, a,b, c. are similar, I think it will be best represented/summarized in only one figure. Same case for figure 9.

Response 1:

Thank the reviewer for the reminds on Figure 4 and 9. We have modified the represented/summarized in only one figure 4 and  represented/summarized in only one figure 9 .

Author Response File: Author Response.docx