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Article

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

by
Yuyun Chen
1,
Yi Shen
1,*,
Yuanming Chen
1,
Guodong Xu
1,
Yudong Liu
1 and
Rui Huang
2,*
1
Guangdong Provincial Key Laboratory of Automotive Display and Touch Technologies, Shantou Goworld Display Technology Co., Ltd.,12 Longjiang Rd., Shantou 515065, China
2
School of Materials Science and Engineering, Hanshan Normal University, Chaozhou 521041, China
*
Authors to whom correspondence should be addressed.
Coatings 2024, 14(5), 555; https://doi.org/10.3390/coatings14050555
Submission received: 22 March 2024 / Revised: 17 April 2024 / Accepted: 25 April 2024 / Published: 30 April 2024
(This article belongs to the Special Issue Advanced Metal Oxide Films: Materials and Applications)
Browse Figures
Versions Notes

Abstract

:
Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

1. Introduction

Indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) are quite popular in the display field, due to their high mobility and transparency, large-area uniformity, and low-temperature processability [1,2,3]. Positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) stabilities determine the on-state and off-state stabilities of IGZO TFTs, respectively, both of which are key issues for applications [4,5]. In order to enhance the electrical stabilities and maintain the uniformity of amorphous IGZO TFTs, the active layers require annealing at a temperature that is higher than the deposition temperature (room temperature in most cases) but lower than the crystallization temperature (i.e., ~600 °C) [6,7,8]. Although the effects of annealing temperatures (Ta) on the IGZO films or the transfer characteristics of the as-fabricated IGZO TFTs have been studied [6,9,10,11,12,13,14,15,16], limited attention has been paid to their PBTS and NBTS stabilities, which are more important technical indicators. The structural origin (generally at the atomic scale) for the effects of Ta on bias stress stabilities has not been fully investigated.
Configurations of IGZO TFTs primarily involve a top-gate staggered structure, a bottom-gate staggered structure, a top-gate coplanar structure, and a bottom-gate coplanar structure [3]. Among these configurations, bottom-gate structures are commonly used for prototype displays since the gate metals at the bottom enable to blocking of the backlights. Compared with the staggered structure, the coplanar structure has some advantages such as simpler fabrication methods, lower contact resistances with source and drain electrodes, and smaller stray capacitances. Nevertheless, extra defects may be introduced at the interface between the active layer and the insulator of coplanar TFT during deposition and patterning of source/drain layers, which would affect the successive deposition of the active layer and result in poor electrical stabilities. Controlling the post-treatment temperature is important for coplanar TFTs to achieve a high-quality interface and active layer structure and enhance electrical stabilities.
In this work, the bottom-gate coplanar TFTs with IGZO films annealed at different Ta were prepared and their bias temperature stress stabilities were compared. The atomic structures of IGZO/dielectric layers were examined to understand the structural origin since the electrical instabilities were closely related to de-trapping or trapping of charged particles near or at the IGZO/dielectric interface [5,17,18,19,20]. Considering that multiple elements are irregularly involved within IGZO/dielectric layers, depth profiling was performed by X-ray photoelectron spectroscopy (XPS) for a detailed structural analysis.

2. Method

The bottom-gate coplanar IGZO TFTs were prepared using the following steps: 100 nm Mo, 200 nm SiO2, and 100 nm Mo were deposited on the glass substrates successively, which were the gate electrode, insulation dielectric, and source/drain electrode of the oxide TFTs. After magnetron sputtering deposition, each of the above layers was patterned using wet-etching methods. Then the active films were deposited by mid-frequency (MF) magnetron sputtering of the IGZO targets (In2O3: Ga2O3: ZnO = 1:1:2 mol%). The IGZO films were annealed in air at different temperatures (Ta = 300 °C and 400 °C) for one hour and wet etched for the desired channel size (10 μm in length and 50 μm in width). Here, Ta below 250 °C was not considered, because it was found that the IGZO layer was not sufficiently oxidized at 250 °C and it was difficult to turn the TFTs off. Ta over 400 °C was not considered either since Mo was slightly oxidized at 400 °C and their conductivity may be more or less reduced. At last, 1 μm polymethyl methacrylate (PMMA) passivation layers were coated and patterned to expose the gate, source, and drain electrodes.
A P100 Source Meter was used to measure the transfer characteristics of our IGZO TFTs. During the drain current (IDS) measurement, the gate voltage (VGS) varied from −10 V to +20 V and the drain-source voltage (VDS) was maintained at 10.1 V. Based on the IDS-VGS transfer curves, we extracted some electrical parameters, including saturation mobility μ, subthreshold swing SS, the ratio of on-state to off-state current Ion/Ioff, and the threshold voltage Vth. The SS was calculated from the reciprocal of the maximum slope in the log (IDS)-VGS transfer curves. The μ and Vth were calculated by linear extrapolation of the IDS1/2-VGS transfer curves [21,22].
The electrical stabilities of IGZO TFTs were evaluated using positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) tests. During PBTS tests, VGS, VDS, and environmental temperature (T) were maintained at +20 V, 0.1 V, and 60 °C, respectively. During NBTS tests, VGS, VDS, and T were set at −20 V, 0.1 V, and 60 °C, respectively.
The depth profile of IGZO/SiO2 layers was collated using scanning X-ray photoelectron spectroscopy (XPS) (PHI 5000 V Versa Probe III, Chigasaki, Japan) with a monochromatic Al Kα X-ray source (1486.6 eV, 50 W, 15 kV). To control/minimize the charge building, a conductive mask was used to provide a conducting pathway and charge neutralization facilities of XPS instruments were applied. When the XPS spectra were collected, the base vacuum of the testing chamber was kept at 6.9 × 10−8 Pa. The broad survey spectra were collected for the original surface, which included C1s signals. Then, the depth profiles were further collected after every 0.5 min Ar+ sputtering. The energy and area of the Ar+ beam were set at 2 keV and 3 mm × 3 mm, respectively. The profiles of element contents (including carbon, oxygen, gallium, zinc, and indium) were obtained from these spectra. The C1s region showed that the carbon contamination was sufficiently removed after the first 0.5 min of sputtering. C1s at 284.8 eV for carbon on the surface were chosen for calibration. The core-level spectra were fitted using the Gaussian/Lorentzian function with Shirley-type background subtraction. The IGZO layers were also characterized using scanning electron spectroscopy (Gemini 450, Zeiss, Cambridge, UK).

3. Results

3.1. XPS Characterization

In-depth photoelectron spectra in the range of 150~170 eV for IGZO/SiO2 samples annealed at different temperatures (Ta) are given in Figure 1. With increasing depth from the IGZO surface, variations in the photoelectron spectra can be divided into three stages. First, only one component centered at ~161.0 eV was observed in the spectra, the position of which agreed with that of the Ga3s component for the Ga2O3 reference samples [23]. This component can be attributed to the Ga-O bonds within the IGZO layer. The position as well as line shapes of the spectra at the first stage were almost unchanged (see the green spectra in Figure 1), indicating a uniform IGZO layer. Second, the Ga3s component shifted towards a lower binding energy (BE) side and an additional component at ~153.0 eV appeared. BE of the latter component was close to that of the Si2s component of SiO2 [24]. Such double-peak spectra suggest an IGZO-SiO2 interfacial mixing layer, the thickness of which was ~15 ± 2 nm. The interfacial mixing layer can be seen as the result of the implantation of atoms from the oxide target into the SiO2 surface. Third, there was only one Si2s component in the following spectra, which can be attributed to the signal from a SiO2 layer. The above variations indicate that the film structure of IGZO/SiO2 includes three parts: an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. The effects of Ta on the atomic structures of these three parts were further investigated.

3.1.1. IGZO Layer

Figure 2 displays core-level spectra collected at a depth of ~5 nm from the surface to exemplify the uniform structure of the IGZO layer. In Figure 2a–c, there were symmetric components centered at ~161.0 ± 0.1 eV, ~1022.15 ± 0.15 eV, and ~445.05 ± 0.15 eV, which were in agreement with those of the Ga3s, Zn2p, and In3d components of Ga2O3, ZnO, and In2O3 reference samples, respectively [23,25,26]. These components arose from Ga-O, Zn-O, and In-O bonds in the IGZO layer. The fitting spectra, which were generated from a one-component model, agreed well with the experimental spectra in Figure 2a–c. The fitting results (see in Table 1) showed that at higher Ta, the full width of half maximum (FWHM) was nearly unvaried, but the position of these components shifted towards the higher BE side (i.e., +0.3 eV). These phenomena suggest an enhancement in the binding energy of Ga-O, Zn-O, and In-O bonds within the IGZO layer.
In Figure 2d, asymmetric O1s spectra consist of one major component (OI) at ~530.9 ± 0.4 eV and a sub-component (OII) on the high-BE side. Generally, OI and OII components were considered to be the result of M-O (M represents the metallic elements in IGZO) bonds and oxygen vacancies, respectively [27,28,29]. However, Idriss believes that a signal arising from an oxygen vacancy is impossible, based on the following reasons [30]. First, it is unreasonable in principle that photoelectron spectroscopy enables one to measure the kinetic energy of a missing electron. Second, the surface oxygen vacancies would be oxidized instantaneously in an ambient environment due to the strong adsorption energy of H2O, and thus ex situ measurements of oxygen vacancies were impossible. The sub-component in O1s spectra for metallic oxides is thus attributed to some structural imperfections containing oxygen atoms, such as hydroxyls, water molecules, and organic contaminants [30,31]. In our case, the correlation between the sub-component and organic contaminants was excluded since there were no C1s signals for the spectra collected from the IGZO layer. Fitting spectra generated from a double-component model agreed well with the experimental O1s spectra, and the area ratio of the OII component (AOII%) was calculated. It was found that AOII% for the IGZO layer was not sensitive to Ta, suggesting that comparable O-related imperfections were introduced into the IGZO layer at both Ta.

3.1.2. IGZO-SiO2 Interfacial Mixing Layer

The atomic structures of the IGZO-SiO2 interfacial mixing layer were further studied. In Figure 3a–c, the Ga3s, Zn2p, and In3d components at 159.90 ± 0.01 eV, 1021.35 ± 0.05 eV, and 444.1 ± 0.1 eV, respectively, were observed in the core-level spectra of the interfacial mixing layer annealed at both Ta. Compared with those for the IGZO layer, the BE of these components for the interfacial mixing layer (Table 2) was relatively lower. Additionally, full width of half maximum (FWHM) values of the Zn2p and In3d components for the interfacial layer (Table 2) were larger than those for the IGZO layer. These differences indicate that the M-O chemical bonds in the interfacial mixing layer were weaker and more disordered than those in the IGZO layer. At higher Ta, the Ga3s and Zn2p components were almost unvaried, but the In3d component shifted evidently towards the low-BE side (−0.1 eV). These results suggest that Ga-O and Zn-O bonds became somewhat weaker while the In-O bonds turned out to be apparently weakened at higher Ta. This phenomenon can be interpreted in terms of their bond energy, which led to distinct thermal stabilities. The In-O bonds exhibit a relatively lower bond energy and thus are more thermally unstable compared with Ga-O and Zn-O bonds [32,33]. Unlike those in the mixing layer, the In-O bonds within the IGZO layer were enhanced at higher Ta (Figure 2a–c). This distinction can be understood in terms of the dual role of Ta in the atomic structures. The annealing of amorphous semi-conductive oxides (i.e., heat treatment at temperatures below the crystallization temperature) is generally considered a defect in the annihilation process. Under these circumstances, more point defects will be annealed out at elevated temperatures due to their enhanced atomic mobility [34,35] or the combination with ambient gas [6,36]. As a result, the electrical stabilities of the oxides were improved. Nevertheless, some experimental evidence shows that semi-conductive oxides become electrically unstable with increasing ambient temperatures [37,38,39]. These abnormal phenomena revealed that a defect generation process is also involved in the annealing process, which would compete with the annihilation process and lead to an increase in atomic defects. In our case, the In-O bonds in the interfacial mixing layer were weaker than those in the IGZO layer, and thus they would be more easily broken by thermal vibration at higher Ta. Thus, at higher Ta, defect generation arising from breaking chemical bonds may overwhelm defect annihilation due to enhanced atomic mobility, leading to weakened In-O bonds in the interfacial mixing layer.
There was one more component centered at 152.65 ± 0.15 eV in the spectra in the range of 150~170 eV (Figure 3a), which pointed to the Si2s component [24]. The binding energy of this component for the interfacial mixing layer (Table 2) was smaller than that for the SiO2 layer (as shown in Figure 4a and Table 3), indicating that at the initial growth of IGZO, ion bombardment led to structural damages (for instance, dangling bonds and weak bonds). Although BE of Si2s component for the interfacial layer increased at higher Ta, it was still smaller than that for the SiO2 layer. These phenomena suggest that although the structural damages at interface resulting from ion bombardment were reduced at higher Ta, they were unable to be totally annihilated.
In Figure 3d, the O1s spectra at both Ta were asymmetric with a sub-component on the high-BE side. As mentioned above, the sub-component on the high-BE side arises from O-related defects (for example, hydroxyls, water molecules, and organic contaminants). At higher Ta, the intensity of the sub-component increased. The curve-fitting analysis also showed that the area ratio of the sub-component (AOII%) increased at higher Ta. Both direct observation and indirect analysis showed that higher Ta resulted in more O-related defects in the interfacial mixing layer. Similarly, it has been reported that with an increasing annealing temperature of IGZO, more water molecules were distributed at deeper depths [16,40].

3.1.3. SiO2 Layer

The atomic structures of the SiO2 layer annealed at different Ta were further studied. Figure 4 presents the Si2s and O1s spectra collected from the SiO2 layer. At higher Ta, either the Si2p or O1s component shifted towards the high-BE side, indicating stronger Si-O bonds.
It should be noted that the BE values of the Si2s component for our SiO2 films were lower than those for the SiO2 bulk (154.7 ± 0.1 eV) [24]. This result was attributed to the atomic disordering within films arising from a far-from-equilibrium sputtering condition.
The above experimental results show the effects of Ta on IGZO/SiO2 structures and the electrical stabilities of IGZO TFTs. The structural results can be summarized as follows: (1) higher Ta resulted in stronger chemical bonds within the IGZO layer and SiO2 layers; (2) higher Ta had complex effects on the atomic structure of the IGZO/SiO2 interfacial mixing layer: stronger Si-O bonds, weaker M-O bonds, and more O-related defects.

3.2. SEM Characterization

Figure 5 displays the surface morphology of IGZO layers annealed at different Ta. IGZO layers annealed at both Ta were columnar structures and their columnar widths were comparable (35 ± 5 nm). This result suggests that annealing temperatures over 300~400 °C had no effect on the surface morphology of IGZO layers.

3.3. Bias Stress Stabilities

3.3.1. Transfer Characteristics

The transfer characteristics of as-fabricated TFTs with IGZO annealed at different Ta were compared (see the green curves in Figure 6). First, at higher Ta, the transfer curves shifted negatively, indicating a negative shift in the threshold voltage (Vth). Actually, many researchers have observed more negative Vth for as-fabricated TFTs with IGZO annealed at higher temperatures [6,9,11,12,14,41]. Such a negatively shifted Vth at higher Ta was related to the decreased resistance of our IGZO films (R). The R-value of the IGZO annealed at 400 °C (4.1 × 105 Ω) was at least two orders of magnitude less than that of the IGZO annealed at 300 °C (>4 × 107 Ω). The decreased resistance was attributed to the increased carrier concentration because the saturation mobilities of our TFTs with IGZO annealed at different Ta were similar (as listed in Table 4). Second, the slope in the linear region of the transfer curves in the higher-Ta case increased, which suggests a lower subthreshold swing (SS). As suggested for amorphous silicon thin-film transistors, the interfacial trap density (NSSMax) can be estimated from SS by the following equation:
N S S M a x = ( S S l o g ( e ) k T / q − 1 ) C o x q
where k is the Boltzmann constant, q is the electron charge, T is the temperature, and Cox is the insulator capacitance per unit area [42,43]. Given the fact that the Cox of our SiO2 dielectric was 2.4 × 10−8 F/cm2, the NssMax of our TFTs decreased from 1~2 × 1012/cm2 to ~8 × 1011/cm2 when Ta increased from 300 °C to 400 °C.

3.3.2. Positive Bias Temperature Stress (PBTS) Stabilities

PBTS stabilities of TFTs with IGZO annealed at 300 °C to 400 °C were further studied. The TFT with IGZO annealed at 300 °C exhibited a positive Vth shift (+1.3 V) without any change in SS after 1h PBTS, and then turned out to be stable after 2 h or 3 h of PBTS (Figure 6a). The amplitude of such a ΔVth was smaller than those of the reported oxide TFTs under the same PBTS conditions (Table 5). The positively shifted Vth under PBTS is primarily attributed to the electron trapping near or at the semiconductor/insulator (S/I) interface, without generating a new state [17,18,19]. However, neither position nor shape was varied after PBTS for the TFT with IGZO annealed at 400 °C (Figure 6c), indicating improved PBTS stabilities. Given the fact that the carrier concentration increased at higher T (as discussed in Section 3.3.1), the increased PBTS stabilities correlated with the reduced interface trap (as evident by the smaller SS), which lessened the effects of electron trapping near or at the IGZO/SiO2 interface.
As revealed by XPS analysis, the improved structural features near/at the IGZO/SiO2 interface involved stronger Si-O bonds in the interfacial mixing layer. Cho et al. observed that oxide TFT, with stronger Si-O bonds on the insulation surface, exhibited smaller ΔVth under PBTS [44]. In this sense, the reduced interfacial traps, resulting in the enhanced PBTS stabilities at higher Ta, may be due to the strengthened Si-O bonds near/at the interface.

3.3.3. Negative Bias Temperature Stress (NBTS) Stabilities

The effects of Ta on NBTS stabilities were somewhat different from those on PBTS stabilities. The TFT with IGZO annealed at 300 °C showed a negative Vth shift (−2.0 V) after 1 h NBTS and became stable after 2 h or 3 h of NBTS (Figure 6b). The amplitude of this negative ΔVth was in the range of the reported values for oxide TFTs under the same NBTS conditions. However, the TFT with IGZO annealed at 400 °C presented a continuous negative Vth shift during NBTS, resulting in a larger Vth shift (−4.5 V) after 3 h of NBTS (Figure 6d). In other words, higher Ta slightly increased the NBTS instabilities. Similarly, Chen et al. reported that higher a post-annealing temperature resulted in increased negative bias stress instabilities [10]. Three mechanisms for instabilities under negative bias stress have been proposed: hole trapping at the S/I interface [5], defect generation in active layers [18,19], and electron de-trapping at the S/I interface [17,20]. The first mechanism was not considered because the number of holes in n-type semiconductors was negligible. The second mechanism was unable to explain our experimental results since (i) the defect state in the IGZO would result in degradation in SS and μ, rather than the almost unvaried SS and slightly increased μ (Table 4), and (ii) the XPS results revealed that no extra structural defects were introduced into the IGZO layer at higher Ta (see in Section 3.1.1). Therefore, our increased NBTS instabilities at higher Ta were mainly attributed to the enhanced electron de-trapping near or at the S/I interface. Under negative bias stress, the interfacial donor-like defects released electrons towards the IGZO layer and turned out to be positively charged. The released electrons would be trapped within the IGZO layer and thus are not recovered instantly. In the following bias sweeping, the positively charged donor-like defects and trapped electrons formed a residual field, leading to enhanced electron accumulation in the front channel, which, in turn, resulted in a negative ΔVth.
Our XPS analysis showed that the increased interfacial defects at higher Ta include weakened M-O bonds and increased O-related defects (e.g., water molecules and hydroxyls). Much experimental evidence has shown that the weakened M-O bonds and water molecules were donor-like in nature, which enables the release of electrons and results in a larger Vth shift under negative bias stress [29,45,46]. Therefore, the increased NBTS instabilities can be attributed to the weakened M-O bonds and increased water molecules in the IGZO/SiO2 interfacial mixing layer.
Table 5. Reference data for the bias temperature stabilities of oxide TFTs. BG and TG represent bottom-gate and top-gate configurations.
Table 5. Reference data for the bias temperature stabilities of oxide TFTs. BG and TG represent bottom-gate and top-gate configurations.
ConfigurationActive LayerVGS (V)Temp (°C)Time (s)ΔVth (V)Reference
Coplanar_BGIGZO+206030002.5[47]
Staggered_BGIGZO+206036000.5[48]
Staggered_BGIGZTO+206072001.8[49]
Staggered_BGIZO+206072003.0[50]
Staggered_BGIZO:Pr+206072002.0[50]
Coplanar_BGIGZO+206010,8001.3This work
Staggered_BGSZTO−20603600−2[51]
Staggered_BGSZTO−20603600−2.73[52]
Staggered_BGIGZO−20603600−0.5[48]
Staggered_BGIGZTO−206072000.5[49]
Staggered_BGIZO−20607200−0.8[50]
Staggered_BGIZO:Pr−20607200−0.71[50]
Staggered_BGIZO−206010,800−3.5[53]
Staggered_BGHIZO−206010,800−3~−1[54]
Coplanar_BGIGZO−206010,800−2This work

4. Discussions

The above experimental results showed that the structural quality of the IGZO/SiO2 interfacial mixing layer was the key structural factor for the electrical stabilities of bottom-gate coplanar IGZO TFTs. In this part, we discuss how the processing conditions affect this key factor in order to propose the main points for preparing electrically stable semi-conductive devices.
For bottom-gate coplanar TFTs, structural imperfections forming from the insulation surface are inevitable during the preparation of source/drain electrodes and the active layer [43,55,56]. To enhance the performance of devices, post-heat treatment (for example, by adjusting Ta) is necessary to reduce these structural defects. Therefore, the structural quality of the oxide/insulator interfacial mixing layer depends on the competition between defect generation from ion bombardment and defect annihilation through heat treatment.
Our study, as well as other reported results [10,13,14,57], showed that unlimited enhancement in post-heat treatment by increasing Ta would result in negative effects on oxide TFTs (such as degraded transfer characteristics and electrical stabilities). Seen in this light, higher Ta would play a negative role in defect generation, rather than the generally considered positive role in defect annihilation, when Ta was increased up to a certain degree. In this work, XPS analysis (as schematically drawn in Figure 7) revealed that at higher Ta, although the damaged Si-O bonds were partially annihilated, the weak M-O bonds were easily broken due to thermal vibration. Moreover, more undesired molecules (e.g., water molecules) from the ambient atmosphere were introduced into the interfacial mixing layer at higher Ta because of the enhanced diffusion length. As a result, the electrical stabilities of IGZO TFTs were not comprehensively improved, i.e., enhanced PBTS stabilities but degraded NBTS stabilities. Thus, unlimitedly enhancing annealing temperatures may not be an effective way to improve the structural quality of the interfacial layer. In this regard, controlling defect generation is more important to achieving a high-quality interfacial layer. To control defect generation during the sputtering of oxides, a mild sputtering condition of source/drain electrodes and oxides or a bombardment-resistant insulation surface (through densifying the film structure) may be required.

5. Conclusions

In conclusion, the effects of annealing temperatures (Ta) on the IGZO/SiO2 film structure and electrical stabilities of bottom-gate coplanar IGZO TFTs were investigated to build a process–structure–property holistic link. The XPS results presented a three-layer structure of IGZO/SiO2: a uniform IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had complex effects on the structure of the interfacial mixing layer, though it only resulted in stronger chemical bonds within the IGZO and SiO2 layers. Particularly, although the damaged Si-O bonds within the interfacial mixing layer were improved at high Ta, the weak M-O bonds (M points to the metallic atoms in IGZO) were thermally disturbed. Additionally, the undesired O-related molecules (e.g., water molecules) were introduced into the interfacial mixing layer. The IGZO TFTs with IGZO annealed at higher Ta exhibited enhanced positive bias temperature stress (PBTS) stabilities but degraded negative bias temperature (NBTS) stabilities. The enhanced PBTS stabilities were attributed to the reduced electron traps due to the stronger Si-O bonds near the IGZO/SiO2 interfacial mixing layer. The decreased NBTS stabilities were ascribed to the increased electron de-trapping arising from the donor-like defects within the interfacial mixing layer (such as weaker M-O bonds and increased O-related defects). Our results indicate that to achieve enhanced comprehensive performance of IGZO TFTs, controlling defect generation (e.g., by using a mild growth condition of source/drain electrodes and oxides or densifying the SiO2 layer) may be more significant than enhancing defect annihilation (e.g., by increasing Ta).

Author Contributions

Conceptualization, Y.C. (Yuyun Chen), Y.S., Y.L. and R.H.; Methodology, Y.C. (Yuyun Chen), Y.C. (Yuanming Chen), G.X., Y.L. and R.H.; Validation, G.X.; Formal analysis, Y.C. (Yuyun Chen), Y.S., Y.C. (Yuanming Chen), G.X. and R.H.; Investigation, Y.C. (Yuyun Chen), Y.C. (Yuanming Chen), G.X. and Y.L.; Data curation, Y.C. (Yuyun Chen), Y.C. (Yuanming Chen) and G.X.; Writing—original draft, Y.C. (Yuyun Chen); Writing—review & editing, Y.C. (Yuyun Chen), Y.S. and R.H.; Supervision, Y.S.; Funding acquisition, Y.L. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the Guangdong Provincial Science and Technology Innovation Strategy Special Project (City and County Science and Technology Innovation Support Project) [grant number STKJ2023053].

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are contained within the article.

Acknowledgments

The authors acknowledge the support from the Guangdong Technion Israel Institute of Technology.

Conflicts of Interest

Yuyun Chen, Yi Shen, Yuanming Chen, Guodong Xu, and Yudong Liu were employed by the company Shantou Goworld Display Technology Co., Ltd. Rui Huang declares that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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Coatings 14 00555 g001
Figure 1. In-depth photoelectron spectra in the range of 150~170 eV for IGZO/SiO2 samples annealed at 300 °C (a) and 400 °C (b).
Figure 1. In-depth photoelectron spectra in the range of 150~170 eV for IGZO/SiO2 samples annealed at 300 °C (a) and 400 °C (b).
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Figure 2. (a) Ga3s, (b) Zn2p, (c) In3d, and (d) O1s spectra of the IGZO layer annealed at 300 °C and 400 °C. The spectra were collected at a depth of 5 nm from IGZO surface.
Figure 2. (a) Ga3s, (b) Zn2p, (c) In3d, and (d) O1s spectra of the IGZO layer annealed at 300 °C and 400 °C. The spectra were collected at a depth of 5 nm from IGZO surface.
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Figure 3. (a) Ga3s and Si2s, (b) Zn2p, (c) In3d, and (d) O1s spectra taken from IGZO-SiO2 interfacial mixing layer annealed at 300 °C and 400 °C.
Figure 3. (a) Ga3s and Si2s, (b) Zn2p, (c) In3d, and (d) O1s spectra taken from IGZO-SiO2 interfacial mixing layer annealed at 300 °C and 400 °C.
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Figure 4. (a) Si2s and (b) O1s spectra of SiO2 layer annealed at 300 °C and 400 °C.
Figure 4. (a) Si2s and (b) O1s spectra of SiO2 layer annealed at 300 °C and 400 °C.
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Figure 5. Surface morphology of IGZO annealed at (a) 300 °C and (b) 400 °C.
Figure 5. Surface morphology of IGZO annealed at (a) 300 °C and (b) 400 °C.
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Figure 6. Transfer characteristic curves of the TFTs with IGZO annealed at 300 °C and 400 °C during 3h positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) (a–d).
Figure 6. Transfer characteristic curves of the TFTs with IGZO annealed at 300 °C and 400 °C during 3h positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) (a–d).
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Figure 7. Schematic drawing of dual effects of higher Ta on structure of IGZO-SiO2 mixing layer: enhanced Si-O bonds, weaker M-O bonds, and more H2O molecules.
Figure 7. Schematic drawing of dual effects of higher Ta on structure of IGZO-SiO2 mixing layer: enhanced Si-O bonds, weaker M-O bonds, and more H2O molecules.
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Table 1. Parameters extracted by fitting the core-level spectra in Figure 2.
Table 1. Parameters extracted by fitting the core-level spectra in Figure 2.
Ta (°C)Ga3sZn2pIn3dO1s
Position (eV)FWHM (eV)Position (eV)FWHM (eV)Position (eV)FWHM (eV)AOII (%)
300160.93.31022.02.2444.92.021
400161.23.31022.32.2445.22.021
Table 2. Parameters extracted by fitting the core-level spectra in Figure 3.
Table 2. Parameters extracted by fitting the core-level spectra in Figure 3.
Ta (°C)Ga3sZn2pIn3dSi2sO1s
Position (eV)FWHM (eV)Position (eV)FWHM (eV)Position (eV)FWHM (eV)Position (eV)FWHM (eV)AOII%(%)
300159.912.81021.382.5444.132.4152.53.120
400159.893.01021.352.5444.022.5152.83.124
Table 3. Parameters extracted by fitting the core-level spectra in Figure 4.
Table 3. Parameters extracted by fitting the core-level spectra in Figure 4.
Ta (°C)Si2sO1s
Position (eV)FWHM (eV)Position (eV)FWHM (eV)
300153.23.2531.52.3
400153.33.1531.62.4
Table 4. The electrical parameters (including mobility μ, subthreshold swing SS, Ion and Ioff ratio Ion/Ioff, threshold voltage Vth, and Vth shift ΔVth) extracted from the transfer curves in Figure 5.
Table 4. The electrical parameters (including mobility μ, subthreshold swing SS, Ion and Ioff ratio Ion/Ioff, threshold voltage Vth, and Vth shift ΔVth) extracted from the transfer curves in Figure 5.
Ta (°C)Stateμ (cm2/Vs)SS (V/dec)Ion/IoffVth (V)ΔVth (V)
300As-fabricated950.777.6 × 1061.7+1.5
3h PBTS1030.722.5 × 1063.2
400As-fabricated930.443.7 × 107−3.20.0
3h PBTS1050.444.2 × 107−3.2
300As-fabricated1030.578.4 × 1061.3−1.9
3h NBTS1240.635.6 × 107−0.6
400As-fabricated950.406.0 × 107−2.5−4.5
3h NBTS1020.543.0 × 107−7.0
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MDPI and ACS Style

Chen, Y.; Shen, Y.; Chen, Y.; Xu, G.; Liu, Y.; Huang, R. Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors. Coatings 2024, 14, 555. https://doi.org/10.3390/coatings14050555

AMA Style

Chen Y, Shen Y, Chen Y, Xu G, Liu Y, Huang R. Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors. Coatings. 2024; 14(5):555. https://doi.org/10.3390/coatings14050555

Chicago/Turabian Style

Chen, Yuyun, Yi Shen, Yuanming Chen, Guodong Xu, Yudong Liu, and Rui Huang. 2024. "Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors" Coatings 14, no. 5: 555. https://doi.org/10.3390/coatings14050555

APA Style

Chen, Y., Shen, Y., Chen, Y., Xu, G., Liu, Y., & Huang, R. (2024). Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors. Coatings, 14(5), 555. https://doi.org/10.3390/coatings14050555

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