1. Introduction
Fractional calculus is a branch of mathematical analysis which forms a more general description of the conventional integer-order calculus. As it is well known, integer-order calculus deals with differentiation that, given a function
, is described by the expression
, where
is an integer number
. In fractional calculus, the same expression describes the differentiation, yet the order is now a real
number, leading to a wider range of values. The idea of fractional derivative dates back to the end of the 17-th century; it is not until the past few decades, however, when fractional calculus started being used for a variety of scientific problems and applications. The cause of its increasing application is that, as mentioned above, it forms a generalization of the traditional calculus, and thus describes more real problems with higher accuracy [
1,
2,
3,
4]. One of the most popular methods, that makes the analysis of a real system easier, is the Laplace transform. This is an efficient way to describe and solve equations in frequency domain with simple calculations and without transformations to time domain during the process. The Laplace transform of the derivative of a function,
, in the fractional domain is:
for zero initial conditions [
1]. Employing this definition, the impedance in the fractional-domain has the general form:
where the variable
a represents the order of the element. For
the element is called fractional-order capacitor, or sometimes Constant Phase Element (CPE), with
being the pseudo-capacitance in Farad/sec
1−. In the case that
the expression in (
1) represents a fractional-order inductor with
being the pseudo-inductance in Henry/sec
1−. When
, the element is a resistor, capacitor, and inductor, respectively.
Fractional-order modeling considers the effects of the long-term memory, and due to the offered extra degrees of freedom, it is suitable for modeling, analyzing, and synthesizing electrical, chemical, and biological systems [
5,
6,
7,
8,
9,
10,
11,
12]. In particular, circuit emulators of individual parts of the human body and even the complete human body play an important role for fast and accurate diagnosis of different diseases and morphological changes arising from environmental impacts such as long time exposure to pollution and contamination. For example, the complete human body impedance model studied in [
13,
14] offers circuits more accurate than the international IEC 60990 safety standard. It is impossible to test the safety of any designed instrument on real humans and therefore, tests are conducted on circuit models. In a similar manner, circuit models for specific human organs have been widely proposed and used to characterize changes that occur in these organs as a result of diseases, pollution or other types of damages. In this regards, the clear relationship between fractional-order models and fractal geometry has already been highlighted in different articles (see for example [
15]). Fractal geometry is especially visible in the tissue structure of the lungs [
16]. However, the large variations in the circuit model parameters from one human to the other require developing electronically-adjustable circuits that can be re-configured easily to reflect these changes and allow future integration in smart point of care bio-medical devices (see [
17]).
Lungs are located in the chest on either side of the heart in the rib cage. Their purpose is to provide oxygen to the blood [
18]. Their shape is conical with a narrow rounded apex at the top, and a broad concave base that rests on the convex surface of the diaphragm. Due to the presence of the heart, the left lung is slightly smaller than the right. Lungs are part of the lower respiratory track beginning from trachea and followed by bronchi and bronchioles. The bronchial tree is a series of passages that supplies air to the alveoli of the lungs. It begins with the trachea, which divides into a left and right bronchus. Broncholies are divided into alveolar ducts that create the alveolar sacs, which contains the alveoli, where gas exchanging happens [
19]. Oxygen breathed in and carbon dioxide breathed out. Due to its airway’s branches self similarities (fractal geometry), lungs are a great candidate for the application of fractional-order calculus theory [
20,
21,
22,
23,
24,
25,
26]. At a low frequency range inheritance is insignificant, so each airway can be modeled by a gamma cell resistance and capacitance. In biology, when a circuit shares the same impedance with a tissue in a specific frequency range, then it is called equivalent circuit. Although the model that is used to characterize viscoelastic behavior is composed of two resistors and one capacitor, in the case of lungs the electrical equivalent impedance of each airway is considered to be consisted of one resistor and one capacitor [
27]. Theoretically, the air flow will be the electric current and the air pressure will be the voltage, respectively.
Regarding to the above description the electrical equivalent, shown in
Figure 1, consists of a series connection of a passive resistor and a fractional-order capacitor. The equivalent impedance is given by (
2)
with
R being an ohmic resistance,
being the pseudo-capacitance and
being the order of the element [
16].
The (scaled) values of the resistances and pseudo-capacitances, as well as of the order of the fractional-order capacitors, taken from seven subjects in the range [0.9 Hz, 6 Hz] are summarized in
Table 1.
Table 1 of the manuscript shows that the measured circuit parameters for 7 individuals have a variation in pseudo-capacitance of more than 14 times (from 17.5 nFarad/s
0.05 to 238 nFarad/s
0.42). Also, the variation in the dispersion coefficient from 0.6 to nearly double the value at 1.1 indicates the importance of re-configurability of any proposed circuit model in order to reflect the measured values of any particular individual, which is the focus of this work.
Owing to the fact that fractional-order capacitors are not available in the market [
28], their behavior is approximated through the employment of RC networks [
29], or the employment of the gyration techniques implemented using active elements [
10]. The first solution is easily realizable, but it does not offer the capability of programming because the values of all passive elements must be changed, in order to change the characteristics of the element. On the other hand, the second method offers electronic adjustment of the characteristics of the element, but this is achieved at the expense of circuit complexity and active component count. The contribution, made in this work, is that a novel solution for implementing emulators of fractional-order capacitors with order in the range (0, 2), which offers significant reduction of the spread of time-constants and scaling factors with regards to the straightforward implementation [
30], is presented. This also leads to a significant reduction of the total capacitance area and the total power dissipation. All the above have been achieved keeping: (a) the fully electronic adjustment of the characteristics of the capacitor, including its value as well as its order, and (b) the capability of emulating fractional-order capacitors with order greater than one by the same core.
The paper is organized as follows: the procedure for emulating the behavior of the fractional-order capacitors is presented in
Section 2, while the circuit implementation of the proposed scheme is given in
Section 3. The performance of the intermediate stages and of the whole system are evaluated at post-layout level in
Section 4, using the Cadence IC design suite and MOS transistor models provided by the Austria Mikro Systeme (AMS) 0.35
m CMOS process.
2. Emulation of Fractional-Order Capacitors
According to [
30], the emulation of a fractional-order capacitor is preformed through the utilization of the Functional Block Diagram (FBD) depicted in
Figure 2. The equivalent impedance is given by the expression in (
3)
with
being the transconductance parameter of the voltage-to-current (
) converter,
being a time-constant associated to the unity-gain frequency (
) of the differentiator according to the formula:
, and
being the order of the differentiator. The value of the emulated pseudo-capacitance has the form of (
4)
Due to the restriction on the values range of the variable
q, only the cases #1 to #6 (i.e.,
) are implementable. The last case in
Table 1, where the order of the fractional-order capacitor is greater than one (i.e.,
), cannot be emulated by the present form of the FBD in
Figure 2. In order to overcome this obstacle, the modified FBD in
Figure 3 will be utilized, using an extra integer-order differentiator stage between the fractional-order differentiator and the
converter and, thus,
[
31].
As the equivalent in
Figure 1 is valid over the frequency range
f = [0.9 Hz, 6 Hz], an appropriate selection of unity-gain frequency of the differentiator (
) could be 2.5 Hz. The values of the pseudo-capacitance and the order
of the fractional-order elements, along with the values of the order
q of the fractional-order differentiator and the transconductance
of the FBD in
Figure 3, for the seven cases of emulation are summarized in
Table 2.
Taking also into account the results provided in [
32], the 2nd-order Continued Fraction Expansion (CFE) approximation will be utilized for approximating the behavior of the fractional-order differentiator with an error less than 5% in the frequency range of interest. The resulted rational transfer function has the form
where in (
5) the coefficients
and
are positive real numbers provided in [
33].
The implementation of (
5) can be performed using the multi-feedback Inverse-Follow-the-Leader- Feedback (IFLF) structure demonstrated in
Figure 4, where the realized transfer function is
The values of scaling factors
and time-constants
are calculated by equating the coefficients of the numerator and denominator of (
5) and (
6) [
10]. The resulted values are summarized in
Table 3. Considering the spread (i.e., the ratio of the maximum and minimum value) of both scaling factors and time-constants, it is derived that the spread of scaling factors for all possible cases is equal to 12, 174, while for the time-constants the corresponding value is 388. Taking into account that in the case of employing OTAs these scaling factors will be controlled by dc currents, it is readily obtained that an extremely wide range of bias currents is required towards this goal.
Another possible solution for overcoming this practical problem is the utilization of the Partial Fraction Expansion (PFE) method introduced in [
34]. According to this, the transfer function in (
5) can be decomposed in the form of (
7)
where
are the residues of (
5),
are the poles of (
5) and
.
The expression in (
7) can be alternatively written as
where
and
. The implementation of (
8) can be performed by the functional block diagram given in
Figure 5. Using (
5), (
7) and (
8), the resulted values of times constants are summarized in
Table 4. The spread of scaling factors is now significantly reduced into the value 884 and the spread of time-constants is now equal to 362, more or less the same as in the previous case. Therefore, the PFE approximation tool is preferable than the CFE tool with regards to reduction of the spread of scaling factors.
3. Circuit Implementation
In order to approximate the fractional-order differentiator stage, which is required in the functional block diagram in
Figure 3, the OTA-C topology depicted in
Figure 6 will be utilized. This topology implements the transfer function in (
8); the values of scaling factors, provided in
Table 4, are performed through an appropriate scaling of the corresponding transconductances and, also, their signs are implemented through an appropriate configuration of the input terminals of the corresponding OTAs. The realized time-constants are given by the general expression in (
9)
with
and
being the transconductance of the OTAs and the capacitance associated to the
jth- integration stage.
The integer-order differentiator is implemented by the topology demonstrated in
Figure 7 [
35], and the realized transfer function is given by (
10)
The
conversion stage is implemented by the multiple-output OTA configuration depicted in
Figure 8, with the conversion gain being equal to
.
In order to implement the whole model, which is provided in
Figure 1, a floating resistor emulator is also required. This is realized by the topology, given in
Figure 9, where the realized resistance is
.
A possible OTA topology, in order to implement the topologies in
Figure 6,
Figure 7,
Figure 8 and
Figure 9, is that presented in
Figure 10, which is capable of handling input voltages with maximum amplitude 50 mV, with a total harmonic distortion less than 1% [
36]. Considering MOS transistors biased in the sub-threshold region, the realized transconductance is
with
being the bias current,
being the sub-threshold slope factor, and
(≃26 mV at 27
C) being the thermal voltage. Using (
9) and (
11), the resulted expression of the realized time-constants is that given by (
12)
According to (
11) and (
12), the temperature variations affect both the implemented values of transconductance and time-constant due to the dependence of thermal voltage from the temperature. This can be compensated by employing proportional to the absolute temperature (PTAT) dc current sources [
37].
4. Simulation Results
Using the expression in (
12) and considering that
= 5 pF,
= 70 pF, then the calculated values of the dc bias currents, required for realizing the time-constants in
Table 4, are provided in
Table 5. The scaling factors {
} were implemented by multiplying the dc bias current
by these factors, as it is derived from (
11). Using (
10) and (
12), and considering that
= 25 pF, the dc bias current of the OTAs employed for implementing an integer-order differentiator with time-constant 63.69 ms (i.e.,
= 2.5 Hz) was equal to 22.1 pA. In addition, the values of the dc bias currents for implementing the
converter stage and the floating resistors, calculated using (
4), (
11) and
Table 1, are given in
Table 5. The evaluation of the behavior of the proposed lung impedance model will be performed using the Cadence IC design suite and MOS transistor models provided by the Austria Mikro Systeme (AMS) 0.35
m CMOS process. Considering that
= 0.75 V, the MOS transistors aspect ratios of the OTAs used in
Figure 6,
Figure 7 and
Figure 8, selected in such way that all transistors will operate in the sub-threshold region, are provided in
Table 6.
The layout design of the proposed lung impedance emulator is demonstrated in
Figure 11, where the silicon area is 555.35
m × 485.75
m. As a first-step the correct operation of the building blocks of the model in
Figure 1 was verified. The obtained impedance magnitude and phase responses of the CPE emulator are given in
Figure 12. The characteristic values of the gain and phase of the fractional-order differentiator at the center frequency of the approximation (i.e.,
= 2.5 Hz) as well as the values of the implemented resistances of the employed
converter stage in
Figure 8 and resistor emulator in
Figure 9 are summarized in
Table 7, with the corresponding theoretically predicted values (i.e., derived using ideal circuit elements) given in parentheses. The gain and phase of the integer-order differentiator in
Figure 7 at frequency
= 2.5 Hz, which is used in the case #7 for implementing the order
, were 1 and +88.3° with the theoretical values being 1 and +90°, respectively.
The second step is the consideration of the total circuit of the lung impedance emulator in
Figure 11. The obtained impedance magnitude and phase responses are provided in
Figure 13, where the corresponding theoretically predicted plots are given by dashes. The most important performance characteristics are given in
Table 8, along with the theoretical values given between parentheses. Considering the case
R = 6.44 M
,
= 238 nF/s
and
= 0.5808, the derived statistical plots about the magnitude and phase of the impedance at the center frequency of the approximation (i.e.,
= 2.5 Hz) are provided in
Figure 14.
These results are derived, by employing the Monte-Carlo analysis offered by the Analog Design Environment of the Cadence IC design suite, for a number of runs and considering variations of the channel width and length, gate oxide thickness, threshold voltage, carrier mobility, and substrate and channel doping concentration. The values of standard deviation were 0.09 M and , with the nominal values being 6.89 M and , confirming that the proposed structure has reasonable sensitivity characteristics.
It must be mentioned at this point that, in the simulations, the tuning operation is performed by altering the bias current of the transconductors. In the case of a practical implementation with large number of circuit elements, this can be performed by using an appropriate digital circuitry as in [
38,
39,
40] or using an auxiliary analog system as that proposed in [
41].