Journal of Low Power Electronics and Applications

2212 KiB

Open AccessArticle

Untrimmed Low-Power Thermal Sensor for SoC in 22 nm Digital Fabrication Technology

by Ro'ee Eitan and Ariel Cohen

J. Low Power Electron. Appl. 2014, 4(4), 304-316; https://doi.org/10.3390/jlpea4040304 - 9 Dec 2014

Cited by 3 | Viewed by 8345

Thermal sensors (TS) are essential for achieving optimized performance and reliability in the era of nanoscale microprocessor and system on chip (SoC). Compiling with the low-power and small die area of the mobile computing, the presented TS supports a wide range of sampling frequencies with an optimized power envelope. The TS supports up to 45 K samples/s, low average power consumption, as low as 20 μW, and small core Si area of 0.013 mm². Advanced circuit techniques are used in order to overcome process variability, ensuring inaccuracy lower than ±2 °C without any calibration. All this makes the presented thermal sensor a cost-effective, low-power solution for 22 nm nanoscale digital process technology. Full article

(This article belongs to the Special Issue Low Power Sensors: Technology, Circuit Interfaces, Systems and Applications)

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526 KiB

Open AccessArticle

Ultra-Low Voltage Sixth-Order Low Pass Filter for Sensing the T-Wave Signal in ECGs

by Panagiotis Bertsias and Costas Psychalinos

J. Low Power Electron. Appl. 2014, 4(4), 292-303; https://doi.org/10.3390/jlpea4040292 - 26 Nov 2014

Cited by 5 | Viewed by 8306

Abstract

An ultra-low voltage sixth-order low pass filter topology, suitable for sensing the T-wave signal in an electrocardiogram (ECG), is presented in this paper. This is realized using a cascade connection of second-order building blocks constructed from a sinh-domain two-integrator loop. The performance of the filter has been evaluated using the Cadence Analog Design Environment and the design kit provided by the Austria Mikro Systeme (AMS) 0.35-µm CMOS process. The power consumption of filters was 7.21 nW, while a total harmonic distortion (THD) level of 4% was observed for an input signal of 220 pA. The RMS value of the input referred noise was 0.43 pA, and the simulated value of the dynamic range (DR) was 51.1 dB. A comparison with already published counterparts shows that the proposed topology offers the benefits of 0.5-V supply voltage operation and significantly improved power efficiency. Full article

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835 KiB

Open AccessReview

A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

by Eric Bharucha, Hassan Sepehrian and Benoit Gosselin

J. Low Power Electron. Appl. 2014, 4(4), 268-291; https://doi.org/10.3390/jlpea4040268 - 14 Nov 2014

Cited by 33 | Viewed by 11883

Abstract

When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics. Full article

(This article belongs to the Special Issue Low-Power Biomedical Applications)

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J. Low Power Electron. Appl., Volume 4, Issue 4 (December 2014) – 3 articles , Pages 268-316

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