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Peer-Review Record

DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Electronics 2022, 11(1), 122; https://doi.org/10.3390/electronics11010122
by Jiemin Li 1,2,3,*, Shancong Zhang 1,2 and Chong Bao 1,2
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Electronics 2022, 11(1), 122; https://doi.org/10.3390/electronics11010122
Submission received: 31 October 2021 / Revised: 19 December 2021 / Accepted: 22 December 2021 / Published: 30 December 2021

Round 1

Reviewer 1 Report

  1. line 210 : Referred as “classic SECDED” seems to be 32-bit Hamming codes. And also proposed models make syndrome and calculate SECDED as Hamming code. Just change the location of parity reduces 15 operations? Except the change of parity bit what is improved?
  2. As FPGA, Software verification test conducted, more results figures are required( ex, oscilloscoper wave)
  3. As you use improved SECDED to reduce resource of architecture, there is no resource results of proposed model, you need more date for CORE synthesized, and compare with other cores with ECC.
  4. We understand that integrity of data, and reliability of process improved as pipeline rollback architecture, but it seems not a little work will be loaded to single core architecture, and core. However There is no result data of core performance(speed).
  5. In using microcontroller power consumption is not irresistible. You added lots of modules to basic core, and it leads to increases of power consumption. If available, add of power consumption information will increase persuasive power of your proposal
  6. As using Pipeline, During repeating in one stage, all other stages are temporarily pushed back or waiting, but there is no mention of this.
  7. The design of the ARBIT module that controls the pipeline seems to be the most important. There is no design method or rationale for
  8. There should be more details about the ASIC technology used for synthesis in the Experiment section. What is the process node?
  9. In Figure 26, The processor response according to the Error injection rate is the same, but it is necessary to mention this.
  10. Overall figures need to be improved quality.

Author Response

"Please see the attachment."

Author Response File: Author Response.pdf

Reviewer 2 Report

The work submitted for publication addresses the solution to a problem of great interest in the space sector. The correction of CPU errors caused by SEUs has been addressed in previous works, but the idea raised in this paper is of great interest.

One of the problems detected in the paper is the sloppiness in the presentation of the work. There are many typographical and grammatical errors, lack of uniformity and lack of in-house review prior to submission.

The introduction and design proposal sections are well presented, but the same is not true for the implementation and verification sections. The implementation section is very terse and lacking in detail. The verification and testing section lacks the canonical scenarios that allow verifying the correction of each of the errors that may occur, as well as the possible combinations between them. 

A PDF file with annotations is included to assist authors in their review. 

Comments for author File: Comments.pdf

Author Response

Response to Reviewer 2 Comments

Dear reviewer, I would like to express my heartfelt thanks. I am deeply moved by your meticulous and patience.  It's my honor to receive your advice on my English paper. This also makes me grateful for my first time on English thesis writing. The following points are my modifications and replies to your suggestions.

 

Point 1: The work submitted for publication addresses the solution to a problem of great interest in the space sector. The correction of CPU errors caused by SEUs has been addressed in previous works, but the idea raised in this paper is of great interest.


 

Response 1: Please provide your response for Point 1. (in red)

Thank you for your suggestions and interest in this work. This revision is mainly divided into two parts. One is the adjustment of English grammar and structure. On the other hand, a large number of data and pictures are added for the implementation and verification later in this paper.

 

Point 2: One of the problems detected in the paper is the sloppiness in the presentation of the work. There are many typographical and grammatical errors, lack of uniformity and lack of in-house review prior to submission.

 

Response 2: Please provide your response for Point 2. (in red)

First of all, in view of the English grammar and structure problems mentioned in this paper, I completed all the changes according to the suggestions of you. Because this problem is trivial, I adopted the revision mode in the manuscript submitted. On the other hand, I unified the use of relevant nouns in the article, such as rollback, Figure, SECDED code, etc. The use of fonts for special text has also been modified. Some inappropriate statements have also been changed. According to your suggestion, our group conducted an internal review. At the same time, we adjusted the narrative ways of section 4 and section 5. The original narration of these two paragraphs lacks logic and correspondence in structure. We consciously added summary sentences in section 4 and section 5 to make the test methods correspond to the test results.

 

Point 3: The introduction and design proposal sections are well presented, but the same is not true for the implementation and verification sections. The implementation section is very terse and lacking in detail. The verification and testing section lacks the canonical scenarios that allow verifying the correction of each of the errors that may occur, as well as the possible combinations between them.

 

Response 3: Please provide your response for Point 2. (in red)

I totally agree with you. In fact, I focus on the implementation and verification of this revision. This revision divides the section 4 into functional test and performance test, explains the test principle and process for all aspects, and draws pictures to illustrate, so as to ensure the comprehensiveness of the test and the correspondence between the previous and the following text. In the verification part, the demonstration is given from the aspects of function, performance and power consumption. The function verification adds the situation that the previous test does not cover, and gives the waveform diagram. For the performance verification, it not only gives the curve diagram, but also provides detailed data for demonstration. Moreover, in this verification part, the comparison of resources is added to explain the characteristics of coding, and the evaluation is made from the perspective of synthesis and power consumption, which are ignored but also very important contents in the original paper.

 

Point 4: A PDF file with annotations is included to assist authors in their review.

 

Response 4: Please provide your response for Point 2. (in red)

Thank you again for your PDF document, which enables me to quickly locate my existing problems in a short time. I have carefully revised it this time and hope these problems can be well solved in the manuscript submitted. I also hope you can give some suggestions on some supplements and ideas of the article. Thank you again!

Further detailed changes,Please see the attachment

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments are included in the attached file.

Comments for author File: Comments.pdf

Author Response

    Thanks again for the reviewer's suggestions on my paper. I revised all the questions raised by the teacher.

 "Please see the attachment."

Author Response File: Author Response.pdf

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