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Electronics
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Fault-Tolerant Architectures and Applications for Embedded and Reconfigurable Systems-on-a-Chip
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Fault-Tolerant Architectures and Applications for Embedded and Reconfigurable Systems-on-a-Chip

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (20 November 2021) | Viewed by 10704

Special Issue Editors

Dr. Rui Policarpo Duarte

E-Mail Website
Guest Editor
INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisbon, Portugal
Interests: reconfigurable computing; FPGA architectures and design; fault-tolerant reconfigurable systems; optimization of SoC FPGA design
Special Issues, Collections and Topics in MDPI journals
Dr. Paulo Flores

E-Mail Website
Guest Editor
INESC-ID, Instituto Superior Técnico (ECE Department), University of Lisbon, Lisbon, Portugal
Interests: embedded systems architectures; dedicated and reconfigurable computation (FPGAs); design and optimization of models and algorithms applied to electronic design automation (EDA) problems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

With the increasing dependability of computing system in everyday life, such as in automotive and industrial industries, scientific experiments, and space missions, it is important to have systems that guarantee reliability and are capable of operating, even in harsh conditions, as reliability has a direct impact on a systems’s performance. In some technologies, such as FPGAs and microcontrollers, there is an inherent trade-off in the amount of resources, processing power available, and reliability a system can exhibit. Depending on the technology used, a designer usually adopts different strategies, thus making it hard to determine tolerance to the faults of heterogeneous systems. Moreover, the specificity of most applications makes it difficult to create a system design template that can be reused. Therefore, it is necessary to automate such system design through the proposal of novel methods and tools. Finally, the advancement of technology enables the development of novel applications that require tolerance to faults, but their specificity makes it difficult to adopt traditional fault mitigation techniques. The aim of this Special Issue is to gather the most recent developments and applications of embedded and reconfigurable systems, covering, but not limited to, the following scopes:

  • Applications of fault-tolerance mechanisms in embedded and reconfigurable (SoC-FPGA) systems, e.g., neural networks, edge computing, and automotive and space systems
  • Approximating computing architectures
  • Fault-tolerance methods for heterogeneous systems
  • Communication mechanisms for inter-layer fault-tolerance stack
  • Unified hardware–software fault-tolerance
  • Systems with limited resources: low-power and portable systems
  • Open source implementations
  • EDA tools.

Dr. Rui Policarpo Duarte
Prof. Dr. Paulo Flores
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (3 papers)

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Research

27 pages, 7563 KiB  
Article
DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA
by Jiemin Li, Shancong Zhang and Chong Bao
Electronics 2022, 11(1), 122; https://doi.org/10.3390/electronics11010122 - 30 Dec 2021
Cited by 13 | Viewed by 4285
Abstract
With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a [...] Read more.
With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable. Full article
(This article belongs to the Special Issue Fault-Tolerant Architectures and Applications for Embedded and Reconfigurable Systems-on-a-Chip)
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12 pages, 643 KiB  
Article
Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application
by Laurent Gantel, Quentin Berthet, Emna Amri, Alexandre Karlov and Andres Upegui
Electronics 2021, 10(17), 2148; https://doi.org/10.3390/electronics10172148 - 3 Sep 2021
Cited by 3 | Viewed by 2616
Abstract
With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event [...] Read more.
With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability. Full article
(This article belongs to the Special Issue Fault-Tolerant Architectures and Applications for Embedded and Reconfigurable Systems-on-a-Chip)
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20 pages, 8404 KiB  
Article
Multiple Sensor Fail-Operational Architecture for Electric Vehicle Powertrain Control System
by Yungchen Wang and Rongshun Chen
Electronics 2021, 10(11), 1306; https://doi.org/10.3390/electronics10111306 - 30 May 2021
Viewed by 2703
Abstract
With the expanding demand to meet specific safety requirements, a new definition of the architecture at the system level is required to keep the powertrain system still operational after the fault emerge of some sensors. This work proposes a fail-operational architecture by integrating [...] Read more.
With the expanding demand to meet specific safety requirements, a new definition of the architecture at the system level is required to keep the powertrain system still operational after the fault emerge of some sensors. This work proposes a fail-operational architecture by integrating battery management and motor control system, which implements heterogeneous sensor signal reconstruction and model-based signal estimation for redundant signal generation and adopts random forest for signal arbitration. The proposed architecture can reduce the system failure rate and allow a fault-toleration of up to three sensors at any given time without increasing costs. Finally, the proposed architecture was verified by comparing the fault detection performance among three arbitration algorithms in a model in the loop (MIL) platform. Full article
(This article belongs to the Special Issue Fault-Tolerant Architectures and Applications for Embedded and Reconfigurable Systems-on-a-Chip)
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