Resource- and Power-Efficient High-Performance Object Detection Inference Acceleration Using FPGA

Round 1

Reviewer 1 Report

First, the authors introduce the optimization method of deep neural networks in detail, and thoroughly investigate the optimization method of neural networks.

Besides, the authors carefully introduce the YOLOv2 network and analyze the computation principle of each network layer.

The authors present a resource-efficient yet high-performance object detection inference acceleration with detailed implementation and design choices, which is end-to-end hardware acceleration implementation while maintaining high performance and speed. And, they test their object detection acceleration by implementing YOLOv2 on two FPGA boards and achieve up to 184GOPS with limited resource utilization.

 

 

Author Response

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Reviewer 2 Report

The authors present an interesting and detailed approach to FPGA-based inference acceleration for object detection. The drawings and detailed implementation descriptions are particularly appreciated.

The main drawback of this paper is the lack of objection detection "precision" data for the proposed design, the original YOLOv2, and the other methods used for comparison in Table 5. For the COCO dataset, this could be the Mean Average Precision (MAP) data. This data MUST be included, and the data should show comparable precision results with the 16-bit implementations and better precision results thatn the 1-6 bit and 8 bit implementations.

Other suggested minor improvements include a more thorough review of all previous comparable approaches for the target problem and improvements in the English presentation. A comprehensive review of the state-of-the-art in custom hardware (or FPGA) implementations of object detection (or just YOLO) should be presented. The authors should justify the use of only the 4 references compared in Table 5. The English descriptions could also be improved quite a bit, and care should be taken to correct all English typos and grammatical errors.

Author Response

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Reviewer 3 Report

This work presents a resource-efficient yet high-performance object detection inference acceleration (YOLOv2) on an FPGA. The paper starts with lot of related work as well as a detailed description of YOLOv2 which is followed by an explanation of the author's approach. Compared to a software implementation running on a desktop CPU, the FPGA implementation speeds up the algorithm by up to 28 and 8 times, respectively. The authors also compared their implementation with other FPGA implementations with the author's implementation is most power and resource-efficient. Well done work, for my opinion!

Author Response

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Thank you!

Author Response File: Author Response.docx

Round 2

Reviewer 1 Report

I am satisfied with the authors' effort in improving the paper.

Reviewer 2 Report

The paper is now significantly improved from the previous version.