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Applications of FPGAs and Reconfigurable Computing: Current Trends and Future...
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Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 March 2022) | Viewed by 24615

Special Issue Editor

Prof. Konstantinos Masselos

E-Mail Website
Guest Editor
Department of Informatics and Telecommunications, University of Peloponnese, 221 00 Tripolis, Peloponnese, Greece
Interests: high performance computing systems; high level synthesis; FPGAs and reconfigurable hardware; low power design; integrated circuits; embedded systems

Special Issue Information

Dear Colleagues, 

FPGAs and reconfigurable computing platforms bring significant improvements in implementation efficiency compared to other programmable integrated circuits such as CPUs and GPUs while offering post-fabrication flexibility that is not possible in application-specific integrated circuits (ASICs). Given the fact that conventional von-Neumann architectures suffer from high power densities, power and energy efficiency and cooling become top priorities for scalable high-performance computing. FPGAs allow matching hardware to the application, avoiding overheads, and achieving higher hardware efficiency than other programmable architectures.

Today, FPGAs are heterogeneous systems-on-a-chip (soc) combining reconfigurable fabric with application specific blocks and programmable processors in the form of embedded hard IPs. Given their computational capabilities and energy efficiency, FPGAs are present in most heterogeneous computing systems as accelerators. Applications of FPGAs include accelerators for scientific computing, artificial intelligence/machine learning, embedded systems, real-time systems, digital signal processing, computer vision, computer graphics, hardware emulation, cryptography, and manufacturing systems.

We invite authors from both the academic and industrial communities to contribute original research articles as well as review articles that present applications of FPGAs and other reconfigurable computing architectures in different domains. A simple discussion of applications’ implementations using FPGAs is not considered a sufficient research contribution. Submitted papers should emphasize novel applications/algorithms, novel design techniques/use of architectures, or clearly measured implementation efficiency benefits (especially in comparison to other implementation platforms such as multi-/many core CPUs, GPUs and ASICs).

Relevant topics include but are not limited to:

  1. FPGA acceleration of artificial intelligence, machine learning, deep learning and neural networks;
  2. Applications of FPGAs in cybersecurity;
  3. The role of FPGAs in the cloud and in data centers;
  4. FPGAs in high-performance computing;
  5. FPGAs in edge/fog/IoT and mobile computing;
  6. FPGA acceleration in finance and enterprises (including cryptocurrencies);
  7. FPGAs in networks with emphasis on 5G and software-defined networks;
  8. FPGAs in space and automotive systems;
  9. Trends in education with emphasis on a) the use of FPGAs and FPGA clouds in teaching and research of relevant modules and b) education for FPGAs and reconfigurable computing, including courses, laboratories, teaching experiences;
  10. The FPGA market: current status and future perspectives.

Prof. Konstantinos Masselos
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGA acceleration of artificial intelligence, machine learning, deep learning and neural networks
  • Applications of FPGAs in cybersecurity
  • The role of FPGAs in the cloud and in data centers
  • FPGAs in high-performance computing
  • FPGAs in edge/fog/IoT and mobile computing
  • FPGA acceleration in finance and enterprises (including cryptocurrencies)
  • FPGAs in networks with emphasis on 5G and software-defined networks
  • FPGAs in space and automotive systems
  • Trends in education with emphasis on a) the use of FPGAs and FPGA clouds in teaching and research of relevant modules and b) education for FPGAs and recon-figurable computing, including courses, laboratories, teaching experiences
  • The FPGA market: current status and future perspectives

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Published Papers (7 papers)

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Research

24 pages, 4857 KiB  
Article
Resource- and Power-Efficient High-Performance Object Detection Inference Acceleration Using FPGA
by Solomon Negussie Tesema and El-Bay Bourennane
Electronics 2022, 11(12), 1827; https://doi.org/10.3390/electronics11121827 - 8 Jun 2022
Cited by 1 | Viewed by 2610
Abstract
The success of deep convolutional neural networks in solving age-old computer vision challenges, particularly object detection, came with high requirements in terms of computation capability, energy consumption, and a lack of real-time processing capability. However, FPGA-based inference accelerations have recently been receiving more [...] Read more.
The success of deep convolutional neural networks in solving age-old computer vision challenges, particularly object detection, came with high requirements in terms of computation capability, energy consumption, and a lack of real-time processing capability. However, FPGA-based inference accelerations have recently been receiving more attention from academia and industry due to their high energy efficiency and flexible programmability. This paper presents resource-efficient yet high-performance object detection inference acceleration with detailed implementation and design choices. We tested our object detection acceleration by implementing YOLOv2 on two FPGA boards and achieved up to 184 GOPS with limited resource utilization. Full article
(This article belongs to the Special Issue Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives)
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20 pages, 6841 KiB  
Article
FPGA-Based Reconfigurable Convolutional Neural Network Accelerator Using Sparse and Convolutional Optimization
by Kavitha Malali Vishveshwarappa Gowda, Sowmya Madhavan, Stefano Rinaldi, Parameshachari Bidare Divakarachari and Anitha Atmakur
Electronics 2022, 11(10), 1653; https://doi.org/10.3390/electronics11101653 - 22 May 2022
Cited by 8 | Viewed by 3776
Abstract
Nowadays, the data flow architecture is considered as a general solution for the acceleration of a deep neural network (DNN) because of its higher parallelism. However, the conventional DNN accelerator offers only a restricted flexibility for diverse network models. In order to overcome [...] Read more.
Nowadays, the data flow architecture is considered as a general solution for the acceleration of a deep neural network (DNN) because of its higher parallelism. However, the conventional DNN accelerator offers only a restricted flexibility for diverse network models. In order to overcome this, a reconfigurable convolutional neural network (RCNN) accelerator, i.e., one of the DNN, is required to be developed over the field-programmable gate array (FPGA) platform. In this paper, the sparse optimization of weight (SOW) and convolutional optimization (CO) are proposed to improve the performances of the RCNN accelerator. The combination of SOW and CO is used to optimize the feature map and weight sizes of the RCNN accelerator; therefore, the hardware resources consumed by this RCNN are minimized in FPGA. The performances of RCNN-SOW-CO are analyzed by means of feature map size, weight size, sparseness of the input feature map (IFM), weight parameter proportion, block random access memory (BRAM), digital signal processing (DSP) elements, look-up tables (LUTs), slices, delay, power, and accuracy. An existing architectures OIDSCNN, LP-CNN, and DPR-NN are used to justify efficiency of the RCNN-SOW-CO. The LUT of RCNN-SOW-CO with Alexnet designed in the Zynq-7020 is 5150, which is less than the OIDSCNN and DPR-NN. Full article
(This article belongs to the Special Issue Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives)
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25 pages, 1619 KiB  
Article
Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
by Zbigniew Mudza and Rafał Kiełbik
Electronics 2022, 11(8), 1261; https://doi.org/10.3390/electronics11081261 - 16 Apr 2022
Viewed by 2236
Abstract
FPGAs can provide application-specific acceleration for computationally demanding tasks. However, they are rarely considered general-purpose platforms due to low productivity of software development and long reconfiguration time. These problems can be mitigated by implementing a coarser overlay atop the FPGA fabric. Combining this [...] Read more.
FPGAs can provide application-specific acceleration for computationally demanding tasks. However, they are rarely considered general-purpose platforms due to low productivity of software development and long reconfiguration time. These problems can be mitigated by implementing a coarser overlay atop the FPGA fabric. Combining this approach with partial reconfiguration allows for the modification of individual processing elements (PEs) of the virtual architecture without altering the rest of the system. Module relocation can be used to share implementation details between functionally equivalent PEs that use identical sets of resources, thus eliminating redundant placement and routing runs. Proper floorplanning is crucial for virtual Coarse-Grained Reconfigurable Architectures (CGRAs) with relocatable PEs considering their tendency to use nearest-neighbor connection patterns. It requires solving two problems—finding identical regions in the FPGA fabric and assigning individual partitions to certain locations. This article presents minor improvements of a state-of-the-art solution for the first and proposes a novel technique for solving the other. The proposed automated floorplanner uses modified breadth-first search with direction-based penalties to create initial floorplan consistent with geometry of logical array, then improves the result with 2-opt local optimization. Compared to simulated annealing solutions, the proposed approach allows for the reduction in the floorplanning time by two to three orders of magnitude without compromising the quality of the results. Full article
(This article belongs to the Special Issue Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives)
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22 pages, 1232 KiB  
Article
Efficient FPGA Implementation of an ANN-Based Demapper Using Cross-Layer Analysis
by Jonas Ney, Bilal Hammoud, Sebastian Dörner, Matthias Herrmann, Jannis Clausius, Stephan ten Brink and Norbert Wehn
Electronics 2022, 11(7), 1138; https://doi.org/10.3390/electronics11071138 - 3 Apr 2022
Cited by 5 | Viewed by 2814
Abstract
In the field of communication, autoencoder (AE) refers to a system that replaces parts of the traditional transmitter and receiver with artificial neural networks (ANNs). To meet the system performance requirements, it is necessary for the AE to adapt to the changing wireless-channel [...] Read more.
In the field of communication, autoencoder (AE) refers to a system that replaces parts of the traditional transmitter and receiver with artificial neural networks (ANNs). To meet the system performance requirements, it is necessary for the AE to adapt to the changing wireless-channel conditions at runtime. Thus, online fine-tuning in the form of ANN-retraining is of great importance. Many algorithms on the ANN layer are developed to improve the AE’s performance at the communication layer. Yet, the link of the system performance and the ANN topology to the hardware layer is not fully explored. In this paper, we analyze the relations between the design layers and present a hardware implementation of an AE-based demapper that enables fine-tuning to adapt to varying channel conditions. As a platform, we selected field-programmable gate arrays (FPGAs) which provide high flexibility and allow to satisfy the low-power and low-latency requirements of embedded communication systems. Furthermore, our cross-layer approach leverages the flexibility of FPGAs to dynamically adapt the degree of parallelism (DOP) to satisfy the system-level requirements and to ensure environmental adaptation. Our solution achieves 2000× higher throughput than a high-performance graphics processor unit (GPU), draws 5× less power than an embedded central processing unit (CPU) and is 5800× more energy efficient compared to an embedded GPU for small batch size. To the best of our knowledge, such a cross-layer design approach combined with FPGA implementation is unprecedented. Full article
(This article belongs to the Special Issue Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives)
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17 pages, 3990 KiB  
Article
Reconfigurable Computing for Reactive Robotics Using Open-Source FPGAs
by José M. Cañas, Jesús Fernández-Conde, Julio Vega and Juan Ordóñez
Electronics 2022, 11(1), 8; https://doi.org/10.3390/electronics11010008 - 22 Dec 2021
Cited by 6 | Viewed by 5092
Abstract
Reconfigurable computing provides a paradigm to create intelligent systems different from the classic software computing approach. Instead of using a processor with an instruction set, a full stack of middleware, and an application program running on top, the field-programmable gate arrays (FPGAs) integrate [...] Read more.
Reconfigurable computing provides a paradigm to create intelligent systems different from the classic software computing approach. Instead of using a processor with an instruction set, a full stack of middleware, and an application program running on top, the field-programmable gate arrays (FPGAs) integrate a cell set that can be configured in different ways. A few vendors have dominated this market with their proprietary tools, hardware devices, and boards, resulting in fragmented ecosystems with few standards and little interoperation. However, a new and complete toolchain for FPGAs with its associated open tools has recently emerged from the open-source community. Robotics is an expanding application field that may definitely benefit from this revolution, as fast speed and low power consumption are usual requirements. This paper hypothesizes that basic reactive robot behaviors may be easily designed following the reconfigurable computing approach and the state-of-the-art open FPGA toolchain. They provide new abstractions such as circuit blocks and wires for building intelligent robots. Visual programming and block libraries make such development painless and reliable. As experimental validation, two reactive behaviors have been created in a real robot involving common sensors, actuators, and in-between logic. They have been also implemented using classic software programming for comparison purposes. Results are discussed and show that the development of reactive robot behaviors using reconfigurable computing and open tools is feasible, also achieving a high degree of simplicity and reusability, and benefiting from FPGAs’ low power consumption and time-critical responsiveness. Full article
(This article belongs to the Special Issue Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives)
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12 pages, 547 KiB  
Article
A Novel FPGA-Based Intent Recognition System Utilizing Deep Recurrent Neural Networks
by Kyriaki Tsantikidou, Nikolaos Tampouratzis and Ioannis Papaefstathiou
Electronics 2021, 10(20), 2495; https://doi.org/10.3390/electronics10202495 - 13 Oct 2021
Cited by 2 | Viewed by 2318
Abstract
In recent years, systems that monitor and control home environments, based on non-vocal and non-manual interfaces, have been introduced to improve the quality of life of people with mobility difficulties. In this work, we present the reconfigurable implementation and optimization of such a [...] Read more.
In recent years, systems that monitor and control home environments, based on non-vocal and non-manual interfaces, have been introduced to improve the quality of life of people with mobility difficulties. In this work, we present the reconfigurable implementation and optimization of such a novel system that utilizes a recurrent neural network (RNN). As demonstrated in the real-world results, FPGAs have proved to be very efficient when implementing RNNs. In particular, our reconfigurable implementation is more than 150× faster than a high-end Intel Xeon CPU executing the reference inference tasks. Moreover, the proposed system achieves more than 300× the improvements, in terms of energy efficiency, when compared with the server CPU, while, in terms of the reported achieved GFLOPS/W, it outperforms even a server-tailored GPU. An additional important contribution of the work discussed in this study is that the implementation and optimization process demonstrated can also act as a reference to anyone implementing the inference tasks of RNNs in reconfigurable hardware; this is further facilitated by the fact that our C++ code, which is tailored for a high-level-synthesis (HLS) tool, is distributed in open-source, and can easily be incorporated to existing HLS libraries. Full article
(This article belongs to the Special Issue Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives)
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18 pages, 640 KiB  
Article
A Hardware Platform for Ensuring OS Kernel Integrity on RISC-V
by Donghyun Kwon, Dongil Hwang and Yunheung Paek
Electronics 2021, 10(17), 2068; https://doi.org/10.3390/electronics10172068 - 26 Aug 2021
Cited by 1 | Viewed by 3014
Abstract
The OS kernel is typically preassumed as a trusted computing base in most computing systems. However, it also implies that once an attacker takes control of the OS kernel, the attacker can seize the entire system. Because of such security importance of the [...] Read more.
The OS kernel is typically preassumed as a trusted computing base in most computing systems. However, it also implies that once an attacker takes control of the OS kernel, the attacker can seize the entire system. Because of such security importance of the OS kernel, many works have proposed security solutions for the OS kernel using an external hardware module located outside the processor. By doing this, these works can realize the physical isolation of security solutions from the OS kernel running in the processor, but they cannot access the inner state of the processor, which attackers can manipulate. Thus, they elaborated several methods to overcome such limited capability of external hardware. However, those methods usually come with several side effects, such as high-performance overhead, kernel code modifications, and/or excessively complicated hardware designs. In this paper, we introduce RiskiM, a new hardware-based monitoring platform to ensure kernel integrity from outside the host system. To deliver the inner state of the host to RiskiM, we have devised a hardware interface architecture, called PEMI. Through PEMI, RiskiM is supplied with all internal states of the host system essential for fulfilling its monitoring task to protect the kernel. To empirically validate our monitoring platform’s security strength and performance, we have fully implemented PEMI and RiskiM on a RISC-V based processor and FPGA, respectively. Our experiments show that RiskiM succeeds in the host kernel protection by detecting even the advanced attacks which could circumvent previous solutions, yet suffering from virtually no aforementioned side effects. Full article
(This article belongs to the Special Issue Applications of FPGAs and Reconfigurable Computing: Current Trends and Future Perspectives)
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