3.1. Simulated Structures, Models, and Parameters
In this paper, we used a Synopsys Sentaurus TCAD devices simulator [
16] to validate the proposed structure. First, the Structural Editor tool was used to design the proposed structure in
Figure 2 below. In particular, the cylindrical command of the Sentaurus tool (Rotate 360 degrees) was able to form a virtual gate-all-around (GAA) structure based on half the 2D structure in device simulation. Using these features, we were able to simulate the entire vertical channel 3D NAND string and validate and analyze the overall behavior of the proposed devices. Next, the configuration of each contact point will be explained. First, the SUB contact at the bottom controls the voltage of the filler located inside the channel, and the CSL (Common-Source-Line) contact serves as the ground for the entire string. And the GSL (Ground-Select-Line) contact located on it controls the contact between CSL and the channel, and the 10 WL (Word Line) controls the operation of each memory cell. Finally, the source-select-line (SSL) bit line (BL) controls the contact between the channel, and the top BL acts as a drain.
Figure 2b shows an enlarged view of the dimensions of the elements used in the simulated device. The oxide, nitride, and block oxide layers of the tunnel were maintained at 4, 7, and 11 nm, respectively. In addition, as verified in previous studies, regardless of the thinness of the filler, and even if the thickness becomes too thin to deliver the hole carrier, it is confirmed that the erase operation can be performed up to 5 nm through the 2-step erase method [
15]. Therefore, in this study, the thickness of the filler was set to 5 nm and the remaining area was filled with M-oxide. Thus, the total diameter of the simulation device is 100 nm. The word line gate length and the interval between successive word lines were fixed at 30 nm. While device simulation is in progress, the doping concentration dependence, high field saturation, and trap scattering mobility models were used. In addition, Shockley-Read-Hall [
17], Auger [
18], and Hurkx band-to-band recombination models [
19] were also used to simulate the operation of the transistor in a V-NAND structure. In addition, the Poole–Frenkel model [
20] and the nonlocal tunneling model [
16] were used to model the electron and hole transport in silicon nitride.
Figure 3 shows the doping concentration of the formed structure and additional information on the SSL and GSL regions. First, in the case of the SSL region shown in (a), the length of the SSL gate is set to 100 nm, and this is also the case for the GSL in (b). This is for suppression of leakage current flowing to the BL and CSL, respectively, and enhancement of gate control capability. It is known that such a structure or a plurality of gates is used in the actual 3D NAND structure. Second, the doping concentration of the pillar was set to a lower concentration (5 × 10
18 cm
−3). This is in consideration of the difficulties in the process and the change of the threshold voltage due to the increase of the doping concentration. Lastly, as illustrated in
Figure 2, unlike the SP structure of previous research [
16], the lower SUB area is composed of pure metal electrodes.
These changes can be expected to sacrifice the Peri circuit region in the previous SP structure and solve temperature problems that may occur during the process. Of course, this is also a possible structure because it is ironically difficult to deliver a large number of hole carriers in IGZO channels.
In addition, the parameters described in
Table 1 were applied to polysilicon and silicon nitride for each material trap, and
Table 2 shows the voltages applied to each operation. (Parameters other than the indicated trap parameters were basically applied from referenced papers [
13,
15,
16]). Additionally,
Figure 4 shows the result of simulating the actual measurement results of ref [
21] (
Figure 5a, VDS = 0.1 V) with simulated elements of the same scale by applying the parameters described above. As you can see, there are some differences, but we can see that the results are similar overall. These results show the reliability of the IGZO parameter used in this paper.
3.2. Simulation Results and Analysis When Applying IF Structure in COP Structure
First of all, we predicted that the following three situations will occur in the erase operation when real IGZO channels and filler structures are used in 3D NAND Flash memory through a more detailed simulation study.
Figure 5 shows an explanation of the three possibilities mentioned above: First, as shown in (
Figure 5a), if the filler and IGZO channels are not defective or problematic, the low hole characteristics of IGZO materials may not be overcome and the hole carriers may not be transferred to the IGZO channel. Of course, if a voltage much higher than the erase voltage currently in use (~30 V or more) is applied, the hole carriers may be transferred, but such an operation may be a great problem for both the channel and the filler.
Next, as shown in (
Figure 5b), the uppermost end of the filler will be once the filler is formed and then planarized by the CMP process. However, in this process, if the CMP process goes very or extremely well, a very sharp edge will be formed as shown in the red circle in the figure. At these edges, even if the same voltage is applied, a much larger electric field will be formed, and thus the transfer of the hole carrier may be possible beyond the barrier due to the material characteristics of IGZO. Of course, there is a prerequisite that the quality of the CMP process must be very good in order to achieve this, but this assumption can also be considered because the current development speed of the CMP process is very fast. Finally, as shown in (
Figure 5c), it is unlikely that the contact between the filler and the IGZO channel is absolutely flat and vertical, and rather there is a possibility that spikes may occur in the direction of the IGZO channel or in the opposite direction due to nonuniformity in the etching process or deposition process. These spikes may generate an electric field much stronger than other regions when an erase voltage is applied like the edge described above (
Figure 5b), and through this, hole carriers may be transmitted to the IGZO channel. Therefore, this study will evaluate and analyze the influence of the erase operation on these three possibilities.
Figure 6 shows the results of the erase operation according to the interface state between the IGZO channel and the filler. First, when the interface state of the two materials is the most ideal, ironically, it shows the slowest erase operation speed. This result means that the hole carriers were not transferred to the IGZO channel through the filler at all, and the erase operation was purely an emission of electrons by the E-field. Next, where only one edge is present at the tip of the filler by the CMP process, it shows a faster operating speed than the previous result. Therefore, in this result, it can be confirmed that a small amount of hole carriers were supplied to the IGZO channel through a slight hole emission at the tip of the filler. Finally, the result of 1 edge + 6 spikes is the result of forming 6 spikes at arbitrary positions in the structure (
Figure 5c) and performing the erase operation.
Simulation results show the fastest erase operation speed as expected, and this result shows that hole carriers are discharged due to the same phenomenon in spikes as well as at the tip of the filler, and the erase operation is performed through it. Therefore, based on these results and the contents of
Figure 1, the interface state between the filler and the IGZO channel would be ideal in the case where the erase speed in the 3D NAND flash memory with the IGZO channel and filler structure was the slowest, and in the case of the fastest, 1 edge +, it can be assumed that it will be in the state of 6 spikes. Of course, in the actual device, many more spikes may be formed than the simulation result, thereby releasing many hole carriers.
However, if a certain level of hole carrier is filled in the channel, the voltage of the channel will increase, and the E-field will be weakened due to the voltage difference between the filler and the IGZO channel so that the hole carriers cannot move. Therefore, increasing the spikes does not increase the erase rate indefinitely and it will eventually stagnate.
The results in
Figure 7 can specifically explain the previously assumed content. First, in (
Figure 7a–c), it can be observed that the interface where many spikes are generated delivers more hole carriers to the IGZO channel than the ideal interface. However, this does not mean that all hole carriers are filled in the channel like the Polysilicon channel, and as shown in the cross-sectional result (
Figure 7c), the density at which hole carriers can actually transmit voltage is filled to only 2 nm near 40 nm, which is the interface with the tunnel oxide. Therefore, as shown in the voltage distribution from (
Figure 7d–f), the voltage drop is of course very severe in the ideal interface state, but even in the presence of spikes, the voltage rise increased by only 6.3 V. Therefore, it can be seen that the channel voltage at this time, specifically the voltage at the tunnel oxide contact surface, is 13.7 V, and the difference from the filler voltage of 18 V is only about 4.3 V. In other words, when such a small voltage difference is formed, it can be confirmed that the hole carriers can no longer overcome the low hole characteristics of IGZO and cannot be transmitted to the channel.
These results indicate, as we explained earlier, that it is meaningless to form many spikes to increase the erase operation efficiency, and also why it is not necessary to supply the hole carrier from the crystal sub to the filler at the expense of the peri circuit area. Simply put, hole carriers that can be transferred to the IGZO channel or necessary hole carriers can only fill a thickness of 1–2 nm at the interface between the tunnel oxide and the channel, and these filled hole carriers increase the voltage of the channel but at the same time reduce the voltage difference between the filler and the channel. This reduced voltage difference eventually makes it impossible to transfer the hole carrier to the channel, and the increase in the hole carrier density of the channel becomes stagnant. Thus, the interface state of the filler and IGZO channels in the proposed structure should not be an unconditional ideal state, but it also does not require numerous spikes for hole carrier transmission. Currently, it is difficult to control the process for forming these spikes due to process limitations, but if process technology develops thereafter, it will be possible to precisely control the proper formation of the spike and secure maximum erasing efficiency.
Through the previous results, we confirmed that even if realistic process conditions are applied, the proposed structure overcomes the adverse hole-related characteristics of IGZO in the 3D NAND flash memory structure to which the IGZO channel is applied and enables a fast erase operation. Next, we will examine the points that may be of concern with respect to the application of the IGZO channel and the filler structure. The first thing to be considered before applying the proposed IF structure is whether the leakage current increases. This is because, although considered and verified in the IP structure of previous studies, when the pillar and the channel are in direct contact, the pillar itself becomes a pass for the leakage current and there is a possibility of increasing the leakage current.
First, as illustrated in
Figure 8a, the leakage current in the reading operation is about 10
−15 A, which is well maintained at low leakage current characteristics. This is one of the advantages of IGZO materials, compared to the existing 3D NAND Flash structure using the PolySilicon channel that is about 10
−13 A [
15]. In particular, a leakage current to the SUB contact is 10
−20 A, which is actually 0, and if the filler thickness is sufficiently thin, it is expected that the leakage current would not occur in this direction regardless of the filler doping concentration.
Next, the channel potential change shown in (b) represents a channel-boosting performance change to inhibit programming behavior on an unselected string when the program operation is performed on the selected string in the 3D NAND structure [
22]. This “self-boosting” technique is an operation of increasing a channel voltage within a string sharing the same BL among strings to be programmed to suppress programming behavior [
22].
Assuming the string to which the corresponding action is applied, it can be observed that when the filler thickness is 5 nm in the proposed IGZO channel + IF structure, the channel potential is 1.5 V lower than the general 3D NAND structure. This phenomenon is thought to be affected by the channel potential directly connected to the column because the sub-contact connected to the column is in the ground state. On top of that, since the IGZO channel itself has a weak N-type characteristic and an average carrier density of about 1017 cm−3, it is considered that an additional voltage drop occurs. However, even in the IGZO channel + Filler structure, the channel voltage could be raised to 14.2 V through the self-boosting technique, and at this voltage, the difference from the program operating voltage of 20 V is only 5.8 V, so it seems that the original role of preventing program operation can be sufficiently performed.
Finally,
Table 3 shows the results of comparing the typical 3D NAND with the strengths and weaknesses of the proposed structure. First, in the case of program operation speed, it is expected that all three structures to be compared will be almost the same. This is because the voltage of the channel in the program operation is fixed in the GND state, so the factors that affect the program operation performance are the type and quality of the ONO layer and WL metal, and basically, all three structures are the same structure and process. Second, in the case of erase operation speed, it can be seen that the proposed IF structure is absolutely excellent. In particular, these advantages will be able to stably solve the problem of erasure speed degradation that may occur when gate stacks of 300 to 500 or more are used due to future technological advances. This is because the filler that supplies hole carriers in the proposed IF structure is basically doped with P-type, so it is hardly affected by the increase in height. Third, the leakage current, which was feared to be a problem of directly coupling the filler to the channel, confirmed a very small leakage current of 10
−15 A by properly controlling the doping concentration of the filler in addition to the inherent low leakage current characteristics of the IGZO material. This can be expected to dramatically reduce standby power consumption, one of the most important considerations, especially for mobile devices. Forth, it has been confirmed that the self-boosting performance is about 1.5 V lower than that of a typical 3D NAND flash structure. However, this lowered channel boosting voltage is only a 5.8 V difference from the program voltage, so it is expected that the original role of preventing the program from operating will be performed without any problems.
Finally, if you compare the three structures in terms of the manufacturing process, the SP structure proposed in the previous study first needs to deliver hole carriers to the filler from the crystal sub-area at the bottom, so two types of filler structures are required for this. Therefore, there was a problem that the Peri circuit area was sacrificed and the process cost was greatly increased compared to the existing 3D NAND structure. However, in the case of the new IF structure proposed this time, the erase operation is possible with only a small amount of hole carriers by reversely using the material properties of IGZO, so the cost of increasing the process can be minimized because only one filler adjacent to the channel is sufficient.