Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
Round 1
Reviewer 1 Report
I find that the paper is well-organized and presents valuable insights. However, there are several areas that require revisions. Please consider the following suggestions to improve the overall quality of your work:
DUT Device Structure:
To enhance readers' understanding of the tested device, particularly the significance of the "M" parameter, it would be beneficial to include a basic schematic diagram illustrating the fundamental structure of the DUT (Device Under Test). This schematic can assist readers in visualizing the device's components and their relationship to the discussed parameters.
Specific Details of Measurement and Comparison:
In the methodology section, it is important to provide specific details about the equipment used for testing and comparisons. This should include information such as the make and model of the instruments, their specifications, and any relevant settings or configurations. These details are essential for ensuring the reproducibility of the study and allowing readers to evaluate the validity of the results.
Author Response
DUT Device Structure:
To enhance readers' understanding of the tested device, particularly the significance of the "M" parameter, it would be beneficial to include a basic schematic diagram illustrating the fundamental structure of the DUT (Device Under Test). This schematic can assist readers in visualizing the device's components and their relationship to the discussed parameters.
Added Figure 5, which shows the layout of a finfet transistor with the parameters Nfins, Nfing, Lg and M.
Specific Details of Measurement and Comparison:
In the methodology section, it is important to provide specific details about the equipment used for testing and comparisons. This should include information such as the make and model of the instruments, their specifications, and any relevant settings or configurations. These details are essential for ensuring the reproducibility of the study and allowing readers to evaluate the validity of the results.
Created dedicated section for measurement setup (section 4) and added following text:
“The measurement setup consists of a Cascade 300mm Probe Station, a Keysight N5227A PNA Vector Network Analyzer (VNA) with frequency range from DC up to 67 GHz and Cascade Infinity RF GSG probes for on-wafer probing with frequency range from DC up to 110 GHz In order to be able to measure the S-parameters up to 110 GHz, the frequency range of the VNA is extended using a Keysight N5250CX10 millimeter-wave module for each port. The output of the mmW module and the input of the RF probes are connected using 1-mm coaxial cables for higher-order mode suppression. For the 2-port S-parameter measurement the VNA was calibrated up to the probe tips using a standard 2-port short-open-load-thru (SOLT) method. A block-diagram and a picture of the measurement setup are shown in Fig.\ref{fig:meas_setup_block_diagram} and \ref{fig:meas_setup_photo} respectively. The measurement was carried out with RF input power Pin = -20dBm at both ports, for values of the gate bias voltage Vg ranging between 0V and 0.8V and, only for the standard structure, with drain bias voltage VDD = 0.8V.
Added also a picture and a block-diagram of the measurement setup (Fig.6)
Reviewer 2 Report
In this work, the authors proposed capacitor-like structures to measure gate resistance of radio-frequency (RF) transistors. Furthermore, the authors compared the capacitor-like structures with standard structures. This work is of interest to other researchers in scientific and engineering community of RF transistors. However, there are a few comments to be addressed. The detailed comments are as follows:
1) GaN semiconductor has potential application in RF transistors. It would be great if the authors include these developments and achievements in the introduction, so to give the readers a much broader view. Recent development concerning on the MOCVD epitaxy of GaN semiconductor, such as Laser & Photonics Reviews 2023, 17, 2200455 (https://doi.org/10.1002/lpor.202200455), should be added, so that the readers can be clear about the state-of-the-art of this topic.
2) Please add more detailed information about the simulation for gate resistance, such as simulation parameters, physical model, and simulation software.
3) There are several undefined abbreviations in the manuscript, such as DUT, FinFET, GSG, and RC. It is difficult for researchers in other fields to understand these technical terms.
4) In Table 1, Nfing is not defined in the manuscript. What is meaning of Nfing? What are the differences between Nfing and Nfins?
5) I suggest add the illustration of capacitor-like structures and standard structures on the 16 nm FinFET test chip, and label the Nfins, Nfing, Lg, and M on the illustration. This would make it much more accessible.
6) In figure 6, we can observe that when the Vg increases, the relative deviation of measured gate resistance decreases. What are the reasons behind the phenomenon?
7) In the “Conclusion” section, the authors conclude that capacitor-like structures and standard structures exhibit similar variance over frequency. However, we can find in figure 8 that when the value of M is eight, the capacitor-like structures possess lower variance over frequency in comparison with standard structures. What are the reasons behind the contradictory result?
Author Response
1) GaN semiconductor has potential application in RF transistors. It would be great if the authors include these developments and achievements in the introduction, so to give the readers a much broader view. Recent development concerning on the MOCVD epitaxy of GaN semiconductor, such as Laser & Photonics Reviews 2023, 17, 2200455 (https://doi.org/10.1002/lpor.202200455), should be added, so that the readers can be clear about the state-of-the-art of this topic.
Added sentence in the introduction (“This has made them in many ways competitive with the more performant and expensive III-V semiconductor processes like GaN”) and cited the suggested paper.
2) Please add more detailed information about the simulation for gate resistance, such as simulation parameters, physical model, and simulation software.
Added following sentence in section 4:
“The simulation setup consists of a standard 2-port S-parameter analysis with frequency range from DC up to 110 GHz, which is carried out using the Spectre simulator and the RF transistor models from the PDK.”
3) There are several undefined abbreviations in the manuscript, such as DUT, FinFET (no way to spell out), GSG, and RC. It is difficult for researchers in other fields to understand these technical terms.
Fixed almost all, except for FinFET (not aware of a way to spell it out)
4) In Table 1, Nfing is not defined in the manuscript. What is meaning of Nfing? What are the differences between Nfing and Nfins?
Added definition of Nfing in the text. Added also Fig.5, which illustrates the various device parameters, including Nfins and Nfing.
5) I suggest add the illustration of capacitor-like structures and standard structures on the 16 nm FinFET test chip, and label the Nfins, Nfing, Lg, and M on the illustration. This would make it much more accessible.
Added Fig.5. It is just the layout of a FinFET transistor, regardless of whether it is a capacitor-like or standard structure.
6) In figure 6, we can observe that when the Vg increases, the relative deviation of measured gate resistance decreases. What are the reasons behind the phenomenon?
I modified the plot replacing Delta_Vg with abs(Delta_Vg), so that it becomes more visible that the smallest deviation is obtained for Vg = 0.4V. The reason is explained in the newly added section 2:
“This model is based on a distributed representation of the MOS structure which can not be easily integrated in a compact model of the transistor. In such a model indeed it is preferred to use only one node for each terminal to prevent long simulation times at circuit level. For this reason the various contributions in (\ref{eq:Rg_components}) are typically absorbed into a single lumped resistance $R_g$ placed at the input of the equivalent circuit \cite{enz2000mos}. Since each component of the model has to be bias-independent, the dependency of $R_{ch}$ on $V_g$ is typically sacrificed, and the value at one typical $V_g$ operating point is chosen.”
The explanation goes in more details in section 5:
“This section focuses on the analysis of the capacitor-like structure. The plot of Rg vs frequency for Vg = 0.4V in Fig.\ref{fig:Rg_Zstruct_hyd_dut27} shows very good agreement with the foundry model over the entire frequency range. On the other hand the plot of |Delta_Rg| over frequency for different bias conditions in Fig.\ref{fig:delta_Rg} shows that the best agreement between measurement and simulation is obtained for Vg = 0.4V The reason is that, as explained in section \ref{Gate_resistance}, the dependency of Rch on Vg is neglected in the model, and a single value at a "convenient" Vg is taken. Based on these data, the chosen bias point seems to be Vg = 0.4V which is a reasonable choice, as it was observed to be the bias condition which optimizes ft. In practice, since the RF transistor is biased most of the times either exactly at Vg = 0.4V or at a value close to it, the error introduced by this approximation is small.”
7) In the “Conclusion” section, the authors conclude that capacitor-like structures and standard structures exhibit similar variance over frequency. However, we can find in figure 8 that when the value of M is eight, the capacitor-like structures possess lower variance over frequency in comparison with standard structures. What are the reasons behind the contradictory result?
I added the explanation below, which goes more into details:
“It can be observed that the measurements performed with the two structures show a variation over frequency between 2\% and 10\%. In most cases the variation is between 2\% and 5\%, with the exception of the capacitor-like structure with M=1 and the standard structure with M=8, which show up to 7\% and 10\% deviation respectively. This shows that the standard structure with large M and the capacitor-like structure with small M represent the worst case not only in terms of agreement with the model, as discussed in sections \ref{Capacitor_structures} and \ref{Comparison}, but also in terms of frequency stability.”
Reviewer 3 Report
The manuscript looks good except for one issue: what's the impact of process variations (such as gate length) on the gate resistance? Please simulate and describe/analyze it.
Author Response
The manuscript looks good except for one issue: what's the impact of process variations (such as gate length) on the gate resistance? Please simulate and describe/analyze it.
Added Montecarlo simulations in section 5, Figure 7 and following text:
“In Fig.\ref{fig:Rg_Zstruct_vs_Nfins_Lg} the measured $R_g$ is compared to simulations as a function of the geometrical parameters $N_{fins}$ and $L_g$. In order to capture the device-to-device (mismatch) variations and the die-to-die, wafer-to-wafer and lot-to-lot (process) variations, Montecarlo simulations with 2000 samples are run for each set of parameters. The results are displayed in 3 different curves: the mean value $\mu(R_g)$ of the gate resistance and the so-called $\pm3\sigma$ curves, i.e. the quantities $\mu(R_g)\pm3\sigma(R_g)$, where $\sigma(R_g)$ is the variance of $R_g$. These are relevant because they define the interval in which $R_g$ falls with a probability of 99.7\%, and therefore provide a good estimation of the process and mismatch variation. The measured data shows very good correlation with $\mu(R_g)$ and lies completely in the interval delimited by the $\pm3\sigma$ curves. Based on these simulation results, an overall $R_g$ fluctuation of up to 55\% above or below the mean value is expected. One interesting observation from Fig.\ref{fig:Rg_Zstruct_vs_Lg} is that the spread of $R_g$ becomes tighter for large values of $L_g$. This is expected because $L_g$ is one of the transistor parameters which is mostly affected by the process variation. Since the fluctuation $\delta L_g$ is independent of $L_g$, its impact decreases as $L_g$ gets larger.”
Reviewer 4 Report
An alternative de-embedding method of parameters of transistors for RF and millimeter-wave applications is proposed in the paper. The method requires only open de-embedding.
Comments
1) Page1, line 20 – 21: “…the standard common-source structure with open-short de-embedding is always used”. Open-short de-embedding method is not the only type of de-embedding methods studied in research papers. For example, another type of the de-embedding method studied in a research paper [R1] is "Thru-Short-Open" one. This technique should also be mentioned in your paper and used in the comparative analysis.
2) It is required to describe the experimental setup in more details. Please, show also a photo and block or circuit diagram of the setup.
3) Check expression (3). If it represents mean value then it is incorrect because in this case division by N is omitted.
[R1] J.Y. Kim, M.K. Choi, and S. Lee “A “Thru-Short-Open” De-embedding Method for Accurate On-Wafer RF Measurements of Nano-Scale MOSFETs”, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.12, NO.1, MARCH, 2012.
Minor editing of English language required.
Author Response
An alternative de-embedding method of parameters of transistors for RF and millimeter-wave applications is proposed in the paper. The method requires only open de-embedding.
Comments
1) Page1, line 20 – 21: “…the standard common-source structure with open-short de-embedding is always used”. Open-short de-embedding method is not the only type of de-embedding methods studied in research papers. For example, another type of the de-embedding method studied in a research paper [R1] is "Thru-Short-Open" one. This technique should also be mentioned in your paper and used in the comparative analysis.
Added a paragraph in the introduction, where this paper is cited:
“One key aspect in device characterization at mmW frequencies is the de-embedding of the on-chip interconnect parasitics, which are caused mainly by the pads and feedlines. Most of the traditional de-embedding methods are based on a lumped representation of the parasitics and make use of one or more de-embedding structures to eliminate their contributions and extract the behavior of the device under test (DUT). The most popular is the open-short method \cite{koolen1991improved}, which is used as reference in this article. The main limitation of the lumped methods is that they neglect the distributed nature of the interconnects at high frequency. In order to partially take this effect into account, some more refined method have been devised \cite{kim2012thru,tiemeijer2005comparison}, which achieve higher accuracy but requires additional de-embedding structures.”
Adding the thru-short-open de-embedding methodology to the analysis is unfortunately not possible because we didn’t tape-out test structures for it. Moreover, it is in my opinion somehow beyond scope, since most of the point of this article is to be able to measure the gate resistance with fewer de-embedding structures to save area.
2) It is required to describe the experimental setup in more details. Please, show also a photo and block or circuit diagram of the setup.
Created dedicated section for measurement setup (section 4) and added following text:
“The measurement setup consists of a Cascade 300mm Probe Station, a Keysight N5227A PNA Vector Network Analyzer (VNA) with frequency range from DC up to 67 GHz and Cascade Infinity RF GSG probes for on-wafer probing with frequency range from DC up to 110 GHz In order to be able to measure the S-parameters up to 110 GHz, the frequency range of the VNA is extended using a Keysight N5250CX10 millimeter-wave module for each port. The output of the mmW module and the input of the RF probes are connected using 1-mm coaxial cables for higher-order mode suppression. For the 2-port S-parameter measurement the VNA was calibrated up to the probe tips using a standard 2-port short-open-load-thru (SOLT) method. A block-diagram and a picture of the measurement setup are shown in Fig.\ref{fig:meas_setup_block_diagram} and \ref{fig:meas_setup_photo} respectively. The measurement was carried out with RF input power Pin = -20dBm at both ports, for values of the gate bias voltage Vg ranging between 0V and 0.8V and, only for the standard structure, with drain bias voltage VDD = 0.8V.
Added also a picture and a block-diagram of the measurement setup (Fig.6)
3) Check expression (3). If it represents mean value then it is incorrect because in this case division by N is omitted.
Corrected
Round 2
Reviewer 4 Report
The authors have responded satisfactorily to all of my original comments and I am now happy to recommend the paper for publication.
