Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test

Round 1

Reviewer 1 Report

memristors offer a new approach to design DFFs with improved performance. 5 Herein,Adopt the design method of MRL we propose two simplified-edge-triggered DFFs that utilize 6 the signals transmitted in the two-stage inversion again to reduce the number of devices. In addition, 7 two new 4-bit LFSRs were designed and verified using the proposed DFFs. Compared to the partially 8 existing LFSRs, the designed LFSRs reduce the number of devices significantly, decrease power 9 consumption by 32.7% and 33.3%, and increase delay time by 34.5% and 30.7% for NOR and NAND 10 gates, respectively. Finally, the proposed falling-edge-triggered DFF is used to implement the major 11 blocks of the BIST circuit, and simulation results confirm their correctness and feasibility.

This work is well written and can be considered for publication in current form.

 

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 2 Report

The authors of the paper "Memristor based D-Flip-Flog Design and Application in Built-In

Self-Test" presents the memristor design of DFF-based applications. In this version the paper does not meet the criteria for publication in the following causes:

 

1. In the introduction there are not enough references covering the topic. Mainly the contribution of this study to the literature in this field is not present. To remedy this, I recommend the authors to clearly specify the contribution and the novelty elements in this article in the last part of introduction.

2. A standard publication rule of providing sufficient details of the method and equipment, simulators so that the results can be reproduced is impossible.

3. The paper itself refers to simulations and these simulations are at the laboratory level for students and many memristor models are already available for all SPICE simulators, especially LTspice.

4. The proposed solutions are inspired at almost identical level with logic circuits from traditional technology outside bringing real novel elements. It is easy to recognize the classical topology of the standard circuits. Basically, they are classical logic circuits in which the advantages of the presence of a memristor are speculated.

5. The introduction of the memristor in the input block must be motivated, which technologically will not be easy for the industry to find in the end a hybrid technology that will increase the problems of large-scale production without substantial benefits.

6. The new performances suggested in the article will be surpassed in conventional technology without resorting to a hybrid technology.

7. The proposed combinations of DFF with memristor have been known for about 80 years since the beginning of TTL technology.

8. An article should contain elements of theoretical modelling in relation to novel elements, followed by simulation and experimentally validated. From this perspective the paper is limited to simulation and the simulation is incompletely presented without listing the exact SPICE models used and the working environment.

9. Concluzions are present but without a validation or comparative study with other results in the literature to justify the publication of this paper.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

-Other than errors in the text, surprisingly there is a typo error in the title of the manuscript!!!

-Re-write this sentence in the abstract because it is not clear "Herein,Adopt the design method of MRL we propose two simplified-edge-triggered DFFs that utilize 6 the signals transmitted in the two-stage inversion again to reduce the number of devices".

-Authors claim getting lower power but higher delay for proposed NOR and NAND gates, so what the advantage are for this design?

-Compare the power-delay product of your design with others to show your design advantages.

-Other than simulation results, the parameters of the proposed DFFs must be summarized and presented in a table format. 

-Are the DFFs in Fig.4 high or low level sensitive type? The simulations graphs in Fig. 5 are not consistent, please revise them and  specify if they are low or high level sensitive.   

English editing of the manuscript by an expert is required

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

The authors of the revised version of the paper “Memristor based D-Flip-Flop Design and Application in

 

Built-In Self-Test” followed the recommendations on the first version of this article. In this form the DFF investigation carried out in LTspice, BIST adds clarity by highlighting the originality of the work. I recommend that the paper be accepted for publication in revised form.

 

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 3 Report

-The study is not complete, load must be added and the DFFs must characterized with load.

-The power-delay product calculations must be explained.

-Check any logic design text book to find out the DFFs parameters.

The manuscript cannot be accepted, it still lacks a lot works. 

Author Response

Please see the attachment.

Author Response File: Author Response.pdf